Design of an automatic gain control loop for high speed communication

This paper presents the design of an automatic gain control (AGC) loop for high-speed communication systems, which can be used in wired, wireless, or optical receiver. The design is performed in 130 nm SiGe BiCMOS technology. A Gilbert cell-based variable gain amplifier is designed, which shows approximately linear gain control with respect to the gain control voltage. The variable gain amplifier is followed by two fixed gain cascode amplifiers. Then, a full wave rectifier-based peak detector is designed and analyzed. To reduce the peak detector error, a compensation technique is applied. Finally, an operational amplifier is designed, which is used as voltage adder and comparator. The designed AGC loop is simulated with sinusoidal and pseudorandom binary sequence (prbs) input signal with high frequency signal of 1 to 30 GHz. The simulation results of the AGC loop show that a gain tuning range of 47 dB (−7 to 40 dB) is obtained in this design. It is also seen that the reference signal can be varied from 50 to 200 mV. This AGC works in the input voltage signal range between 3 mV peak and 230 mV peak, and the power dissipation of is 79 mW.     

90 dB, 90 MHz, 30 mW CMOS OTA for a high capacitive load

The design of simple gain‐enhancement configurations for cascode transistors is presented. Applying one‐ or two‐stage differential amplifiers or an improved regulated cascode configuration in the feedback loop of a cascode, allows high‐speed and high‐gain super‐transistors at low voltage to be designed. These concepts were implemented in a symmetrical OTA resulting in a measured 90 dB, 90 MHz, 30 mW amplifier performance for a.14 pF load. Settling measurements to 0·1% error for a unity‐gain configuration are presented. Copyright © 1999 John Wiley & Sons, Ltd.     

A front‐end receiver with a dual cross‐coupling technique for MICS applications

This paper presents a front‐end receiver with a dual cross‐couple technique for Medical Implant Communication Services M applications, using a standard complementary metal‐oxide semiconductor process. A lower‐power design is achieved using a resistive feedback, g_m‐boosting technique along with a current reuse topology in the receiver's transconductance stage. In addition, a dual cross‐coupling configuration applied at the input stage increases overall gain performance and reduces power consumption. The measured power dissipation of the low‐noise amplifier is only 0.51 mW. The conversion gain of the receiver is 19.74 dB, while the radio frequency and local oscillator frequencies are respectively 403.5 and 393.5 MHz, and the LO power is 0 dBm. The chip exhibits excellent isolation below −70 dB from LO to intermediate frequency and LO to radio frequency. Copyright © 2016 John Wiley & Sons, Ltd.     

A 0.7‐dB NF, +8.2‐dBm IIP3 CMOS low noise amplifier using frequency selective feedback

A CMOS amplifier employing the frequency selective feedback technique using a shunt feedback capacitor is designed and measured. The proposed amplifier can achieve a high IIP3 (input referred third‐order intercept point) by reducing the third‐ and second‐order nonlinearity contributions to the IMD3 (third‐order intermodulation distortion), which is accomplished using a capacitor as the frequency selective element. Also, the shunt feedback capacitor improves the noise performance of the amplifier. By applying the technique to a cascode LNA using 0.18‐µm CMOS technology, we obtain the NF of 0.7 dB, an IIP3 of +8.2 dBm, and a gain of 15.1 dB at 14.4 mW of power consumption at 900 MHz. Copyright © 2015 John Wiley & Sons, Ltd.     

Multiple output differential OTA with linearizing bulk‐driven active‐error feedback loop for continuous‐time filter applications

A CMOS circuit realization of a highly linear multiple‐output differential operational transconductance amplifier (OTA) has been proposed. The presented approach exploits a differential pair as an input stage with both the gate and the bulk terminals as signal ports. For the proposed OTA, improved linearity is obtained by means of the active‐error feedback loop operating at the bulk terminals of the input stage. SPICE simulations of the OTA show that, for 0.35 µm AMS process, total harmonic distortion at 1.36Vpp is less than 1% with dynamic range equal to 60.1 dB at power consumption of 276 μW from 3.3 V supply. As an example, both single output and dual differential OTAs are used to design third‐order elliptic low‐pass filters. The cut‐off frequency of the filters is 1 MHz. The power consumption of the OTA‐C filter utilizing the dual output differential OTA is reduced to 1.24 mW in comparison to 2.2 mW consumed by the single output differential OTA‐C filter counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

Positive feedback for gain enhancement in sub‐100 nm multi‐GHz CMOS amplifier design

The use of positive feedback as a solution to intrinsic gain degradation in scaled CMOS technologies, such as 65 nm and below, is discussed in detail. Criteria for increasing gain while keeping the system stable are derived using a positive feedback amplifier model. These criteria are shown to provide significant gain enhancement in silicon. This work extends the previously reported DC gain analysis to include evaluation of additional effects of positive feedback as well an investigation of the frequency behavior using S‐parameter measurements in silicon. These S‐parameter measurements of fully differential positive feedback amplifiers designed in TSMC's 65 nm technology show gain enhancements of up to 26.7 dB at frequencies up to 8.5 GHz. Copyright © 2013 John Wiley & Sons, Ltd.     

Spectral Linewidth Reduction in Widely Wavelength Tunable DFB Laser Array

We have developed an L-band tunable distributed feedback laser array (TLA) with a new design to reduce the spectral linewidth. A wide wavelength tuning range of $sim$40 nm is obtained with a high fiber output power of 20 mW and a high side-mode suppression ratio of ≫50 dB in the TLA module. A narrow linewidth of less than 580 kHz is achieved over the entire tuning range. Furthermore, we investigated the causes of linewidth variation. We found that a TLA with a longer cavity is more tolerant to external feedback, which reduces the variation in linewidth.      

A low-power 75 dB digitally programmable variable-gain amplifier in 0.18μm CMOS

Variable-gain amplifiers (VGAs) are essential building blocks of many communication systems. In this paper, a monolithic low-power digitally programmable VGA with 75 dB of gain range is presented. The core of the design is based on a low-distortion source-degenerated differential amplifier structure. The gain is varied by changing the source-degeneration resistor and tuning the resistors in the common-mode feedback circuitry. The complete VGA consists of three gain stages. As a proof of concept, a 24 dB single-gain stage with 2 dB gain steps is fabricated in a 0.18 ?m CMOS technology. The prototype chip is tested, and measurement results are obtained. Based on these results, the gain stage is redesigned to optimize its performance, and a three-stage 75 dB VGA is designed and simulated. Each stage has a digitally tunable gain range of 25 dB. The overall gain can be varied from ?15 dB to 60 dB in 2.5 dB gain steps. The bandwidth of the multi-stage VGA is higher than 140 MHz, and the gain error is less than 0.3 dB. The overall VGA draws 6.5mA from a 1.8V power supply. The noise figure of the system at maximum gain is 12.5 dB, and the third-order intermodulation intercept point (IIP3) at minimum gain is 14.4 dBm.     

定向耦合器反馈型短波低噪声高线性放大器设计

利用双极性晶体管采用定向耦合器负反馈的形式设计了一款适用于短波超宽带接收机的低噪声高线性放大器。负反馈技术拓展了动态范围以及增益平坦度,定向耦合器的低损耗以及隔离吸收对噪声和输入输出端的匹配有很大改善。该放大器射频应用频率是1.5~100MHz,覆盖了6个倍频程。测试结果表明:放大器增益13dBm,噪声低于2.7dB,输出三阶截点高于43dBm,1dB压缩点高于26dBm,,输出二阶截点高于80dBm。     

A new result in negative-feedback theory,and its application to audio power amplifiers

A nest of differentiating loops is described by means of which a very large amount of negative feedback can be applied to a specified stage in an amplifier (normally the output stage) with progresively less being applied to other stages. The effects of nonlinearity (other than hard limiting) in the specified stage can be virtually eliminated. The structure enables Bode's limit for loop-gain roll-off to be exceeded for the specified stage; both the frequency up to which loop gain is maintained constant and the frequency at which loop gain falls through unity are free design variables. As a result, practical difficulties associated with excess phase shift in low-frequency power transistors are minimized. The structure does not increase the susceptibility to transient overload and the resulting intermodulation. A practical amplifier using output transistors with fT～2 MHz has an output-stage loop gain of 25,000 (88 dB) at 20 kHz and 0.002 per cent harmonic distortion.     

流水线模数转换器设计

设计了一款14位、125MS/s流水线模数转换器(ADC)。通过前端采样/保持电路(SHA)消除对输入信号采样的孔径误差,采用4位结构的首级转换电路提高ADC线性性能,设计了带输入缓冲的栅压自举开关以缓解首级转换电路输入采样开关中自举电容对SHA的负载效应,流水线ADC级间通过逐级按比例缩减策略使功耗得到节省。该设计采用0.18μm 1P5MCMOS工艺,ADC版图面积2.3 mm×1.4 mm。Spectre后仿真结果显示,采样频率125 MHz、输入信号在接近Nyquist频率(61MHz)处时信号噪声畸变比(SNDR)和无杂散动态范围(SFDR)可分别达到75.7 dB和85.9 dB。在1.8V电源电压下,ADC核心部分功耗为263 mW。     

Ce3+:LiCaAlF6 crystal for high-gain orhigh-peak-power amplification of ultraviolet femtosecond pulses and newpotential ultraviolet gain medium: Ce3+:LiSr0.8Ca0.2AlF6

To develop high-peak-power ultrashort pulse laser systems in the ultraviolet region, a large Ce³⁺:LiCaAlF₆ (Ce:LiCAF) crystal, a tunable ultraviolet laser medium with large saturation fluence and broad gain spectrum width, was grown successfully with a diameter of more than 70 mm. To demonstrate high small signal gain, a four-pass confocal amplifier with 60 dB gain and 54 μJ output energy was constructed. Chirped pulse amplification (CPA) in the ultraviolet region was demonstrated using Ce:LiCAF for higher energy extraction. A modified bow-tie-style four-pass amplifier pumped by 100-mJ 266-nm 10-Hz pulses from a Q-switched Nd:YAG laser had 370-times gain and delivered 6-mJ 290-nm pulses. After dispersion compensation, the output pulses can be compressed down to 115 fs. This is the first ultraviolet, all-solid-state high-peak-power CPA laser system using ultraviolet gain media, and this demonstration shows further scalability of the Ce:LiCAF CPA system. Additionally, a new gain medium, Ce³⁺ :LiSr_0.8Ca_0.2AlF₆, with longer fluorescence lifetime and sufficient gain spectrum width over 18 nm was grown to upgrade this system as a candidate for a final power amplifier gain module     

Design of 3.1 to 10.6 GHz ultra‐wideband flat gain LNA

In this paper, a new ultra‐wideband low‐noise amplifier (LNA) is proposed. The proposed LNA has flat gain and low noise figure (NF) in the frequency range of 3.1 to 10.6 GHz. To obtain higher gain, cascode architecture is used. In this design, to have a lower NF, the noise cancellation technique applies to the cascode architecture. In addition, to have better matching at the input and output, active feedback and matching transistors are used, which also leads to better NF. To have flat gain, RLC load is used. In the proposed LNA, only one inductor is used, which leads to the smaller chip area. The proposed circuit is designed in 90 nm CMOS technology. The simulation shows NF of between 1.62 and 2.1 dB, flat gain between 11.9 and 12 dB and power consumption of 11.72 mW in the frequency range of 3.1 to 10.6 GHz. The simulation results support the theoretical predictions. Copyright © 2017 John Wiley & Sons, Ltd.     

0.03～4.5GHz超宽带低噪声放大器设计与实现

采用负反馈和均衡器结构,选用Avago公司生产的增强型高电子迁移率晶体管ATF55143,利用ADS软件设计、仿真和优化,最终实现了一款覆盖0.03~4.5 GHz频段的低噪声放大器,该模块中的低噪声放大器使用分立元件搭建,匹配电路调试灵活,满足了模块对输入输出驻波的高要求。其增益大于25 d B,平坦度小于等于±0.9 d B,噪声系数小于1.2 d B,输入输出驻波比小于1.75。该放大器模块体积小巧,成本较低,调试灵活,可望在通讯领域得到广泛应用。     

A low‐power four‐stage amplifier for driving large capacitive loads

A four‐stage amplifier with a new and efficient frequency compensation topology is presented in this paper. The new compensation scheme applies a Miller capacitor as the main negative feedback, a resistor and a capacitor in series as a load for one of the intermediate stages, and two feedforward paths. In order to design the amplifier and acquire circuit parameters, small signal analyses have been carried out to derive the signal transfer function and the pole‐zero locations. The proposed amplifier was designed and implemented in a standard 90 nm CMOS process with two heavy capacitive loads of 500 pF and 1 nF. The simulation results show that when driving a 500 pF load, the amplifier has a gain‐bandwidth product of 18 MHz consuming only 40.9 μW. With a 1 nF capacitive load, the proposed amplifier achieves 15.1 MHz gain‐bandwidth product and dissipates 55.2 μW from a single 0.9 V power supply. Copyright © 2013 John Wiley & Sons, Ltd.     

Design and simulation of novel amplifier‐based mixer for ISM band wireless applications

This letter describes a low‐voltage low‐power (LV‐LP) 2.4‐GHz mixer for Industrial, Scientific and Medical (ISM) band wireless applications. The approach is based on a two‐stage amplifier, and the Gilbert switch stage is inserted between the two amplifier stages. The proposed amplifier‐based mixer delivers a remarkable conversion gain of 13 dB with a local oscillator (LO) power of 7 dBm, while consuming only 1.05‐mW DC power from a 0.8‐V supply voltage. The input‐referred third‐order intercept point (IIP3) of the mixer is 3.82 dBm, and the chip area is only 0.429 mm². The results indicate that this mixer is suitable for the low‐voltage low‐power applications. Copyright © 2014 John Wiley & Sons, Ltd.     

A 63‐dB gain OTA operating in subthreshold with 20‐nW power consumption

This paper presents a two‐stage bulk‐driven operational transconductance amplifier operating in weak‐inversion region. The proposed amplifier is upgraded using recycling structure, current shunt technique, positive feedback source degeneration and indirect frequency compensation feedback to enhance transconductance under a reasonable stability. Combining these approaches leads to an ultra‐low‐power high performance amplifier without increasing power dissipation compared to the conventional one. Simulation results in 0.13‐µm complementary metal–oxide–semiconductor technology show the proposed structure achieves a 63‐dB DC gain at 0.25‐V supply voltage with just 20‐nW power dissipation. Copyright © 2016 John Wiley & Sons, Ltd.     

A novel feed-forward compensation technique for single-stage fully-differential CMOS folded cascode rail-to-rail amplifier

This paper presents a novel active and passive mixed feed-forward compensation technique for single-stage CMOS folded-cascode rail-to-rail operational trans-conductance amplifiers (OTA). Simulations using 0.5 μm Agilent CMOS process parameters indicate a phase margin of around 82° with an unity gain bandwidth of 320 MHz (@1.17 pF capacitive load including the device parasitics). Also, the compensated OTA provided over 60 dB DC-gain with rail-to-rail output voltage swing as well as wide input common-mode range. This ensures optimum step response (fast and accurate settling without ringing) for the feedback amplifier in switched-capacitor signal processing applications. An improved ``fast sensing' common-mode feedback circuit with high common-mode gain is also used for the single-stage cascode OTA.     

Low‐power and low‐noise complementary metal oxide semiconductor distributed amplifier using the gain‐peaking technique

This paper presents an improved topology for ultra‐low‐power complementary metal oxide semiconductor (CMOS) distributed amplifier (DA) based on modified folded cascode gain cells. The proposed CMOS‐DA can be applicable in low‐supply‐voltage applications, because of the use of folded gain cell's structure. The proposed DA decreases power consumption by employing the forward body biasing network, while maintains high gain. By using a gain‐peaking inductor at the gate of the transistor, the proposed DA structure achieved to the gain flatness in high frequencies while the bandwidth is improved as well. In addition, employing RC network at the body terminal improves the noise performance of the proposed DA. The DA architecture consists of three amplification stages. Detailed analysis is provided for the proposed folded cascode DA. According to the post‐layout simulation results of the proposed amplifier using a 0.13‐µm CMOS process, DA achieves power gain of 17.3 ± 0.8 dB in bandwidth of 14.5 GHz, a good input third‐order intercept point (IIP3) of +5.5 dBm. The minimum noise figure is 1.8–5 dB, and input and output return losses are less than −11.5 dB and −10 dB, respectively, and the proposed structure consumes 12 mW from a 0.5 V voltage supply. Copyright © 2016 John Wiley & Sons, Ltd.     

Micropower CMOS Integrated Low-Noise Amplification, Filtering, and Digitization of Multimodal Neuropotentials

Electrical activity in the brain spans a wide range of spatial and temporal scales, requiring simultaneous recording of multiple modalities of neurophysiological signals in order to capture various aspects of brain state dynamics. Here, we present a 16-channel neural interface integrated circuit fabricated in a 0.5 mum 3M2P CMOS process for selective digital acquisition of biopotentials across the spectrum of neural signal modalities in the brain, ranging from single spike action potentials to local field potentials (LFP), electrocorticograms (ECoG), and electroencephalograms (EEG). Each channel is composed of a tunable bandwidth, fixed gain front-end amplifier and a programmable gain/resolution continuous-time incremental DeltaSigma analog-to-digital converter (ADC). A two-stage topology for the front-end voltage amplifier with capacitive feedback offers independent tuning of the amplifier bandpass frequency corners, and attains a noise efficiency factor (NEF) of 2.9 at 8.2 kHz bandwidth for spike recording, and a NEF of 3.2 at 140 Hz bandwidth for EEG recording. The amplifier has a measured midband gain of 39.6 dB, frequency response from 0.2 Hz to 8.2 kHz, and an input-referred noise of 1.94 muV _rms while drawing 12.2 muA of current from a 3.3 V supply. The lower and higher cutoff frequencies of the bandpass filter are adjustable from 0.2 to 94 Hz and 140 Hz to 8.2 kHz, respectively. At 10-bit resolution, the ADC has an SNDR of 56 dB while consuming 76 muW power. Time-modulation feedback in the ADC offers programmable digital gain (1-4096) for auto-ranging, further improving the dynamic range and linearity of the ADC. Experimental recordings with the system show spike signals in rat somatosensory cortex as well as alpha EEG activity in a human subject.