Analytical and experimental verification of substrate noise spectrum for mixed-signal ICs

In this paper, the most relevant characteristics of the substrate noise spectrum for mixed-signal integrated circuits (ICs) are derived using a simple analytical model. These characteristics are related to parameters of the digital circuit, the package + printed circuit board parasitics, and other elements of the mixed-signal IC. The model used to derive the substrate noise spectral characteristics includes the statistical properties of the digital switching current waveform and the coupling transfer function between the digital power supply nodes and the substrate node of the victim circuitry. The results of the work are validated experimentally on a mixed-signal prototype.     

An embedded 1149.4 extension to support mixed-signal debugging

Debugging electronic circuits is traditionally done with bench equipment directly connected to the circuit under debug. In the digital domain, the difficulties associated with the direct physical access to circuit nodes led to the inclusion of resources providing support to that activity, first at the printed circuit level, and then at the integrated circuit level. The experience acquired with those solutions led to the emergence of dedicated infrastructures for debugging cores at the system-on-chip level. However, all these developments had a small impact in the analog and mixed-signal domain, where debugging still depends, to a large extent, on direct physical access to circuit nodes. As a consequence, when analog and mixed-signal circuits are integrated as cores inside a system-on-chip, the difficulties associated with debugging increase, which cause the time-to-market and the prototype verification costs to also increase.The present work considers the IEEE1149.4 infrastructure as a means to support the debugging of mixed-signal circuits, namely to access the circuit nodes and also an embedded debug mechanism named mixed-signal condition detector, necessary for watch-/breakpoints and real-time analysis operations. One of the main advantages associated with the proposed solution is the seamless migration to the system-on-chip level, as the access is done through electronic means, thus easing debugging operations at different hierarchical levels.     

A unified approach for fault simulation of linear mixed-signal circuits

The rapidly evolving role of analog signal processing has spawned off a variety of mixed-signal circuit applications. The integration of the analog and digital circuits has created a lot of concerns in testing these devices. This paper presents an efficient unified fault simulation platform for mixed-signal circuits while accounting for the imprecision in analog signals. While the classical stuck-at fault model is used for the digital part, faults in the analog circuit cover catastrophic as well as parametric defects in the passive and active components. A unified framework is achieved by combining a discretized representation of the analog circuit with the Z-domain representation of the digital part. Due to the imprecise nature of analog signals, an arithmetic distance based fault detection criterion and a statistical measure of digital fault coverage are proposed.This research was supported by the National Science Foundation under grant MIP-9222481.     

Signature analysis for fault detection of mixed-signal ICs based on dynamic power-supply current

In this paper we have investigated a unified and simultaneous fault detection method for mixed-signal integrated circuits. The method is based on the analysis of the power-supply current through the circuit under test. The analysis has been done paying attention to the dynamic behaviour of the power-supply current, in order to avoid measurement problems related to the large amount of quiescent current drop across many analog blocks.The analysis of the dynamic power-supply current entails certain problems related to the complexity of the measurement process, especially those due to the high speed of the current transients. These problems have been addressed by considering a design for test procedure based on the use of built-in dynamic current sensors.The goal of the design for test methodology proposed is to represent the Iddt through the mixed-signal IC under test by a digital signature. The paper presents some advantages of this approach such as a good tolerance to cross-talk noise and the need for only a conventional digital tester on the complete mixed-signal IC for fault detection. The analysis is illustrated with some test results.     

Verification techniques for substrate coupling and theirapplication to mixed-signal IC design

This paper presents techniques for the analysis of substrate-coupled noise in mixed-signal integrated circuits. Advantages and limitations of some commonly employed verification techniques for substrate coupling are outlined. A preprocessed boundary element method introduced in this paper utilizes precomputed z parameters to generate an analytical model for substrate impedance in a preprocessing stage. Truncated series expansions of the analytical impedance model are used to accelerate solution of the resulting boundary element equations. A methodology that applies these fast techniques to the verification of large mixed-signal circuits and results that confirm its efficiency are described. This complete methodology has been applied to the design and verification of an industrial mixed-signal video analog-to-digital converter IC for substrate noise problems     

基于WOA-PNN算法的电力电子电路故障诊断分析

为进一步提高电力电子电路可靠性,提出了一种基于鲸鱼优化算法(WOA)的优化概率神经网络(PNN)算法,对电力电子电路进行了故障诊断。通过Simulink软件建立电路模型,利用小波变换分析电路中的直流输出。将分析后的参数作为特征值,将电路正常工作状态下的特征值与故障状态中的特征值作为训练样本,输入WOA-PNN,并进行训练。仿真验证结果表明,与直接应用PNN进行故障诊断相比,WOA-PNN算法能更准确地诊断和分析电力电子电路的故障。     

Efficient methods for modelling substrate coupling in mixed-signalintegrated circuits

A key problem in the design of large mixed-signal circuits is the noise caused by the coupling of digital signals into the substrate. This paper describes methods that allow circuit designers to model efficiently such substrate noise in large mixed-signal SPICE designs. In the light of these techniques a new methodology is presented for efficiently modelling the substrate noise caused by current injection and its coupling to analogue signals; this is then extended to provide a real-time modelling capability. The practicality and the numerical efficiency of the methods are demonstrated on several prototype example circuits     

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance GaAs digital ICs with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. The authors evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. GaAs IC fabrication and logic circuit approaches is reviewed. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits.     

Computer-aided failure mode and effect analysis of electronic circuits

Most techniques for Failure Mode and Effect Analysis (FMEA) of the electronic equipment and circuits have up till now been based on manual examination of the circuit schemes. This technique has often been considered to be arduous and time consuming. No computer-based methods to perform the FMEA have been available, and it has become obvious that the usual circuit analysis programs are not suitable for this purpose. However, the extended use of electronic equipment in controlling automatic machines has increased the need to evaluate the safety and security of the system as effectively as possible. This is one of the main ressons for starting the generation of this computer program as a tool for FMEA of electronic circuits.     

基于遗传算法的Kriging元模型及其在模拟集成电路优化设计中的应用

提出了建立电路Kriging元模型,并与遗传算法相结合确定电路参数,优化电路的方法.相对传统多项式回归模型,Kriging模型更适合电路仿真的实验类型;利用遗传算法,解决了基于Kriging元模型电路系统的全局优化问题.最后将该方法应用于带隙基准电路设计,取得令人满意的结果.     

The Effect of Temperature-Induced Quiescent Operating Point Shift on Single-Event Transient Sensitivity in Analog/Mixed-Signal Circuits

This paper discusses the different sensitivities of laser-induced single-event transients (SET) with changed temperature (from 300 to 348 K) for an analog/mixed-signal DC/DC PWM controller IC. Basic analog circuits, such as the amplifier, the comparator, and the current mirror, are selected to perform the experiment. The SET energies for some devices decrease while those for others remain constant. The spice simulation implies that the temperature-induced quiescent operating point shift can dramatically affect the SET sensitivity, especially in a complex analog/mixed-signal system. This effect also gives insights on radiation hardened design and testing in analog/mixed-signal circuits.     

航空电子设备故障诊断技术研究综述

随着电子技术的发展,电子设备组成的复杂化和智能化不断提高,IC芯片制造工艺的不断提高使得VLSI电路的集成密度增加,亦加大了电路故障测试的复杂性和困难度。本文综述了电子电路的通用测试方法和技术,并分析了局限性。详细叙述了刚刚发展起来的基于知识的故障诊断方法,它的应用使对于一个较复杂的电子设备进行准确故障诊断成为可能,并对其发展进行了探讨和展望。     

The prospects for ultrahigh-speed VLSI GaAs digital logic

Recent advances in the state of GaAs integrated circuit fabrication technology have made possible the demonstration of ultrahigh performance (tau_{d} sim 100ps) GaAs digital IC's with up to 64 gate MSI circuit complexities and with gate areas and power dissipations sufficiently low to make VLSI circuits achievable. It is the purpose of this paper to evaluate, based on the current state of GaAs IC technology and the fundamental device physics involved, the prospects of achieving an ultrahigh-speed VLSI GaAs IC technology. The paper includes a performance comparison analysis of Si and GaAs FET's and switching circuits which indicates that, for equivalent speed-power product operation, GaAs IC's should be about six times faster than Si IC's. The state of the art in GaAs IC fabrication and logic circuit approaches is reviewed, with particular emphasis on those approaches which are LSI/VLSI compatible in power and density. The experimental performance results are compared for the leading GaAs logic circuit approaches, both for simple ring oscillators and for more complex sequential logic circuits (which have demonstrated equivalent gate delays as low astau_{d} = 110ps).     

Making complex mixed-signal telecommunication integrated circuitstestable

This article presents a discussion of several methods that can be used to improve the testability of complex mixed-signal telecommunication integrated circuits. We begin by outlining the role of test and its impact on product cost and quality. A brief look at the pending test crises for mixed-signal circuits is also considered. Subsequently, we outline the evolution of test strategies with time, and their corresponding test setups for verifying the function of the analog portion of a mixed-signal circuit. The article also describes several circuit techniques for improving test access and providing built-in self-test solutions for telecommunication circuits     

Optimization Technique for Dynamic Reconfiguration of Programmable Analog/Digital Arrays

This paper presents an investigation of dynamically reconfigurable mixed-signal circuit constructed using a digital control system and the new technology of Field Programmable Analog Arrays (FPAA). A Motorola FPAA described in this paper can be used to build filters for analog signals as well as other kinds of analog applications implemented in switched capacitor technology (S/C-technology). The experimental studies described, take advantage of performance and programmability of the FPAA for filtering of an analog signal. The circuit structure is based on 2 parallel FPAA chips, analog multiplexer and multiplexer's control logic controlled by a digital system such as a PC or a Field Programmable Gate Array (FPGA). Dynamic reconfiguration is used in this system for adaptive filtering, or adaptive processing in general. Modeling and measurements of the transition behavior of the switching process between the 2 FPAA chips and analysis of limitations imposed by hardware imperfections will be presented. The experimental system assembled in this work is an excellent vehicle to learn about intricacies in performance of mixed-signal circuits and is used for verification of theoretical predictions and model validation/modification.     

Computer-aided design considerations for mixed-signal coupling inRF integrated circuits

This paper reviews computer-aided design techniques to address mixed-signal coupling in integrated circuits, particularly wireless RF circuits. Mixed-signal coupling through the chip interconnects, substrate, and package is detrimental to wireless circuit performance as it can swamp out the small received signal prior to amplification or during the mixing process. Specialized simulation techniques for the analysis of periodic circuits in conjunction with semi-analytical methods for chip substrate modeling help analyze the impart of mixed-signal coupling mechanisms on such integrated circuits. Application of these computer-aided design techniques to real-life problems is illustrated with the help of a design example. Design techniques to mitigate mixed-signal coupling can be determined with the help of these modeling and analysis methods     

Crossroads for mixed-signal chips

The last decade saw a surge in the number of small IC design houses, so-called fabless enterprises, that provide systems manufacturers with application-specific ICs (ASICs). More recently, shrinking circuit features and rising transistor density have spawned the system on a chip (SoC), in which most or all of the circuitry required for, say, a cellphone fits on a single IC. Today, these SoCs often contain analog, RF, and mixed-signal components to satisfy the growing demands of communication applications. SoC designers need input from the intellectual property (IP) providers that design circuit modules for use with other SoC elements. Also, they need design tools that can rapidly integrate IP libraries with the mundane sizing, placing, and routing of circuits     

基于布尔可满足性的逻辑电路等价性验证方法

提出了基于布尔可满足性(Boolean Satisfiability,SAT)的逻辑电路等价性验证方法。这一验证方法把每个电路抽象成一个有穷自动机(FSM),为两个待验证的电路构造积机,把等价性验证问题转换成了积机的断言判定问题。改进了Tseitin变换方法,并将其用于把电路约束问题变换成(Conjunctive Normal Form,CNF)公式。之后则用先进的CNF SAT求解器zChaff判定积机所生成的布尔公式的可满足性。事例电路验证说明了该方法的有效性。     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.