A VLSI design methodology for distributed arithmetic

Real-time signal processing requires fast computation of inner products. Distributed arithmetic is a method of inner product computation that uses table-lookup and addition in place of multiplication. Distributed arithmetic has previously been shown to produce novel and seemingly efficient architectures for a variety of signal processing computations; however the methods of design, analysis and comparison have been ad hoc. We propose a systematic method for synthesizing optimal VLSI architectures using distributed arithmetic.A partition of the inner product computation at the word and bit level produces a computation consisting of lookups and additions. We study two classes of algorithms to implement this computation, regular iterative algorithms and tree algorithms, each of which can be expressed in the form of a dependency graph. We use linear and nonlinear maps to assign computations to processors in space and time. Expressions are developed for the area, latency, period and arithmetic error for a particular partition and space/time map of the dependecy graph. We use these expressions to formulate a constrained optimization problem over a large class of architectures. We compare distributed arithmetic with more conventional methods for inner product computation and show how area, latency and period may be traded off while maintaining constant error.This work was supported by Ball Aerospace, Boulder, CO and by the Office of Naval Research, Electronics Branch, Arlington, VA under contract ONR 89-J-1070.     

A new device design methodology for manufacturability

As future technology generations for integrated circuits continue to “shrink”, TCAD tools must be made more central to manufacturing issues; thus, yield optimization and design for manufacturing (DFM) should be addressed integrally with performance and reliability when using TCAD during the initial product design. This paper defines the goals for DFM in TCAD simulations and outlines a formal procedure for achieving an optimized result (ODFM). New design of experiments (DOE), weighted least squares modeling and multiple-objective mean-variance optimization methods are developed as significant parts of the new ODFM procedure. Examples of designing a 0.18-μm MOSFET device are given to show the impact of device design procedures on device performance distributions and sensitivity variance profiles     

A PMC-driven methodology for energy estimation in RVC-CAL video codec specifications

In this paper, an energy estimation methodology based on performance monitor counters (PMC) is proposed to estimate the energy consumption of RVC-CAL video codec specifications. The proposed PMC-driven methodology is able to automatically identify the most appropriate events and training data to cover the main application characteristics. In addition, knowledge of the hardware platform employed is not required. Therefore, this methodology can be easily implemented on other PMC-available systems while keeping the estimation accuracy. It is worth noting that this is an attractive asset to analyze the energy consumption of RVC-CAL codec specifications. Besides, the methodology reduces the PMC redundancy and, thus, the overhead introduced when applied to on-line power management. Experimenting on two RVC-CAL decoders, H.264 and MPEG4 Part2 SP, a coarse estimation model based on instructions per cycle (IPC) and the proposed PMC-driven model are compared. The results show that the PMC-driven model can achieve for the H.264 and MPEG4 Part2 SP decoders average estimation errors of 5.95% and 5.01%, respectively, in comparison to the 17.11% and 13.65% average errors obtained with the IPC-based model. As a consequence, this methodology is suggested to be combined into the RVC framework to help the designer to have an overview of the energy consumption of the specification actors at earlier design stages.     

A design methodology for high-order class-D audio amplifiers

This paper presents a design methodology for high-order class-D amplifiers, based on their similarity with sigma–delta ( $\Upsigma\Updelta$ ) modulators, for which established theory and toolboxes are available. The proposed methodology, which covers the entire design flow, from specifications to component sizing, is validated with three design examples, namely a second-order, a third-order, and a fourth-order class-D amplifier. Moreover, the third-order class-D amplifier has been integrated on silicon and characterized, further confirming the validity of the whole design flow. The achieved results demonstrate that high-order class-D amplifiers can achieve total-harmonic-distortion (THD) performance compatible with the specifications of high-end audio applications (THD  ≈ 90 dB), which would be unfeasible with conventional first-order class-D amplifiers.     

A unified design methodology for CMOS tapered buffers

In this paper, the various disparate approaches to CMOS tapered buffer design are unified into an integrated design methodology. Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of concern in tapered buffers, and each places a separate, often conflicting, constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer design equations are presented for propagation delay and power dissipation, as well as a new split-capacitor model of hot-carrier reliability of tapered buffers and a two-component physical area model. Each performance criterion is individually investigated and analyzed with respect to the number of stages and tapering factor, and the interaction of the four criteria is examined to develop both a qualitative and a quantitative understanding of the various design tradeoffs. The creation of process dependent look-up tables for optimal buffer design is described, and a methodology to apply these look-up tables to application-specific tapered buffers for both unconstrained and constrained systems is developed     

A three-dimensional CMOS design methodology

A technology-updatable design methodology for three-dimensional CMOS circuits has been developed. Four levels of abstraction have been implemented with topographical congruence: (1) technology level, (2) mask level, (3) transistor level, and (4) logic level. A novel transistor-level symbolic representation is introduced which emphasizes the three-dimensional nature of the circuits. A number of design examples are presented.     

A three-dimensional CMOS design methodology

A technology-updatable design methodology for three-dimensional (3-D) CMOS circuits has been developed. Four levels of abstraction have been implemented with topographical congruence: 1) technology level, 2) mask level, 3) transistor level, and 4) logic level. A novel transistor level symbolic representation is introduced which emphasizes the three-dimensional nature of the circuits. A number of design examples is presented.     

A novel methodology for robust VBR video transmission in an ATM system

A dynamic FEC (DFEC) scheme for VBR video in ATM networks is proposed. The scheme combines the design of source encoder, error control, and the network. In the design, we will develop a methodology to vary FEC redundancy dynamically. The methodology considers the fluctuations in video source and network utilisation to adjust the FEC redundancy levels. We demonstrate the effectiveness of the proposed scheme by examining its performance with three existing schemes in terms of loss rates, throughput, and quality degradation. Copyright © 2002 John Wiley & Sons, Ltd.     

A regular fabric design methodology for applications requiring specific layout-level design rules

Regular fabrics have been introduced as an approach to bridge the gap between ASICs and FPGAs in terms of cost and performance. Indeed, compared to an ASIC, by predefining most of the manufacturing masks, they highly reduce time-to-market, non-recoverable engineering costs and lithography hazards. Also, thanks to hardwired configuration and interconnections their performance is closer to those of ASICs than those of FPGAs. They are therefore well suited to many applications requiring low to medium volume applications or higher performance than those provided by FPGAs.In this paper, we evaluate the interest of using a regular fabric to reduce time and design cost significantly in applications involving specific transistor level design (radiative/spacial conditions, side-channel attacks, NMR environment, etc.). With this aim in view, after a broad state of the art overview with an emphasis on architectures and design flows, we develop our approach of a regular fabric designed to limit layout level design, ad-hoc tools and technological migration cost. Then, we evaluate its performance in a 65 nm process versus FPGA and standard cell based ASIC implementations. For sequential designs, our proposed solution is on average 2.5×slower and 2.3×bigger than a standard cell implantation, but also on average 13×faster than a FPGA.     

A solution methodology for exact design space exploration in athree-dimensional design space

This paper describes an exact solution methodology, implemented in Rensselaer's Voyager design space exploration system, for solving the scheduling problem in a three-dimensional (3-D) design space: the usual two-dimensional (2-D) design space (which trades off area and schedule length), plus a third dimension representing clock length. Unlike design space exploration methodologies which rely on bounds or estimates, this methodology is guaranteed to find the globally optimal solution to a 3-D scheduling problem. Furthermore, this methodology efficiently prunes the search space, eliminating provably inferior design points through the following: 1) a careful selection of candidate clock lengths and 2) tight bounds on the number of functional units or on the schedule length. Both chaining and multicycle operations are supported     

A thermal design methodology for multifinger bipolar transistor structures

A technique is presented that allows the increase in maximum temperature rise due to thermal coupling in multifinger structures to be predicted for a wide range of finger lengths and spacings by reference to a single, normalized characteristic. Application of this approach to the design of thermal resistance in multifinger structures results in a fast and straightforward method for generating families of structures that meet given power and temperature criteria without thermal simulation-based optimization. The usefulness of this approach is illustrated through solution of a practical design problem, and the accuracy of the method is verified by comparison with the final solutions to numerical simulation.     

A two-phase methodology for technology selection and system design

A two-phase methodology to guide research and development managers in the evaluation and selection of competing technologies is presented. Deterministic multi-attribute utility theory is used in the first phase to rank the technological alternatives and to eliminate inferior candidates. The procedure is illustrated with an application drawn from a study centering on the evaluation of electric and hybrid passenger vehicles. Thirty-nine individuals were interviewed to assess their risk preferences and determine their attitudes toward the vehicle design. In the second phase, it is assumed that a particular technology has been chosen for further development. The decision-maker must then allocate a fixed amount of resources to different projects, some of which may be undertaken in parallel, to maximize a given measure of performance. The problem is formulated as a probabilistic network and solved heuristically using Monte Carlo simulation. Results are presented for the most preferred vehicle identified in phase one for two representative decision-makers and three budget options. In each case, the heuristic finds a solution that corresponds to the optimal allocation of funds     

A practical design of digital watermarking for video streaming services

A practical design of digital watermarking for video streaming services is proposed in this research. The information of a legitimate recipient is represented as a watermark, which is embedded in the video stream to serve as a cue to trace the recipient in case a clone of the video is illegally distributed. The watermark signals are designed to embed in some areas of video frames to benefit the video stream server, as the result of only partial actions required, including decoding, processing and re-encoding. The invariance of feature points and the self-similarity of hidden signals are further exploited to enable watermark detection without involving the original video. The watermark can decently survive transcoding processes and geometrical modifications of frames. The experimental results demonstrate the advantages of the proposed scheme in terms of watermark visibility, capacity and detection methodology.     

A systematic design methodology for power-optimal design of high-order multi-bit continuous-time Delta-Sigma modulators

In this paper a systematic design methodology for high-order multi-bit continuous-time Delta-Sigma modulators is proposed. It provides a straightforward method for determining the coefficients of the modulator. The method is illustrated for a 4th-order 4-bit modulator with OSR of 8, while 20 MHz signal bandwidth and 12 bit resolution is achieved. The required GBW of the first integrator is less than 1.5 times the sampling frequency, which greatly reduces the overall power consumption.     

A hierarchical design methodology for full-search block matching motion estimation

Many useful DSP algorithms have high dimensions and complex logic. Consequently, an efficient implementation of these algorithms on parallel processor arrays must involve a structured design methodology. Full-search block-matching motion estimation is one of those algorithms that can be developed using parallel processor arrays. In this paper, we present a hierarchical design methodology for the full-search block matching motion estimation. Our proposed methodology reduces the complexity of the algorithm into simpler steps and then explores the different possible design options at each step. Input data timing restrictions are taken into consideration as well as buffering requirements. A designer is able to modify system performance by selecting some of the algorithm variables for pipelining or broadcasting. Our proposed design strategy also allows the designer to study time and hardware complexities of computations at each level of the hierarchy. The resultant architecture allows easy modifications to the organization of data buffers and processing elements-their number, datapath pipelining, and complexity-to produce a system whose performance matches the video data sample rate requirements.     

A recursive design methodology for VLSI: Theory and example

A novel VLSI (Very Large Scale Integration) methodology based on the hierarchical design of computational and system blocks is presented. The underlying algorithms used are shown to optimise the area-time complexity (AT²) of the computational units and at the system design level. The technique is illustrated for a matrix-matrix multiplication by using an image processing window convolver. This paper describes the performance of the recursive design technique comparing it to a typical systolic array, and demonstrates how data word size and convolution size may be expanded by movement up the architectural hierarchy. A prototype CAD (Computer Aided Design) autolayout program is described which maps directly into the hierarchical design environment. Using such design aids, flexible and correct designs may be generated which offer very simple data flow and highly local interconnection, with high performance.     

A model-based and simulation-driven methodology for design of haptic devices

High precision and reliable haptic devices are highly complex products. The complexity that has to be carefully treated in the design process is largely due to the multi-criteria and conflicting character of the functional and performance requirements. These requirements include high stiffness, large workspace, high manipulability, small inertia, low friction, high transparency, as well as cost constraints. The requirements are a basis for creating and assessing design concepts. Concept evaluation relies to a large extent on a systematic usage of kinematic, dynamic, stiffness, friction, and control models. The design process can benefit from a model-based and simulation-driven approach, where one starts from an abstract top-level model that is extended via stepwise refinements and design space exploration into a detailed and integrated systems model that can be physically realized. Such an approach is presented, put in context of the V-model, and evaluated through a test case where a haptic device, based on a Stewart platform, is designed and realized. It can be concluded, based on simulation and experimental results that the performance of this deterministically optimized haptic device satisfies the stated user requirements. Experiences from this case indicate that the methodology is capable of supporting effective and efficient development of high performing haptic devices. However, more test cases are needed to further validate the presented methodology.     

A quantitative design methodology for high-speed interpolation/averaging ADCs

This paper proposes a new quantitative and systematic design methodology for high-speed interpolation/ averaging ADCs. The methodology consists of a new mathematical BW/gain model derived from the pre-amps arrays static model and new small-signal model, a new offset modeling mechanism that can accurately estimate and help to reduce the offset, and hence a new systematic design flow. The methodology enables a quantitative and systematic analysis, conducts iterative and accurate calculation realized in MATLAB, and finally leads to an optimized ADC design that reaches a guaranteed optimum full-chip performance with given specs (i.e., resolution, speed, input range, power, input CM, etc.). The methodology shows significant advantage over the traditional trial-and-error ADC design approach with respect to performance and design efficiency, and is much more reliable in nanometer technologies. The proposed methodology was fully validated in silicon: a 4-bit 5GSps interpolation/averaging ADC is fabricated in a 65 nm CMOS technology and the measurement results show that our ADC has indeed achieved an outstanding and comparable overall performance compared to reported state-of-the art ADCs.     

数字视频混合系统的设计

介绍了利用Philips的一款视频芯片SAA71 99B实现的数字视频混合系统.该系统可以将一路PAL制彩色复合视频信号编码进入另一路PAL制彩色复合视频信号中,以取代第二路视频中用户指定的颜色,从而实现了两路视频的混合.另外还介绍了如何利用单片机的I/O口模拟I 2C总线以及如何利用单片机进行彩色空间变换的算法.