互控?钟控移位寄存器序列

提出了一种新的互控钟控移位寄存器模型.该模型具有设备简单,易于实现,并且产生的序列周期长,线性复杂度高,抗攻击能力强等特点.这种模型被进一步改进,利用它可以生成更好的序列.     

A low-latency asynchronous shift register

In this paper, we first introduce a straightforward asynchronous shift register design implemented by differential cascode voltage switch logic and micropipeline. The corresponding latency defect between data readout is then described. To solve this problem, we propose a new architecture for the design. Finally, a basic building block with respect to our architecture is proposed.     

A 512-bit shift register using compact two-phase single fluxquantum clock generators with large margins and low power

A 512-b shift register was built and tested up to 14.5 GHz. The shift register uses a two-phase clock which is generated by coupling a master control line over many asymmetrically biased two-junction SQUIDs. Compared with other shift registers with Josephson transmission lines to deliver clock, this new clock system provides short delay, low power dissipation, and large DC bias margins. The shift register uses about 3000 Nb/AlO_x/Nb Josephson junctions and consumes about 0.1 mW     

Low power serial-parallel dynamic shift register

Serial-to-parallel shift registers have a wide range of applications. These registers are commonly found in communication systems and interfaces between electronic peripherals. Presented is a unique low power area efficient 128-bit serial-to-parallel shift register design that contains only four transistors per stage. The new register uses the capacitive bootstrapping technique to overcome the threshold voltage drop of MOSFETs. This logic family is named non-ratioed bootstrap logic (NRBL). Target applications are dense smart sensor arrays and image sensors.     

Rijndael移位寄存器实现方案

(1)引 言分组加密算法Rijndael在2000年10月2日被确定为美国高级加密标准AES(Advanced Encryption Standard)。在经过严格的安全分析后,从2002年5月26日起作为官方标准(FIPS197)正式实施,取代DES在未来30年里保护美国联邦政府非机密敏感信息,同时在商业、金融和IT等领域获得广泛应用。Rijndael算法是一个分组长度为128比特、密钥可取128、192和256三种长度的分组密码。16字节的分组被组织成称为状态的4×4字节矩阵,其中的列可看成一个4字节的字。密码变换就在这样的字节、行和列上实施,以圈变换为单位连续迭代若干次(对应不同密钥长…     

A bipolar four-phase dynamic shift register

A 512-b dynamic shift register is integrated on 6.4-mm/SUP 2/ active chip area. The frequency range is from 100 Hz to 3 MHz. At 1 MHz the power dissipation is 20 mW. The performance of the shift register is insensitive to spread in process parameters because the information is regenerated in each cell. The comparison of the measured and the calculated working range shows the essential influence of all parasitic capacitances.     

The bipolar transistor bucket-brigade shift register

An analysis of the bipolar transistor bucket-brigade shift-register operation is presented for comparison to other charge-transfer shift-register schemes. It is shown that incomplete charge transfer, the most important performance limiting effect for the charge-coupled device and the IGFET bucket brigade, is very small under most practical operating conditions for the bipolar transistor bucket brigade. In addition to charge loss due to finite transistor current gain h/SUB fe/ the next most important performance limitation comes from collector-emitter capacitance. It is shown that this collector-emitter capacitance leads to reduced analog time delay on transfer through the register and to signal attenuation effects similar to those resulting from incomplete charge transfer. Using the results of the analysis, experimental data reported by Sangster are discussed and a comparison of the advantages and disadvantages of the bipolar bucket-brigade register with the MOS charge-transfer registers is made.     

A two-phase plasma-coupled static shift register

In designing an experimental 2-bit plasma-coupled shift register, fabricated with standard bipolar technology, it is shown that a simplification of the existing plasma-coupled device (PCD) concept by omission of the double base diode not only decreases the power dissipation and increases the ease of fabrication, but also increases the attractive simplicity of the basic cell. The average power dissipation of the new device is 200 /spl mu/W/bit at a clock frequency of 3 MHz. The bit density is 135 bit/mm/SUP 2/ with 10-/spl mu/m spacing between interconnection lines 10 /spl mu/m in width. A hypothetical layout with dielectric isolation and closer tolerances results in a bit density of 900 bit/mm/SUP 2/ and an estimated power dissipation of 80 /spl mu/W/bit.     

A CCD serial to parallel shift register

Charge-coupled devices have been well known for their serial-type applications. The authors report a new scheme whereby parallel outputs can be obtained from every bit of a serial CCD shift register without destroying the transferred charge and without the use of an external resetting pulse. The results of a 20-b 3/spl phi/ CCD shift register with parallel outputs are described. The work extends the applicability of CCD's to a less restricted area.     

Performance limitations of the IGFET bucket-brigade shift register

The IGFET bucket brigade in integrated circuit form is a particularly simple structure for implementing dynamic charge transfer shift registers. Experimental and analytical studies show that incomplete charge transfer is an important limitation of register performance leading to signal degradation. This sets an upper limit to the clock frequency and to the number of stages in the register. The effects leading to incomplete charge transfer include: 1) the finite rate at which charge moves from one capacitor to the next through the IGFET transconductance; 2) the reduction in transfer rate (due to IGFET output conductance) when part of the charge has already been transferred to the drain; and 3) the loss of charge to interface states. The relative importance of these effects depends on device structure, clock frequency, clock voltage amplitude, and waveform. Under most operating conditions the IGFET output conductance contribution is most important, and the best results were obtained with a structure that minimized the effect. Experimental data show that p-channel registers in 31-bit strings can be operated satisfactorily to clock frequencies in excess of 5 MHz, and that by appropriate register design significantly better performance should be possible.     

Unidirectional transfer properties of the plasma-coupled shift register

Features of bipolar-type shift register (SR), utilizing a plasma-coupled device (PCD) for transferring potential variation through the bulk are described. The coupling-resistance parameter was studied to estimate the shift-register operation. To analyze the coupling resistance, an equivalent PCD circuit model was deduced from the device structure. The model sufficiently accounts for the features of unidirectional propagation based on an essentially geometrical design. To attain preferentially unidirectional signal propagation, an anti-symmetrical element configuration and an extended probe structure were fabricated, and the unidirectional transfer effect was investigated theoretically as well as experimentally. The relation between the operation margin and the device parameter, cell pitch length, and substrate resistivity, are discussed utilizing the antisymmetrical concept. High packing density, low operation voltage, and fewer shift pulses were predicted to be possible from the analytical estimations and were confirmed by the experimental results.     

Analog capacitance ROM with IGFET bucket-brigade shift register

A new type of monolithic analog read-out memory is described. It consists of a memory element and associated on-chip readout circuitry. The memory can be used for storing sample values of time-varying analog signals. The memory element is a matrix of MOS capacitors, preprogrammed in size by a special mask. The readout element is a bucket-brigade shift register with parallel input and serial output. A test circuit that permits investigation of different principles of information transfer from capacitance matrix to shift register has been developed.     

RSFQ 1024-bit shift register for acquisition memory

Rapid single flux quantum (RSFQ) 512-bit and 1024-bit shift registers have been demonstrated. These are the longest superconducting shift registers reported to date, employing 1045 and 2069 Josephson junctions, respectively. The circuit functionality has been confirmed with dc bias margins of ±23% and ±14% for the 512-bit and the 1024-bit shift registers, respectively. The 512-bit shift register has been tested to 20 GHz and 1024-bit register to 19 GHz using an external clock trigger with relative delay measurements at single and double SFQ clock frequencies. The shift registers with the same design have been used for successful implementation of the acquisition shift register (ASR) memory for the projected transient digitizer. These shift registers have the ability to acquire data at high speeds (gigahertz range), statically hold the acquired data, and then read-out the data into conventional room-temperature electronics at low speeds (megahertz range). A 32-bit ASR has been tested up to 18 GHz (the limit of our test setup), and a 1024-bit ASR-up to 16 GHz of acquisition rates, both at 33 MHz read-out frequency. Total power dissipation is about 1 mW for the 1024-bit circuit. The chips are fabricated using Hypres' Nb/AlO_x /Nb process with a junction critical current density of 1.0 kA/cm ²     

A shift register architecture for high-speed data sorting

This paper presents a shift-register architecture or SRA, for data sorting applications. The operations performed by the proposed architecture are (1)shift right, (2)shift left, (3)load, and (4)initialize. Sorting operations, such as insert and delete, can be realized by the combination of these 4 basic operations. The architecture is very regular and mainly composed of two basic cells,sort-cell and compare-cell. The latter is designed to generate control signals orchestrating the operation of sort cells which contain the sorted input sequences. Experimental results show that a single chip solution can achieve real-time performance based on 1.2m CMOS double-metal technology.Work support by the National Science Council of Taiwan, ROC under grant NSC82-0404-E009-184.     

Amorphous silicon shift register for addressing output drivers

An amorphous silicon (a-Si) shift register is described. By integrating this shift register design with an array of a-Si drivers, the cost/complexity of the interface to the array is significantly reduced, without trading off speed. Circuit design considerations unique to a-Si devices are also discussed along with their processing     

High-speed operation of a 64-bit circular shift register

A 64-bit superconducting rapid single flux quantum (RSFQ) circular shift register (CSR) has been demonstrated to operate at clock frequencies up to 18 GHz. The CSR was designed with special attention to timing constraints, which are more severe for “recurrent” circuits (where data must circulate around closed feedback loops) than for systolic arrays where only local timing constraints are relevant. The longest recurrent data path ever demonstrated previously was only several stages long. The testing scheme demonstrated here is unique in that the data circulated up to 50 million times before verification     

Experimental SFQ interferometer shift register prototype with Josephson junctions

A shift register prototype has been implemented with lead-alloy technology. Single-flux quanta have been shifted in both directions by local magnetic fields with a maximum repetition frequency of 250 MHz. The absence or presence of a flux quantum at a given position is read out nondestructively. The speed and the miniaturisation potential of the proposed shift register is discussed.     

Testing a 4-b shift register at 11 GHz

A 4-bit superconducting shift register based on edge triggered gates has been tested up to 11 GHz with two-phase offset sinewave clocks. The edge triggered gates are made by serial connection of a Josephson junction (JJ) and a modified variable threshold gate, fabricated by a Nb/AlO_x/Nb process