LiMn2O4/活性炭复合材料的电化学性能研究

制备了不同比例的活性炭复合LiMn2O4电极材料,研究其在1mol/L Li2SO4溶液中的电化学性能.循环伏安结果表明复合后电极材料的电容包含活性炭的双电层电容和LiMn2O4电化学反应的法拉第电容,复合后响应电流在0～0.6V范围内有所增加,且含80%活性炭时响应电流达到最大;恒流充放电结果表明含80%活性炭时的放电曲线也基本呈直线,表现出较好的电容特性,仅复合了20%的LiMn2O4,其容量却增加了25%;交流阻抗结果表明含80%活性炭的复合电极的溶液欧姆电阻仅为0.1Ω,呈现出更理想的电容行为.     

温度对燃烧包覆LiMn2O4/ZnO及其电性能的影响

通过葡萄糖辅助低温燃烧制备ZnO包覆型LiMn2O4,利用X射线衍射仪、扫描电子显微镜、循环伏安、交流阻抗以及恒流充放电测试等手段,研究了温度对产物晶体结构、微观形貌及电化学性能的影响。XRD结果表明所有产物均为单相尖晶石型LiMn2O4结构。SEM结果表明产物的颗粒尺寸随温度的升高而增大。电化学性能测试表明400℃和500℃制备的LiMn2O4/ZnO具有相对优异的电化学性能,室温1C条件下首次放电比容量分别为119.3mAh/g、116.3mAh/g,循环100次后容量保持率分别85.6%、87.8%。尖晶石LiMn2O4电极的阻抗谱特征与温度有关,电池的电化学性能主要受电荷转移电阻(Rct)影响。     

S-Co复合掺杂LiMn2O4的合成与性能

为了扩大锂离子电池正极材料LixMn2O4的工作电压范围，在保证良好循环性能的基础上提高材料的容量，本文对S-Co复合掺杂LiMn2O4的合成工艺和电化学性能进行了研究．溶胶-凝胶法合成的各试样均为纯的立方尖晶石相，且结晶状态良好．S—Co复合掺杂综合了S掺杂效应和Co掺杂效应，改善了LiMn2O4的电化学性能，在2．4—4．3V充放电压范围内，初始容量较高，达到170mAh／g，30次循环后容量不但没有衰减而且有一定增加．     

以Mn3O4为前驱体的LiMn2O4及其电化学性能

对传统的固相反应进行了改进,以控制结晶法合成出来的Mn3O4为前驱体,和LiOH混合煅烧,制备出锂离子电池正极活性材料尖晶石LiMn2O4。对由此方法得到的尖晶石LiMn2O4的结构和电化学性能进行了研究。通过X线光衍射和扫描电镜分析表明,该材料为纯相尖晶石LiMn2O4,不含其它杂质相,而且晶粒大小比较均匀;通过电化学性能测试表明,该尖晶石LiMn2O4具有良好的电化学性能：其首次放电比容量为128mAh/g,经过10次充放电循环后,其放电比容量仍有124mAh/g。     

薄膜厚度对LiMn2O4薄膜性质的影响

采用溶液沉积法制备不同厚度的LiMn2O4薄膜，用x射线衍射及扫描电子显微镜检测和分析薄膜的物相及形貌；采用恒电流充放电及交流阻抗技术研究LiMn2O4薄膜的电化学性质。结果表明不同厚度的LiMn2O4薄膜均匀，晶粒大小相近，晶粒尺寸在20-50nm之间。当放电电流密度为100μA／cm^2时，不同厚度的LiMn2O4薄膜比容量相差不大，其值在42-47μAh／（cm^2．μm）之间。薄膜循环性能随着薄膜厚度的增加而变差，经50次循环后，薄膜每次循环的容量损失从0．18μm的0．012％升高到1．04μm的0．16％。电化学阻抗表明不同厚度的LiMn2O4薄膜的锂离子扩散系数差别不大，数量级为10^-11cm^2／s。     

Bi和F复合掺杂对LiMn2O4结构及电化学性能的影响

采用固相法合成LiMn2-xBixO4-yFy(x=0,0.03;y=0,0.05,0.1),通过X-射线衍射、扫描电子显微镜、恒电流充放电及循环伏安等技术分析检测合成材料的结构、形貌及电化学性能。结果表明:合成的LiMn2-xBixO4-yFy均为尖晶石结构,无杂相,颗粒表面光滑,大小均匀。常温下以0.2C倍率循环30次,LiMn1.97Bi0.03O3.95F0.05容量保持率为90.88%,远高于未改性LiMn2O4的86.51%,常温及55℃下以1 C倍率循环100次,LiMn1.97Bi0.03O3.95F0.05容量保持率分别为91.81%和83.69%,高于未改性的78.65%和71.82%。Bi和F复合掺杂提高了材料的稳定性和循环性能,尤其是高温循环性能。     

炭黑包覆Al2O3掺杂LiMn2O4正极材料的研究

使用醋酸锂、醋酸锰和氧化铝为原料,采用高温固相法合成掺杂Al离子的LiMn2O4二级产物。合成化学计量比为n(Li)∶n(Mn)∶n(Al)=1.3∶1.9∶0.1。首次烧结温度450℃,烧结时间4h;二次烧结温度750℃,煅烧时间为40h。合成样品采用XRD进行材料表征。测试结果表明:合成样品为尖晶石结构,结晶度较高。所得样品使用炭黑包覆处理,并制成实验性电池,对其进行交流阻抗测试(EIS)分析、循环伏安特性(CV)测试、充放电及循环性能测试分析。实验结果表明:包覆后的正极材料改善了LiMn2O4的大电流充放电性能,该材料在0.5C的首次放电比容量为93mAh/g;包覆材料增强了在大电流充放电下的容量保持率,极大地改善了电池的循环性能,该材料在充放电倍率为0.2C时,32次循环后的容量保持率为92.5%。     

基于碳纳米管-Fe_xO_y复合材料电极的电化学性能

本文主要研究以碳纳米管(carbon nanotubes,CNTs)-FexOy复合材料作为电极分别在水溶液和凝胶电解质中的电化学性能。采用化学气相沉积法制备CNTs薄膜,并利用超声雾化热解法于不同的沉积时间下制备FexOy与其复合制作成电极。对复合电极进行形貌表征及电化学性能检测,包括循环伏安、恒流充放电及交流阻抗测试。结果分析表明,电极的比电容随着沉积时间的增加而增加,且均高于纯CNTs电极,同时界面电荷传递电阻随之减小;然而随着沉积时间的继续增大,样品比电容和能量密度明显下降。沉积10min样品在凝胶电解质的循环伏安测试中比电容达到最大值102.8 F·g-1。     

尖晶石LiMn2O4表面包覆MgO及其性能

Mn^2 在电解液中的溶解是引起LiMn2O4正极材料性能恶化的重要原因。用沉淀法在LiMn2O4表面包覆一层Mg(OH）2,再进行热地理,制备由表面包覆MgO的LiMn2O4。用X光电子能谱、扫播电镜和X射线衍射对包覆前后的LiMn2O4的结构进行了表征。充放电测试结果表明．经表面修饰处理后LiMn2O4的循环及高温性能明显改善。研究结果表明表面修饰北理可以抑制正极材料和电解液之间的相互作用．是改善锂离子二次电池正极材料性能的有效途径。     

水热法制备CoFe2O4/石墨烯复合物及其电化学性能

本研究采用水热法制备了质量比为2∶1的CoFe2O4/石墨烯(CoFe2O4/graphene)复合物,利用XRD、FT-IR和TEM对样品的结构和形貌进行了表征,采用循环伏安法(CV)和恒电流充放电测试研究了其电化学性能。结果表明,CoFe2O4均匀的分布在石墨烯表面,粒径大约为10nm。在0.5A/g的电流密度下,比电容为105F/g。1000次循环后,电容保持率在90%以上。     

LiNi0.8Co0.15Al0.05O2/石墨锂离子电池高荷电存储老化机理研究

高荷电存储寿命对锂离子电池的使用性能具有重要影响, 但是相关研究却较为缺乏。本研究通过高温加速实验, 研究了LiNi_0.8Co_0.15Al_0.05O₂(NCA)/石墨锂离子电池在55 ℃下的存储寿命, 分析了正负极材料在电池寿命终点时的电化学性能和界面变化。研究结果表明, 在55 ℃、高荷电状态下NCA/石墨锂离子电池的存储寿命约为90 d。在寿命终点时, 正负极活性材料的容量有一定下降, 但不是电池容量衰减的主要原因。界面分析表明, 存储后负极表面固体电解质界面(SEI)膜增长明显, 而正极表面固体电解质界面(PEI)膜无明显变化。SEI膜的增长主要是由于电解液溶剂和锂反应, 造成石墨内锂损失, 使电池内可循环锂减少, 这是NCA/石墨电池在存储过程中容量损失的主要原因。     

Thickness dependence of structural and ferroelectric properties of sol-gel Pb(Zr0.56Ti0.44)0.90(Mg1/3Nb2/3)0.10O3 films

Sol-gel Pb(Zr_0.56Ti_0.44)_0.90(Mg_1/3Nb_2/3)_0.10O₃ (PZT-PMN) films were prepared onto the Ti/Pt/Ti bottom electrode by multilayer spin coating. The film thickness ranged from 0.22 to 0.88 μm. The Pt top electrodes were deposited on the PZT-PMN films by DC sputtering. The structural and ferroelectric properties of PZT-PMN films were investigated as a function of film thickness by X-ray diffraction (XRD), scanning electron microscopy (SEM), cross-sectional transmission electron microscopy (XTEM), and by measuring the relative permittivity. The film retains the tetragonal perovskite structure with the [111] and [100] preferred orientations perpendicular to the film surface independent of film thickness. The [100] texture increases with increasing film thickness although the [111] texture is always predominant. The film consists of columnar grains. The average grain size is nearly independent of film thickness. The surface layer containing fine grains about 30 nm in diameter is induced on the top of the film. As the film thickness exceeds 0.44 μm, the number of the fine grains decreases remarkably. The crystalline interface layer about 10 nm thick is formed between the film and the bottom electrode. This interface layer is composed of Pt, Pb, Zr, Ti and O, while it is rich in Ti and deficient in Pb and O as compared with the inside of the film. The measured relative permittivity of the film increases with increasing film thickness, following the low permittivity interface model. On the basis of this model, the relative permittivity is estimated to be 3200 for the intrinsic PZT-PMN film, 750 for the surface layer and 50 for the interface layer.     

Mechanism of surface modification of a porous-coated Ti-6Al-4V implant fabricated by electrical resistance sintering

A porous-coated Ti-6Al-4V implant was fabricated by electrical resistance sintering, using 480 F capacitance and 1.5 kJ input energy. X-ray photoelectron spectroscopy (XPS) was used to study the surface characteristics of the implant material before and after sintering. There were substantial differences in the content of O and N between as-received atomized Ti-6Al-4V powders and the sintered prototype implant, which indicates that electrical resistance sintering alters the surface composition of Ti-6Al-4V. Whereas the surface of atomized Ti-6Al-4V powders was primarily TiO₂, the surface of the implant consisted of a complex of titanium oxides as well as small amounts of titanium carbide and nitride. It is proposed that the electrical resistance sintering process consists of five stages: stage I – electronic breakdown of oxide film and heat accumulation at the metal-oxide interface; stage II – physical breakdown of oxide film; stage III – neck formation and neck growth; stage IV – oxidation, nitriding, and carburizing; and stage V – heat dissipation. The fourth stage, during which the alloy repassivates, is responsible for the altered surface composition of the implant.     

纳米碳管电极成型工艺对其电吸附脱盐性能影响的研究

添加不同种类和含量的粘结剂, 通过冷压和热压方法, 结合炭化处理等不同工艺制备纳米碳管电极, 利用DC-5电池测试仪分析其在盐水中的充放电性能, 比较其电吸附比电容和等效电 阻, 发现当聚四氟乙烯(PTFE)的量为10%, 聚偏氟二乙烯(PVDF)的量为15%时, 电极可以冷压成型; 酚醛树脂(PR)的量为20%时, 电极可以热压成型, 随着粘结剂的增加, 电极在盐水中的电吸 附比电容降低, 等效电阻增大. 通过纳米碳管电极表面结构、形貌、亲水性及在盐水中电吸附电容和等效电阻的分析, 对其脱盐性能进行比较, 发现添加20%PR粘结剂热压成型电极经 炭化后, 其比表面积大, 内部孔隙丰富, 亲水性好, 在盐水中电吸附比电容大, 等效电阻小, 电吸附脱盐效果最为显著.     

Charge trapping characteristics of Al2O3/Al-rich Al2O3/SiO2 stacked films fabricated by radio-frequency magnetron co-sputtering

A thin-film structure comprising Al₂O₃/Al-rich Al₂O₃/SiO₂ was fabricated on Si substrate. We used radio-frequency magnetron co-sputtering with Al metal plates set on an Al₂O₃ target to fabricate the Al-rich Al₂O₃ thin film, which is used as a charge storage layer for nonvolatile Al₂O₃ memory. We investigated the charge trapping characteristics of the film. When the applied voltage between the gate and the substrate is increased, the hysteresis window of capacitance-voltage (C-V) characteristics becomes larger, which is caused by the charge trapping in the film. For a fabricated Al-O capacitor structure, we clarified experimentally that the maximum capacitance in the C-V hysteresis agrees well with the series capacitance of insulators and that the minimum capacitance agrees well with the series capacitance of the semiconductor depletion layer and stacked insulator. When the Al content in the Al-rich Al₂O₃ is increased, a large charge trap density is obtained. When the Al content in the Al-O is changed from 40 to 58%, the charge trap density increases from 0 to 18 × 10¹⁸ cm^− 3, which is 2.6 times larger than that of the trap memory using SiN as the charge storage layer. The device structure would be promising for low-cost nonvolatile memory.     

Analysis of interface states in Au/ZnO/p-InP (MOS) structure

Zinc oxide (ZnO) film was deposited on p-type InP substrate by means of radio frequency magnetron sputtering technique and thus the Au/ZnO/p-InP (MOS) structure was fabricated. The crystal structure and surface morphology of ZnO film deposited on InP were characterized by X-ray diffraction and atomic force microscopy, respectively. The analysis of interface states of the structure is studied using admittance (Y?=?G?+?iωC) measurements at room temperature. It is observed that the capacitance and conductance measurements change with frequency. This change is attributed to the presence of interface states. To determine the interface state density (N_ss), the high-low frequency (C_HF–C_LF) capacitance, Hill–Coleman and conductance methods were used. The N_ss values obtained from these methods are in agreement with each other. Furthermore, the effect of the series resistance (R_s) on admittance measurements was investigated. Thus, the obtained results suggest that the prepared structure can be used in various electronic applications.     

Fe/Bi0.5Sb1.5Te3热电元件高温稳定性研究

热电元件的界面高温稳定性是决定热电器件服役性能和应用前景的重要因素,而阻挡层和热电材料之间的界面扩散和界面电阻则是评价热电元件高温稳定性的主要标准.为了进一步提升P型碲化铋热电器件的界面稳定性,本研究采用高通量筛选的方法选定适用于P型碲化铋的Fe阻挡层材料.通过一步烧结的方法制备了Fe/P-BT的热电元件,并系统研究了...     

涂覆热分解与电化学聚合法制备聚苯胺/RuO2复合电极材料

通过涂覆热分解法并结合电化学聚合法制备得到聚苯胺(PANI)/RuO₂电极材料。使用涂覆热分解法于260℃热处理3 h制备RuO₂薄膜, 通过电化学聚合法将PANI粒子沉积在RuO₂薄膜上, 并在80℃加热12 h。采用XRD分析PANI/RuO₂复合物晶相, 采用SEM观察PANI/RuO₂复合电极材料的形貌变化。利用循环伏安及恒流充放电测试了该复合电极的电化学性能。结果表明, PANI沉积时间为25 min, 该PANI/RuO₂复合电极的最大电容量为9.72 F, 比电容为452 F·g^-1, 充放电曲线体现了较低的电压降、等效串联电阻及良好的充放电性能。经1000次循环伏安后, 其比电容损失约为11%。     

The effect of heat treatment on physical properties of nanograined (WO3)1-x-(Fe2O3)x thin films

Thin films of (WO₃)_1-x-(Fe₂O₃)_x composition were deposited by thermal evaporation on glass substrates and then all samples were annealed at 200-500 °C in air. Optical properties such as transmittance, reflectance, optical bangap energy, and the optical constants of the “as deposited” and the annealed films were studied using ultraviolet-visible spectrophotometry. It was shown that the annealing process changes the film optical properties which were related to Fe₂O₃ concentration. Moreover, using X-ray photoelectron spectroscopy, we have indicated that WO₃ is stoichiometric, while iron oxide was in both FeO and Fe₂O₃ compositions so that the FeO composition converted to Fe₂O₃ after the annealing process. Using atomic force microscopy, it was observed that surface of the “as deposited” films were smooth with a nanometric grain size. The film surface remained unchanged after annealing up to 300 °C. Surface roughness and the grain size of the films with x = 0, 0.05, and 0.75 highly increased at higher annealing temperatures (400 and 500 °C), but were nearly unchanged for medium x-values (0.3 and 0.4).     

Characterization of interface states at Au/SnO2/n-Si (MOS) structures

The purpose of this paper is to characterize the interface states in Au/SnO₂/n-Si (MOS) structures. The characteristic parameters of the interface states are derived from capacitance-voltage (C-V) and conductance-voltage (G/ω-V) measurements as a function of frequency. The C-V and G/ω-V measurements have been carried out in the frequency range of 1 kHz to 1 MHz at room temperature. At each frequency, the measured capacitance and conductance decrease with increasing frequency due to a continuous distribution of the interface states. The frequency dispersion in capacitance and conductance can be interpreted in terms of the interface state density (N_ss) and series resistance (R_s). Especially at low frequencies, the interface states can follow the ac signal and yield an excess capacitance. Due to a continuous density distribution of interface states, the C and G/ω values decrease in depletion region with increasing frequencies. At high frequencies, the effect of series resistance on the capacitance is found appreciable due to the interface state capacitance decreasing with increasing frequency. Experimental results show that the locations of interface states between SnO₂/Si and series resistance have a significant effect on electrical characteristics of MOS structures.