VLSI芯片的可测试性、可调试性、可制造性和可维护性设计

CMOS器件进入深亚微米阶段，VLSI集成电路（IC）继续向高集成度，高速度，低功耗发展，使得IC在制造、设计、封装，测试上都面临新的挑战，测试已从IC设计流程的后端移至前端，VLSI芯片可测试性设计已成为IC设计中必不可少的一部分，本文介绍近几年来VLSI芯片可测试性设计的趋势，提出广义可测试性设计（TDMS技术）概念，即可测试试性，可调试性，可制造性和可维护性设计，并对可调试性设计方法学和广义可测试性设计的系统化方法作了简单介绍。     

数字信号处理器芯片核NDSP25的可测试性设计

介绍了可测试性设计的一般方法，着重讨论了NDSP25数字信号处理器芯片核的可测试性设计策略，以及可测试性设计的实现，并对可测试性设计的结果进行了统计和分析。     

空间以太网数据总线可测试性设计与分析

空间应用领域不断拓展使得空间有效载荷数据管理与传输越来越复杂,对空间数据总线的可靠性、测试的有效性提出更高要求。针对数据总线的可测试性现状及以太网的空间应用情况,提出空间有效载荷以太网数据总线测试性设计要求,基于FMECA及多信号模型对空间以太网数据总线进行可测试性分析,设计。通过搭建空间以太网仿真平台对可测试性设计进行验证。结果表明：设计达到可测试性要求,加入可测试性设计后对系统的性能影响较小,对空间数据总线的测试性设计具有实际的指导意义。     

数字电路功能级上的可测试性设计

集成电路规模的增加,使电路的可测试性成了设计阶段必须考虑的问题,这就需要预先确定电路中各部份的测试性能。本文用概率的观点分析了电路功能(模块)级上的可测试性,提出了可控、可观谱的概念,并导出一套新的模块级上的可控、可观测度的计算方法,从而使大规模电路的可测试性设计成为可能。     

基于边界扫描技术的嵌入式处理器测试方法研究

现代先进微处理器有非常高的集成度和复杂度,而且芯片管脚数相对较少,必须要有一定的自测试设计和其它的可测试性设计来简化测试代码,提高故障覆盖率。该文提出了嵌入式处理器80386EX芯片内部功能的测试方案,设计了符合JTAG规范的测试系统结构,实现了芯片的内部功能部件的测试。接着,通过实验证明了文章所提方法的可行性。最后讨论了下一步的研究工作。     

实例研究-模糊芯片F200的设计、验证和测试

本文介绍模糊推理协处理器VLSI芯片F200的设计,给出了详细的芯片设计流程,并重点讨论了有关芯片的可测试性设计、设计验证和测试等问题。     

可测试性设计技术在一款通用CPU芯片中的应用

可测试性设计(Design-For-Testability,简称DFT)是芯片设计的重要环节,它通过在芯片原始设计中插入各种用于提高芯片可测试性的硬件逻辑,从而使芯片变得容易测试,大幅度节省芯片测试的成本。文中介绍了在一款通用CPU芯片的设计过程中,为提高芯片的易测性而采取的各种可测试性设计技术,主要包括扫描设计(ScanDesign)、存储器内建自测试(Build-in-self-test,简称BIST)以及与IEEE1149.1标准兼容的边界扫描设计(BoundaryScanDesign,简称BSD)等技术。这些技术的使用为该芯片提供了方便可靠的测试方案。     

软件的可测试性设计

软件产品开发规模的扩大和数量的增长迫切需要找到一种方法来增加软件测试的有效性。可测试性设计可以增强软件的可测试性,降低测试的强度。该文讨论了软件可测试性的特征和影响软件测试的因素,以及改进软件可测试性设计的几种方法。建议在软件开发的整个周期中融入软件的可测试性的设计。     

基于IEEE 1500标准的嵌入式存储器测试壳的研究

超大规模集成电路和超深亚微米技术的快速发展,促使了系统芯片(System on Chip,SoC)的产生,同时在SoC中也集成了越来越多的嵌入式存储器,因此嵌入式存储器对SoC芯片的整体性能有非常重要的影响;文章针对SoC中的嵌入式存储器的可测试性设计展开研究;文章基于IEEE 1500标准针对DRAM和SRAM设计了具有兼容性的存储器的测试壳结构,并结合BIST控制器,在Quar-tusⅡ平台上,采用硬件描述语言对测试壳在不同测试指令下的有效性和灵活性进行验证,结果表明文章所设计的测试壳结构达到了预期的要求。     

基于在线测试的边界扫描器件测试原理

当今,微电子技术已进入集成电路(VLSI)时代.随着芯片电路的小型化及表面封装技术(SMT)和电路板组装技术的发展,使得传统测试技术面临着巨大的挑战.为了提高电路和系统的可测试性,提出了一种新的电路板测试方法-边界扫描测,也称JTAG标准.本文简单介绍基于BoundaryScan器件在ICT设备中测试原理.     

功耗限制下RTL数据通路非扫描BIST方法的延时分析

可测性设计（DFT）方法广泛应用于数字电路测试中．通过添加测试硬件,用来降低测试的复杂性。但添加测试硬件后,往往会引起电路的延时变大,从而降低电路的性能,甚至引起延时故障。针对寄存器传输级（RTL）数据通路,文献[1]提出了两种功耗限制下非扫描内建自测试（BIST）方法。跟以前的方法相比较,这两个方法取得较短的测试应用时间和较低的测试硬件开销。本文对这两个方法对电路延时的影响进行分析。实验结果表明,在保持同样的测试应用时间和测试硬件开销的前提下,电路的延时有稍微增加。     

Testing and built-in self-test – A survey

As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This built-in self-test (BIST) approach not only offers economic benefits but also interesting technical opportunities with respect to hierarchical testing and the reuse of test logic during the application of the circuit.Starting with an overview of test problems, test applications and terminology this survey reviews common test methods and analyzes the basic test procedure. The concept of BIST is introduced and discussed, BIST strategies for random logic as well as for structured logic are shown.     

An Automatic DFT System for the Silc Silicon Compiler

This article discusses design for testability automation for the Silc silicon compiler under development at GTE Laboratories, Inc. Our modular design for testability uses both built-in self-test and scan-path techniques for Slic's full custom VLSI designs. A test controller coordinates the testing of the chip's modules. Testability evaluation is performed using controllability/observability methods, and using a method based on information theory. A testable-by-construction approach is followed in order to synthesize blocks of testable logic. A testability ?expert? manages testability knowledge during the synthesis process and makes the ultimate testability decisions.     

Robust scan-based logic test in VDSM technologies

The customer expects defect-free chips, at consumer prices, making thorough manufacturing test mandatory. With increasing chip density, the addition of say 10,000 gates is no longer of great impact (these would occupy only 0.1 mm² on a 0.18-μm die); satisfying timing requirements and not exceeding package or system power requirements are the principal implementation objectives. The new availability of silicon real estate has transformed the design-for-testability environment. Implementing contemporary application-specific integrated circuit (ASIC) designs based on standard-cell and gate array technologies now requires design flows that incorporate DFT. Robust design for testability in very deep-submicron (VDSM) technologies is essential to volume manufacturing. The most common structural test method is scan-based logic test, which is now the backbone of manufacturing test. Using this method, commercial ATPG tools rely on test-mode reconfiguration of the circuit to a pseudo-combinational one, ensuring its access, controllability, and observability. Each state bit is transformed into a stage (either a flip-flop or master-slave latch pair) of a shift register or scan chain accessible from chip pins. The author points out ways to avoid pitfalls in implementing effect scan-based test. These include modifying register-transfer-level circuit representations for testability, using a single clock edge design, and providing clock control     

Knowledge-based system tool for high-level BIST design

The paper describes a knowledge-based computer-aided design (CAD) tool to plan the use of built-in self-test (BIST) in VLSI design. Software is being developed using the LISP object-oriented programming system (LOOPS), a multiparadigm programming environment on Xerox 1108 workstations. The software employs object-oriented, rule-based and procedural programming to model various aspects of the system. The knowledge on which the system is based has been derived from a study group of design-for-testability (DFT) experts drawn from a consortium of five UK companies working under the Alvey VLSI programme. The motivation for the tool is that BIST is expected to have a positive impact on test costs. A range of artificial intelligence techniques are used, including rule-based systems and planning.     

基于FPGA的板级BIST设计和实现策略

为解决复杂电路板的测试问题,边界扫描、内建自测试等可测性设计技术相继发展,针对目前板级可测性设计发展状况,提出了基于FPGA的板级BIST设计策略;通过阐述存储器模块、逻辑模块和模拟模块三大部分的BIST设计,说明了基于FPGA进行板级模块BIST设计的灵活性和优势;最后,给出了在FPGA内构建BIST控制器的方法,并介绍了FPGA自测试的实现以及在板级设计过程中要考虑的问题。     

基于BIST软件测试思想的单元测试框架

BIST是一种成熟的硬件可测性设计的方法,BIST软件测试思想则借用了该技术,它主要包括模板和自治测试部分两大基本结构。在该思想的指导下,整合测试用例、测试点、插装函数、测试报告等测试要素,提出了各个要素的存储或使用方式,以路径覆盖为测试目标,提出了一种BIST软件自测试的测试框架。实践证明,该测试框架有利于BIST软件测试思想的进一步研究和实现。     

Automated BIST for sequential logic synthesis

An automated built-in self-test (BIST) technique for general sequential logic is described that can be used directly at all levels of testing from device testing through system diagnostics. The technique selectively replaces existing system memory elements with BIST flip-flop cells, which it then connects to form a circular chain. Data are compacted and test patterns are generated simultaneously. The approach has been incorporated in a system for behavioral model synthesis to implement BIST in VLSI devices based on standard cells and in circuit packs based on PLDs, automatically. Seven production VLSI devices have been implemented with this automated BIST approach. Area overhead was between 6% and 19% for a fault coverage of 90%+ with the BIST capability alone     

The hierarchical logic schematic capture

A graphic package called Hierarchical Logic Schematic Capture (CAPTURE) has been developed as a design aid for fast turnaround and high complexity LSI/VLSI designs. The data structure to represent the complete model of a hierarchical logic schematic and to handle automatic node assignment is discussed. Conclusions are drawn with the case study of using the package to design a given circuit.