MOS Integrated Circuit Reliability

This paper presents information on the reliability of MOS integrated circuits based on p-channel enhancement-mode transistors, and describes their failure modes and mechanisms. The principal failure mechanisms were ion migration at the surface and oxide shorting. The results of experimental studies of the effects of variations in construction, processing, and levels of stress are presented, and are compared with other available information on MOS integrated circuit reliability. The failure rate for commercially available complex MOS arrays is on the order of 0.001 to 0.01 per 1000 h of operating life at 125°C for arrays containing approximately 600 p-channel transistors. This corresponds to a failure rate on the order of 5 × 10?6 to 5 × 10?5 per equivalent gate per 1000 h. The effects of device complexity, operating temperature, and other factors are discussed. A reliability prediction equation for MOS integrated circuits is derived from available information. An overall activation energy for functional failure mechanisms of approximately 5 kcal/mole (?0.2 eV/molecule) is considered applicable to typical MOS integrated circuits. Thus, the failure rate of MOS devices operated at 50°C ambient temperature can be predicted to be on the order of 10?6 to 10?5 per equivalent gate per 1000 h.     

An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

Reliability of Complementary MOS Integrated Circuits

This paper describes the results of tests of the stability and reliability of complementary MOS (CMOS) integrated circuits (IC). Operating life-tests at 125°C indicated excellent stability of electrical characteristics of both n-channel and p-channel transistors. Over three million device-hours of accelerated operating life-tests indicated a calculated failure rate, at a 60-percent s-confidence level, of 0.08%/1000 hours at 125°C, which corresponds to 0.01%/1000 hours at 55°C or 0.003%/1000 hours at 25°C. Field-usage reliability data on three satellites in orbit indicate a total failure rate of 0.003%/1000 hours (over thirty-four million operating hours with no failures). The observed failure rates are compared with other available data on IC reliability, and it is concluded that the reliability of CMOS ICs is equal to that of p-channel MOS circuits or of bipolar digital circuits of equal complexity, when each type is prepared by a well-controlled process, and operated at the same temperature. The operating temperature of CMOS IC chips in electronic systems is, however, generally lower since logic functions are accomplished at lower dissipation per gate.     

An advanced bipolar-MOS-I2L technology with a thin epitaxial layer for analog-digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I²L) and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-µm design rule. Thin epitaxial layer (leq 2 microm) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n⁺buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

Multiple layers of CMOS integrated circuits using recrystallizedsilicon film

This letter presents a method to fabricate high performance three-dimensional (3-D) integrated circuits based on the conventional CMOS SOI technology. The first layer of transistors is fabricated on SOI and the second layer is fabricated on large-grain polysilicon-on-insulator (LPSOI), using oxide as the interlayer dielectric. The LPSOI film is formed by the recrystallization of amorphous silicon through metal induced lateral crystallization (MILC). The grain size obtained by the LPSOI process is much larger than the transistors and the transistor performance is similar to those fabricated on the SOI layer. Three-dimensional (3-D) CMOS inverters have been demonstrated with p-channel devices stacking over the n-channel ones     

Silicon-on-insulator approach for power IC's integrating verticalDMOS and polycrystalline silicon CMOS thin-film transistors

A novel approach for the monolithic integration of low-voltage logic and analog control circuits with vertical-current flow power transistors is described. This is achieved by fabricating a CMOS device family, using polycrystalline-silicon thin-film transistors (TFTs), on the field oxide of a single-crystal power device. Parasitic interactions between the control and power devices are eliminated in a simple, inexpensive, and easily manufacturable process. The technology is capable of supporting both MOS and bipolar power devices and the presence of the TFT circuits places no restriction on the maximum voltage or current of the power device. The TFTs exhibit good electrical characteristics and the power devices are not compromised by the addition of the TFT control circuits. This concept is demonstrated by the fabrication of a vertical DMOS power transistor with >100-V, >45-A capability, monolithically integrated with current-limiting and temperature-limiting functions     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

Process investigations for a 30-GHz fT submicrometerdouble poly-Si bipolar technology

Major process issues are investigated to establish a manufacturable process for a 30-GHz f_T deep-trench isolated submicrometer double polysilicon bipolar technology. A thinner deep-trench surface oxide minimizes crystal defects generated by thermal stresses during the subsequent processes, and significantly improves collector-to-emitter leakage currents in npn transistors. The effects of reactive-ion-etch (RIE) process used for the base surface oxide etch are evaluated in terms of current gain, emitter resistance, and cutoff frequency of the npn transistors. Silicon surface roughness created by an RIE process produces a nonuniform interface oxide film between the emitter polysilicon and the silicon surface, which results in a lower current gain due to a retardation of arsenic diffusion from the emitter polysilicon through the unbroken thicker portion of the interface oxide film. Lateral pnp transistors and Schottky diodes using a vanadium silicide are characterized as a function of epitaxial layer thickness. Schottky diodes are integrated with high performance npn transistors without using extra photo-masking process steps. The reverse leakage currents of Schottky diodes fabricated by using an RIE process are acceptable for practical use in circuits. A planarization process is investigated by employing an RTA reflow of BPSG films deposited in an LPCVD furnace. The maximum RTA reflow temperature is limited to 1000°C in order to maintain an acceptable integrity of TiSi₂ layer formed on top of the n+ polysilicon layer. The planarity achieved by an RTA reflow at a temperature between 975°C and 1000°C is acceptable for double polysilicon bipolar integrated circuits using metal interconnects produced by an electroplated gold process     

Integrated MOS analog delay line

A 16-stage, fixed or variable analog delay line that makes use of integrated p-channel MOS field-effect transistors is described. The delay line relies on `sample' and `hold' techniques and makes use of the inherent characteristics of p-channel MOS transistors. The delay line provides unit gain with a dynamic range of 1 volt. The bandwidth of the delay line is 0.8 MHz under nonsampling conditions. The lowest sampling rate was found to be 50 Hz. A built-in capacitive compensation technique using signals opposite in phase reduces feedthrough of the sampling signal and final filtering requirements. Investigation of the problems of obtaining unity gain and dynamic range led to the development of a computer-aided analysis that provides a family of dc transfer characteristics of cascaded p- channel MOS `half-stages' when a variation of either a material or electrical parameter is made.     

Comparing MOS and bipolar integrated circuits

In terms of speed and speed/power performance, bipolar integrated circuits are superior to metal-oxide-semiconductor integrated circuits. This superiority is based on the high transconductance inherent in bipolar transistors and is technology-independent. For the MOS case, transconductance is highly technology-dependent, and hence the performance difference will probably diminish in the future. Comparisons of the two technologies in their mid-1966 forms are made; the bipolar performance advantage in most cases is between 10 and 100. MOS integrated circuits have an area-per-function advantage ratio of about 5 for equivalent-function circuits, but a ratio of between 5 and 10 when circuits exploiting the unique MOS properties are considered. In addition, MOS processing is simpler than bipolar processing by approximately 40 percent.     

DIFMOS—A floating-gate electrically erasable nonvolatile semiconductor memory technology

Electrically alterable read-only memories (EAROM's) or reprogrammable read-only memories (RPROM's) can be fabricated using a single-level metal-gate p-channel MOS technology with all conventional processing steps. Given the acronym DIFMOS for dual-injector floating-gate MOS, this technology utilizes the floating-gate technique for nonvolatile storage of data. Avalanche injection of hot electrons through gate oxide from a special injector diode in each bit is used to charge the floating gates. A second injector structure included in each bit permits discharge of the floating gate by avalanche injection of holes through gate oxide. The overall design of the DIFMOS bit is dictated by the physical considerations required for each of the avalanche injector types. The end result is a circuit technology which can provide fully decoded bit-erasable EAROM-type circuits using conventional manufacturing techniques.     

Technology and performance of integrated complementary MOS circuits

The desirable characteristics of complementary MOS circuits are low standby power consumption, high speed, and high noise immunity. These require close control and matching of n- and p-channel transistor characteristics. Acceptable limits for mismatch between devices were derived based on circuit considerations and were related to process variables. Predicted performances were achieved using test circuits; feasibility of the technology has been shown. The reliability of fabricated test structures was evaluated.     

Monolithic integration of 5 V CMOS and high-voltage devices

A fully CMOS-compatible HVIC technology has been developed that features 5 V high-performance digital CMOS with high-voltage devices of more than 400 V. This technology uses only one or two masks in addition to standard p-well CMOS technology. Design optimization has been achieved to meet the needs of both CMOS and high-voltage devices. A large number of different devices are available in this technology, including bipolar transistors, lateral MOS gate power devices, and high-voltage p-channel power devices     

Selective low-pressure silicon epitaxy for MOS and bipolar transistor application

The selective low-pressure epitaxy is presented in this paper. In contrast to LOCOS technology, this process starts with structuring a thick field oxide by anisotropic RIE etching. Then monocrystalline silicon is grown selectively in the windows formed. Si-gate MOS transistors have been produced using this technology. In the field of bipolar transistors, reactive ion etching and selective low-pressure epitaxy has been used to optimize the Schottky collector transistor to a nearly one-dimensional structure. These transistors have been built on a submicrometer epitaxial layer.     

Mosfet fabrication using ion beam nitridation

Ion beam nitridation has been suggested as an alternative to the conventional local oxidation process which is used in the fabrication of most metal-oxide-semiconductor (MOS) integrated circuits. The implantation of 2 keV nitrogen ions in doses of up to 8 x 10¹⁷ cm^-2 results in the formation of a silicon nitride layer approximately 10 nm thick. Herein we describe the electrical characteristics of n-channel silicon gate metal-oxide-semiconductor-field-effect-transistors (MOSFETs) fabricated using this modified local oxidation process, and compare them to devices fabricated simultaneously but using the conventional local oxidation technology. The effective device channel lengths and widths are determined from the electrical characteristics of devices with mask (ideal) dimensions of 4, 6, 8 or 10 μm. The ion beam nitrided devices exhibit a significant reduction in the lateral oxidation effect. A 1.3 μm increase in channel width relative to conventional processing is observed for the ion beam nitrided devices with a 690 mm thick field oxide. On the other hand, fixed oxide charge densities are found to increase by a factor of about two due to the nitrogen implantation, and device channel mobilities are reduced by about 25%.     

A Constant-gm Constant-Slew-Rate Rail-to-Rail Input Stage With Static Feedback and Dynamic Current Steering for VLSI Cell Libraries

A constant-g_m input stage featuring both constant small signal and large signal behaviors over the entire input common-mode range is proposed in this brief. A novel static feedback loop is employed to minimize the N and P transconductance mismatch due to process and temperature variations. The output currents of the N and P differential pairs are dynamically steered to keep a constant g_m and a constant slew rate. The overall technique is independent of the operation regions of input transistors, and does not rely on the quadratic characteristics of input MOS transistors. A prototype chip was designed for a 0.35-mum CMOS technology with 3-V power supply. The experimental results demonstrate that a constant-g_m (plusmn3% variations) and a constant slew rate over the entire input common-mode range have been achieved     

Elements of semiconductor-device reliability

Semiconductor-device quality and reliability are discussed in the context of the major factors producing failures, the relationship of process technology and its control to device quality and reliability, the testing procedures used to determine quality levels, and screening procedures that can be employed to segregate certain levels of device quality. Failure rates are presented for transistors and for both bipolar and MOS integrated circuits in several types of packages and for several kinds of device process technology.     

A high-speed complementary silicon bipolar technology with 12-fJpower-delay product

A complementary silicon bipolar technology offering a substantial improvement in power-delay performance over conventional n-p-n-only bipolar technology is demonstrated. High-speed n-p-n and p-n-p double-polysilicon, self-aligned transistors were fabricated in a 20-mask-count integrated process using an experimental test site designed specifically for complementary bipolar applications. N-p-n and p-n-p transistors with 0.50-μm emitter widths have cutoff frequencies of 50 GHz and 13 GHz, respectively. Two novel complementary bipolar circuits-AC-coupled complementary push-pull ECL, and NTL with complementary emitter-follower-display a significant advantage in power dissipation as well as gate delay when compared to conventional n-p-n-only ECL circuits. Record power-delay products of 34 fJ (23.2 ps at 1.48 mW) and 12 fJ (19.0 ps at 0.65 mW) were achieved for these unloaded complementary circuits, respectively. These results demonstrate the feasibility and resultant performance leverage of high-speed complementary bipolar technologies     

Silicon-gate technology

Silicon-gate technology provides an advantageous approach for implementing large-scale integrated arrays of field-effect transistors. Its advantages?principally resulting from the low threshold voltage and the self-aligned gate structure buried under an insulator?ease the problem of interfacing these circuits to bipolar integrated circuits and increase both their performance and functional density, making MOS integrated circuits easier and more economical to use. This article reviews recent progress with this technology and shows its application to the construction of complex digital functions as illustrated by a memory circuit.