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1.
Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints 总被引:1,自引:0,他引:1
Guoqing Chen Friedman E.G. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(2):161-172
Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints determine a design space for the number and size of the repeaters. The minimum power is shown to occur at the edge of the design space. With delay constraints, closed form solutions for the minimum power are developed, where the average error is 7% as compared with SPICE. With bandwidth constraints, the minimum power can be achieved with minimum-sized repeaters. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are also analyzed. By including inductance, the minimum interconnect power under a delay or bandwidth constraint decreases as compared with an RC interconnect. 相似文献
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在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中. 相似文献
4.
在深亚微米设计中,降低能耗和传播延迟是片上全局总线所面对的两个最主要设计目标.本文提出了一种用于片上全局总线的时空编码方案,它既提高了性能又降低了峰值能耗和平均能耗.该编码方案利用空间总线倒相编码和时间编码电路技术的优点,在消除相邻连线上反相翻转的同时,减少了自翻转数和耦合翻转数.在应用该总线编码技术降低总线延时和能耗的设计中,给出了一种总线上插入中继驱动器的设计方法,以确定它们合适的尺寸和插入位置,使得在满足目标延时和翻转斜率要求的同时总线总的能耗最小.该方法可用来为各种编码技术获得翻转斜率约束下的总线能耗与延时的优化折中. 相似文献
5.
Maheshwari A. Burleson W. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2007,15(11):1239-1244
In this paper, hybrids based on current-sensing and repeaters are proposed for on-chip interconnects in an effort to overcome the limitations of these techniques. A novel receiver for current-sensing results in static power savings and allows an easier transition from current-sensing to traditional full rail voltage signals. Measurements of hybrids on a 0.18-m CMOS technology show significant gains over repeater insertion in delay across wire lengths. Hybrids can also be used in placement constrained and low-noise scenarios to achieve delay and power benefits. 相似文献
6.
《Microelectronics Journal》2007,38(4-5):649-655
The effect of voltage-scaling on interconnect delay minimization by CMOS-repeater insertion is analyzed. Analytical models are developed to calculate the optimum number of repeaters as function of CMOS supply voltage. The analytically obtained results are in good agreement with SPICE extracted results. Analysis shows that voltage-scaling decreases power dissipation and the optimum number of repeaters required for delay minimization in long interconnects. Both resistive and inductive interconnects have been considered. At highly scaled voltages, the inductive interconnect has the advantage of lower power-delay product. It is also seen that voltage-scaling affects delay improvement due to repeater insertion. 相似文献
7.
Moreinis M. Morgenshtein A. Wagner I. A. Kolodny A. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(11):1276-1281
Logic gates as repeaters (LGRs)-a methodology for delay optimization of CMOS logic circuits with resistance-capacitance (RC) interconnects is described. The traditional interconnect segmentation by insertion of repeaters is generalized to segmentation by distributing logic gates over interconnect lines, reducing the number of additional, logically useless inverters. Expressions for optimal segment lengths and gate scaling are derived. Considerations are presented for integrating LGR into a VLSI design flow in conjunction with related methods. Several logic circuits have been implemented, optimized and verified by LGR. Analytical and simulation results were obtained, showing significant improvement in performance in comparison with traditional repeater insertion, while maintaining low complexity and small area 相似文献
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Awwad F.R. Nekili M. Ramachandran V. Sawan M. 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(1):322-335
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The use of regenerative feedback repeaters to reduce the delay in programmable interconnections is described. A static, complementary regenerative feedback (CRF) repeater is proposed. This CRF repeater locally regenerates the new level for a fixed time after a transition has been detected. Design issues and limitations are discussed. It is shown that rising transitions can propagate faster than falling transitions through a chain of overdriven nMOS switches with CRF repeaters. Experimental results from a 1.2 μm CMOS implementation show that the loaded delay through 64 switches for static and dynamic repeaters can be reduced by a factor 1.4-2 over conventional repeaters 相似文献
10.
A power-optimal repeater insertion methodology for global interconnects in nanometer designs 总被引:9,自引:0,他引:9
This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty. Furthermore, this methodology is also used to quantify the relative importance of the various components of the power dissipation for power-optimal solutions for various technology nodes. 相似文献
11.
Venkatesan R. Davis J.A. Bowman K.A. Meindl J.D. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2001,9(6):899-912
A multilevel interconnect architecture design methodology that optimizes the interconnect cross-sectional dimensions of each metal layer is introduced that reduces logic macrocell area, cycle time, power consumption or number of metal layers. The predictive capability of this methodology, which is based on a stochastic wiring distribution, provides insight into defining the process technology parameters for current and future generations of microprocessors and application-specific integrated circuits (ASICs). Using this methodology on an ASIC logic macrocell case study for the 100 nm technology generation, the optimized n-tier multilevel interconnect architecture reduces macrocell area by 32%, cycle time by 16% or number of wiring tracks required on the topmost tier by 62% compared to a conventional design where pitches are doubled for every successive pair of levels. A new repeater insertion methodology is also described that further enhances gigascale integration (GSI) system performance. By using repeaters, a further reduction of 70% in macrocell area, 18% in cycle time, 25% in number of metal levels or 44% in power dissipation is achieved, when compared to an n-tier design without repeaters. The key distinguishing feature of the methodology is its comprehensive framework that simultaneously solves two distinct problems-optimal wire sizing and wiring layer assignment-using independent constraints on maximum repeater area for efficient design space exploration to optimize the area, power, frequency, and metal levels of a GSI logic megacell 相似文献
12.
Optimal Voltage Scaling, Repeater Insertion, and Wire Sizing for Wave-Pipelined Global Interconnects
Deodhar V.V. Davis J.A. 《IEEE transactions on circuits and systems. I, Regular papers》2008,55(4):1023-1030
The simultaneous application of voltage scaling, repeater insertion, and wire sizing is proposed in this paper to achieve high performance, low power, and low area on wave-pipelined interconnect circuits. Based on this methodology, design optimizations for three different types of applications are performed and different design metrics are used to obtain the optimal values of supply voltage, number of repeaters, and interconnect dimensions for these applications. The optimal supply voltage for low-power applications is shown to be twice the threshold voltage. In addition, an optimal throughput-per-energy-area (TPEA) design is compared with low-voltage differential signaling (LVDS). The optimal TPEA design is shown to reduce dynamic power by 10% and wire area by 70% compared to LVDS, without any loss of throughput performance. 相似文献
13.
Kaul H. Sylvester D. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2004,12(5):464-476
In this paper, we propose a new circuit structure, the transition aware global signaling (TAGS) receiver, that detects transitions at arbitrary switch points. The major performance advantage of this circuit occurs when it switches before the 50% point in the input transition. The TAGS receiver stores the next state of the line while quiet. Upon detection of a transition at the end of the line the output is temporarily driven by the stored next state. Transitions at the output of the receiver are much faster than at the end of the line since they are generated locally. Its ability to detect transitions before a standard inverter and locally generate them at its output, allows its use at the end of long interconnects with fewer repeaters for the same delay as the standard repeater paradigm. The need for fewer repeaters with the TAGS scheme results in lower power consumption for on-chip global communication, while also reducing the placement overhead involved with large buffer blocks. This is shown in the context of bus optimizations, where TAGS achieves up to 50% reduction in power compared to standard repeaters. In an industrial 0.13-/spl mu/m CMOS process, TAGS receivers enable 8-mm-long buses at 1.5-GHz clock rates without repeaters, while the traditional scheme required three repeaters on the line. An extensive analysis of crosstalk noise in the bus environment shows that TAGS can handle the noise levels produced in typical bus structures. Also, the variation of delay in the bus structure under worst-case power supply noise for the TAGS scheme is typically smaller than the delay variation using the standard repeater scheme. 相似文献
14.
Deodhar V.V. Davis J.A. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(3):308-318
The technique of optimal voltage scaling and repeater insertion is analyzed in this paper to reduce power dissipation on global interconnects. An analytical model for the maximum bit-rate of a very large scale integration interconnect with repeaters has been derived and results are compared with HSPICE simulations. The analytical model is also used to study the effects of interconnect length and scaling on throughput. The throughput-per-bit-energy is analyzed to determine an optimum combination of supply voltage and repeaters for a low-power global interconnect with 250 nm /spl times/ 250 nm cross-sectional dimensions implemented with the 180 nm micro-optical silicon system technology node. It is shown that the optimal supply voltage is approximately equal to twice the threshold voltage. A case study illustrates that a combination of 1 V supply along with one repeater per millimeter increases the throughput-per-bit-energy to over three times that of a latency-centric interconnect of 2 V, which results in a 70% reduction in power dissipation without any loss of throughput performance. 相似文献
15.
This paper proposes a repeater for boosting the speed of interconnects with low power dissipation. We have designed and implemented at 45 and 32 nm technology nodes. Delay and power dissipation performances are analyzed for various voltage levels at these technology nodes using Spice simulations. A significant reduction in delay and power dissipation are observed compared to a conventional repeater. The results show that the proposed high-speed low-power repeater has a reduced delay for higher load capacitance. The proposed repeater is also compared with LPTG CMOS repeater, and the results shows that the proposed repeater has reduced delay. The proposed repeater can be suitable for high-speed global interconnects and has the capacity to drive large loads. 相似文献
16.
Two major characteristics of the coaxial cable that are of paramount importance in the design of coaxial line repeaters are the nominal cable loss and the variation in the cable loss due to seasonal variations in cable temperature. As a result, there are two types of line repeaters used to equalize for the cable loss characteristics. One is a low-noise ultralinear fixed-gain amplifier. It is designated the basic repeater and is used to equalize for the nominal loss of the coaxial cable. The second type, called the regulating repeater, includes a basic repeater plus additional circuitry which automatically corrects for dynamic variations in cable loss due to temperature. Some of the important design techniques that are used to achieve these low-noise ultralinear repeaters are described. In addition, an analysis of the steady-state response of a tandem string of regulating repeaters is included. 相似文献
17.
Signal propagation delay on a multi-source multi-sink bidirectional bus has a dominant effect on high-performance chips. This
work presents a novel greedy algorithm that minimizes the critical propagation delay of an RLC-based bus. Based on the topology
of a multi-source multi-sink bus and the RLC delay model, the proposed algorithm inserts signal repeaters into the critical
path of the RLC-based bus and adjusts their sizes to minimize the maximal propagation delay. This procedure is repeated until
no additional improvement is needed. Several buses with various topologies are tested using the proposed algorithm in deep
submicron technologies. Experimentally, the critical delay in an RLC-based bus can be reduced dramatically by up to 62.4%
with inserted repeater sizes of 24 and execution time of 1.65 s on average. Moreover, average delay reduction, repeater sizes,
and running time for 0.18 μm technology are 5.8%, 6.4%, and 26.2%, respectively, better than those of 0.35 μm. Additionally,
the topologies of all of the RLC-based buses with inserted repeaters in deep submicron technologies are simulated using HSPICE.
The error ratio in the critical delay of a bus with inserted repeaters determined by comparison with HSPICE is 2.7% on average.
The proposed algorithm is simple and extremely practical. 相似文献
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In this paper, we propose a link layer design for mobile hotspots. We design a novel system architecture that enables high-speed Internet access in railway systems. The proposed design uses a number of repeaters placed along the track and multiple antennas installed on the roof of a vehicle. Each packet is decomposed into smaller fragments and relayed to the vehicle via adjacent repeaters. We also use erasure coding to add parity fragments to original data. This approach is called information raining since fragments are rained upon the vehicle from adjacent repeaters. We investigate two instances of information raining. In blind information raining, all repeaters awaken when they sense the presence of the vehicle. The fragments are then blindly transmitted via awakened repeaters. A vehicle station installed inside the train is responsible for aggregating a large enough number of fragments. In the throughput-optimized information raining, the vehicle station selects a bipartite matching between repeaters and roof-top antennas and activates only a subset of the repeaters. It also dictates the amount of transmission power of each activated repeater. Both the bipartite matching and power allocations are individually shown to be NP-complete. Matching heuristics based on the Hungarian algorithm and Gale-Shapley algorithm are proposed. A simplex-type algorithm is proposed as the power allocation heuristics. 相似文献
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《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2008,16(9):1230-1239
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《Broadcasting, IEEE Transactions on》2009,55(3):652-655