Edge-emitting GaInAs-AlGaAs microlasers

The fabrication and characteristics of edge-emitting microlasers with deeply etched distributed Bragg reflector (DBR) mirrors are presented. Using reactive ion etching, the mirrors are formed at both cavity ends of a ridge waveguide laser with an GaInAs-AlGaAs single-quantum-well active layer. The devices have continuous-wave threshold currents as low as 2 and 6 mA at cavity lengths of 80 and 40 μm, respectively. Lasing operation is achieved down to a length of 28 μm. Diffraction limited reflectivities >75% are obtained for third-order gratings, with two DBR periods     

On the frequency dependent drain conductance of ion-implanted GaAs MESFETs

The effect of MESFET structure on the frequency dispersion of drain conductance (g/sub d/) was examined, It was found that a shorter gate length, lower buried p-layer concentration, lower sheet resistance of n/sup +/ layer, and thinner active layer thickness are effective in suppressing the frequency dependent g/sub d/. These phenomena are explained by the presence of deep traps in the depletion layer between the semi-insulating substate and active layer. We also show that the cross-point change of eye-pattern for density of input signal in logic ICs is due to frequency dependent g/sub d/ The cross-point change between mark ratio of 1/8 and 7/8 shows a linear relationship with gd/sub RF//gd/sub dc/ (the ratio of the drain conductance at RF and dc input), These results indicate that an optimized device structure with g/sub d/ small frequency dispersion can be used to realize high-speed and high quality logic ICs.     

Low-frequency noise properties of selectively dry etched InP HEMT's

The low-frequency noise of lattice-matched InAlAs/InGaAs/InP high electron mobility transistors (HEMT's) gate recess etched with a highly selective dry etching process and with conventional wet etching were studied at different gate and drain biases for the temperature range of 77-340 K. The measurements showed a significantly lower normalized drain current 1/f noise for the dry etched HEMT's under all bias conditions. No difference in the normalized gate current 1/f noise could be observed for the two device types. By varying the temperature, four electron traps could be identified in the drain current noise spectra for both dry and wet etched devices. No additional traps were introduced by the dry etching step. The concentration of the main trap in the Schottky layer is one order of magnitude lower for the dry etched HEMT's. No hydrogen passivation of the shallow donors was observed in these devices. We presume hydrogen passivation of the deep levels as the cause for the trap density reduction. The kink effect in the dry etched HEMT's was observed to be reduced significantly compared with wet etched devices which gives further evidence of trap passivation during dry etching. These results show that dry etched InP HEMT's have suitable characteristics for the fabrication of devices for noise sensitive applications     

Process and Device Performance of Submicrometer-Channel CMOS Devices Using Deep-Trench Isolation and Self-Aligned TiSi/sub 2/ Technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-/spl mu/m-deep with 2-/spl mu/m-wide deep trench is etched in the epitaxial layer and is refilled with 1500 /spl Aring/ of thermal silicon-dioxide film and 2/spl mu/m of polysilicon film. The sheet resistances of N/sup +/ and P/sup +/ diffusion and N/sup +/ -doped polysilicon layers were reduced to 3 to 4 /spl Omega//spl square/ by using the self-aligned TiSi/sub 2/ layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi/sub 2/ layer. The 0.5-/spl mu/m-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi/sub 2/ layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static /spl divide/ 4 counter without suffering from Iatchup even at the Iatchup trigger current of 200 mA.     

A novel trench capacitor enhancement approach by selective liquid-phase deposition

For the first time, a novel and simple trench bottle integrated process is demonstrated on dynamic random access memory (DRAM) manufacturing by selective liquid phase deposition (S-LPD) oxide. After photoresist (PR) filled into a deep trench (DT) and was recess etched at around 1.3 /spl mu/m depth, LPD oxide can be selected as a deposit onto the DT sidewall but not as a deposit on the PR surface. This S-LPD oxide is formed by using hexa-fluosilic acid (H/sub 2/SiF/sub 6/) and water without H/sub 3/BO/sub 3/. After the PR is removed, the LPD oxide becomes a protective layer on DT upper portion. Thus, the DT bottom area can be enlarged to form a trench bottle by NH/sub 4/OH wet etching. Compared to conventional DT trench, 20% of capacitance was enhanced by this S-LPD process. This novel and low-cost method is for the first time demonstrated on 200-mm wafer 110-nm trench DRAM technology.     

Improved NiSi salicide process using presilicide N/sub 2//sup +/ implant for MOSFETs

An improved Ni salicide process has been developed by incorporating nitrogen (N/sub 2//sup +/) implant prior to Ni deposition to widen the salicide processing temperature window. Salicided poly-Si gate and active regions of different linewidths show improved thermal stability with low sheet resistance up to a salicidation temperature of 700 and 750/spl deg/C, respectively. Nitrogen was found to be confined within the NiSi layer and reduced agglomeration of the silicide. Phase transformation to the undesirable high resistivity NiSi/sub 2/ phase was delayed, likely due to a change in the interfacial energy. The electrical results of N/sub 2//sup +/ implanted Ni-salicided PMOSFETs show higher drive current and lower junction leakage as compared to devices with no N/sub 2//sup +/ implant.     

Ion implantation impurity profiles in HfO/sub 2/

We implanted B, As, and P ions in a 110-nm-thick layer of HfO/sub 2/ and extracted the parameters of a Pearson IV function. The projected range of the ion implantation was about half of that in SiO/sub 2/. Thus, when impurities were ion implanted in an Si substrate through a thin layer of HfO/sub 2/ or SiO/sub 2/, a smaller dose was retained in the substrate in the former than in the latter case. This effect was demonstrated with P-ion implantation.     

Low-Loss Surface-Mode Waveguides for Terahertz Si–SiGe Quantum Cascade Lasers

A new design of low-loss terahertz waveguide for Si-SiGe quantum-cascade lasers (QCLs) is presented. Periodic surface gratings are used to define waveguides without the requirement of cleaved or etched end facets. As Si cleaves along the (111) planes and not in the vertical direction for standard Si (100) substrates, this significantly aids the fabrication of waveguides. Losses down to 2 cm^-1 with modal overlap of 0.4 can be achieved for shallow gratings with etched depths of only 0.56 mum for an active material layer thickness of 8 mum. Such low loss and high modal overlap is key to any Si-SiGe QCL being realized     

10K Gate I/sup 2/L and 1K Component Analog Compatible Bipolar VLSI Technology -- HIT-2

An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10K I/sup 2/L gates with 1K analog devices is proposed. The new technology, called high-density integration technology-2 (HIT-2), is based on a new structure concept that consists of three major techniques shallow grooved-isolation, I/sup 2/L active layer etching, and I/sup 2/L current gain increase. I/sup 2/L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV/sub CEO/of more than 10 V and an f/sub T/ of 5 GHz, and lateral p-n-p transistors having an f/sub T/ of 150 MHz.     

1710-V 2.77-m/spl Omega/cm/sup 2/ 4H-SiC trenched and implanted vertical junction field-effect transistors

This letter reports the demonstration of a 4H-SiC trenched and implanted vertical-junction field-effect transistor (TI-VJFET). The p/sup +/n junction gates are created on the sidewalls of deep trenches by angled Al implantation, which eliminates the need for epitaxial regrowth during the JFET fabrication. Blocking voltages up to 1710 V has been achieved with a voltage supporting drift layer of only 9.5 /spl mu/m by using a two-step junction termination extension. The TI-VJFET shows a low specific on-resistance R/sub ON-sp/ of 2.77m/spl Omega/cm/sup 2/, corresponding to a record high value of V/sub B//R/sub ON-sp/ equal to 1056 MW/cm/sup 2/.     

GaAs/AlGaAs quantum cascade microlasers based on monolithic semiconductor-air Bragg mirrors

Edge emitting GaAs-based quantum cascade microlasers at a wavelength of 9 /spl mu/m were realised by monolithic integration of photonic bandgap mirrors based on deeply etched air-semiconductor Bragg gratings. The shortest operating device with Bragg mirrors on both sides has a cavity length of 180 /spl mu/m.     

Optimization of microwave properties for ultrahigh-speed etched and unetched lithium niobate electrooptic modulators

Simultaneous phase velocity and characteristic impedance matching of the ultrahigh-speed electrooptic modulators is presented by using the finite-element method (FEM). It is also shown that the dielectric loss in the silica buffer layer is larger than that in the lithium niobate substrate and when these dielectric losses are included, the resulting bandwidth is reduced significantly. It is also shown that for an etched LN structure, it is relatively easier to match both N/sub m/ and Z/sub c/ simultaneously and the resulting optical bandwidth is also greater.     

Increase in photoluminescence of Zn-doped p-type InP after hydrogenation

The authors report on the effect of hydrogenation on the low-temperature (5.5 K) photoluminescence properties of Zn-doped p-type (p approximately 3*10/sup 18/ cm/sup -3/) InP substrates. The photoluminescence spectrum of the as-grown sample shows a Zn/sub In/ acceptor-related transition near the band-edge at 1.386 eV, a Zn-related PL band at 1.214 eV and a phosphorus vacancy V/sub P/-related PL band at 1.01 eV. After hydrogenation of the samples by exposure to hydrogen plasma, which completely passivates the Zn/sub In/ acceptors over a depth of more than 1 mu m, the deep luminescence bands (1.214 and 1.01 eV) disappeared, with a concomitant approximately 2000-fold increase in the intensity of the near-band-edge emission. Such a large increase in radiative efficiency together with the elimination of the deep luminescence bands indicates hydrogen passivation of deep nonradiative centers in addition to passivation of shallow acceptors.<>     

Room temperature operation of ultra-short quantum cascade lasers with deeply etched Bragg mirrors

Mid-infrared GaAs based bound-to-continuum quantum cascade microlasers with ridge waveguide geometry are fabricated by the monolithic integration of deeply etched semiconductor-air Bragg mirrors. Devices with ultra-short cavities of 50 and 150 /spl mu/m can be operated near room temperature (260 K) or at room temperature (300 K), respectively. 50 /spl mu/m-long devices show singlemode emission up to relatively high drive currents due to the large mode spacing of about 30 cm/sup -1/ (340 nm).     

An insulated shallow extension structure for bulk MOSFET

This brief proposes possible a replacement of shallow p-n junction with insulated shallow extension (ISE) structure for bulk MOSFET. The shallow extension is defined by the sidewall thermal oxide rather than the implanted p-n junction. With this insulator for extension and main junction, a heavier halo doping concentration can be used. Thus, the threshold-voltage roll-off and the junction leakage current can be minimized simultaneously. This structure can be a good alternative for junction structures in sub-100-nm regimes.     

Diffusion coefficient of B in HfO/sub 2/

We implanted B ions in a 110-nm-thick HfO/sub 2/ layer, subjected the substrates to various thermal processes, and evaluated the diffusion coefficient by comparing experimental and numerical data. We found that the diffusion coefficient of B in HfO/sub 2/ is higher than that in SiO/sub 2/ by about four orders and almost the same as that in Si. Therefore, the penetration of B through this layer can be expected to be significant, making the use of a cover layer indispensable for p/sup +/ polycrystalline silicon gate devices.     

GaAs vertical-cavity surface emitting lasers fabricated by reactive ion etching

GaAs quantum well vertical-cavity surface emitting lasers fabricated using low damage reactive ion etching are discussed. Lasers which are partially and completely etched through their structure are compared. The surface recombination velocity of exposed GaAs is not exacerbated in deep etched lasers; other loss mechanisms in shallow etched lasers have comparable impact on laser performance. Etched lasers exhibit low voltage and small differential series resistance at threshold, while devices fabricated by a combination of etching and ion implantation possess lower threshold current. It is found that reactive ion etching has little additional effect on laser operation, whereas the different device structures considered do influence laser performance.<>     

InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

We describe a quasi-planar HBT process using a patterned implanted subcollector with a regrown MBE device layer. Using this process, we have demonstrated discrete SHBT with f/sub t/>250 GHz and DHBT with f/sub t/>230 GHz. The process eliminates the need to trade base resistance for extrinsic base/collector capacitance. Base/collector capacitance was reduced by a factor of 2 over the standard mesa device with a full overlap between the heavily doped base and subcollector regions. The low proportion of extrinsic base/collector capacitance enables further vertical scaling of the collector even in deep submicrometer emitters, thus allowing for higher current density operation. Demonstration ring oscillators fabricated with this process had excellent uniformity and yield with gate delay as low as 7 ps and power dissipation of 6 mW/CML gate. At lower bias current, the power delay product was as low as 20 fJ. To our knowledge, this is the first demonstration of high-performance HBTs and integrated circuits using a patterned implant on InP.     

Significant operating voltage reduction on high-speed GaAs-based heterojunction bipolar transistors using a low band gap InGaAsN base layer

We report the fabrication of double heterojunction bipolar transistors (DHBTs) with the use of a new quaternary InGaAsN material system that takes advantage of a low-energy band gap E/sub G/ in the base to reduce operating voltages in GaAs-based electronic devices. InGaP/In/sub 0.03/Ga/sub 0.97/As/sub 0.99/N/sub 0.01//GaAs DHBTs with improved band gap engineering at both heterojunctions exhibit a DC peak current gain over 16 with small active emitter area. The use of the lattice-matched In/sub 0.03/Ga/sub 0.97/As/sub 0.99/N/sub 0.01/ (E/sub G/=1.20 eV) base layer allows a significant reduction of the turn-on voltage by 250 mV over standard InGaP/GaAs HBTs, while attaining good high-frequency characteristics with cutoff frequency and maximum oscillation frequency as high as 40 GHz and 72 GHz, respectively. Despite inherent transport limitations at the present time, which penalize peak frequencies, this novel technology provides comparable RF performance to conventional devices with a GaAs control base layer but at much lower operating base-emitter bias conditions. This technical progress should benefit to the next generation of RF circuits using GaAs-based HBTs with lower power consumption and better handling of supply voltages in battery-operated wireless handsets.     

A novel wet-etching method using joint proton source in LiNbO/sub 3/

By mixing benzoic and adipic acids as the source of proton exchange, wet etched ridge waveguides are fabricated in Z-cut LiNbO/sub 3/. Under appropriate adipic-benzoic acid concentration ratios, the joint proton source can suppress the proton diffusion in the lateral directions, and thus, the sidewalls are much more vertical than the usual. The etched depths are also enhanced for more than 30%. And meanwhile, the fabricated ridge waveguides possess smooth surfaces and the scattering losses are lower than that of the conventionally produced samples.