Comparison of ordered structure in buried oxide layers in high-dose, low-dose, and internal-thermal-oxidation separation-by-implanted-oxygen wafers

The ordered SiO₂ in the buried oxide (BOX) layer of high-dose, low-dose, and internal-thermal-oxidation (ITOX) separation-by-implanted-oxygen (SIMOX) wafers was investigated by X-ray diffraction. From the results, it was found that the SiO₂ molecules in the low-dose and ITOX SIMOX wafers are better ordered than those in the high-dose SIMOX wafer and that the ordered structure of the ITOX layer is different from that of the originally formed BOX layer, suggesting that the ITOX layer has a structure similar to that of the ordered SiO₂ in the thermal oxide layer.     

氢氧复合注入对SOI-SIMOX埋层结构影响的研究

实验研究了氢、氧复合注入对注氧隔离技术制备SOI（Silicon On Insulator)材料埋层结构的影响。用截面透射电子显微镜和二次离子质谱技术分析了退火前后材料的微结构变化。研究表明，氢离子的注入有利于注氧隔离制备的SOI材料埋层的增宽。进一步的结果表明，室温氢离子注入导致的增宽效应比高温注入明显。     

低剂量 SIMOX圆片线缺陷和针孔的研究

用Secco法、Cu-plating法分别表征了低剂量SIMOX圆片顶层硅线缺陷、埋层的针孔密度。结果显示,低剂量SIMOX圆片的顶层硅缺陷密度低,但埋层质量稍差。通过注入工艺和退火过程的进一步优化,低剂量SIMOX将是一种有前途的SOI材料制备工艺。     

Effect of annealing conditions on the formation of low-dose SIMOX structures implanted at 190 keV

The structure of low-dose SIMOX wafers as a function of annealing conditions has been studied using TEM. A set of samples were implanted at 190 keV with doses of 0.5, 0.83 and 1.8 × 10¹⁸cm^-2} oxygen followed by annealing treatment at different ramp rates (1^~ Cmin^-1 or 5^~ Cmin^-1), temperatures (1310 °C or 1350 °C), and holding times (0 or 5 h). The results show that a higher annealing temperature (1350 °C) with a longer holding time improves the quality of the top Si layers and the smoothness of the interfaces in low-dose SIMOX wafers. A slow thermal ramp rate results in sharp interfaces but leads to a high density of Si islands in the buried oxide (BOX) layer. Chemical etching experiment performed on the top Si layer of a low-dose SIMOX shows pipeline structure indicating the inhomogeneous chemical reactivity of the top Si layer. © 2001 Kluwer Academic Publishers     

Atomic structure display of a real silicon surface under light scattering

Angular dependencies of the scattered light intensity were measured on Si wafers that have different crystallographic orientations by using a He-Ne laser (λ = 632.8 nm, 80 μm spot diameter). During the experiment the Si wafer was fixed relative to the incident beam. Regular patterns were found in the azimuthal-angle-resolved scattering curves. Such patterns seem to be caused by the faceted shallow atomic structures of the surface.     

Hydrogen annealing effects on epitaxy of SOI wafer

Thick silicon on insulator (SOI) wafers have been fabricated by chemical vapor deposition (CVD) after separation by implantation of oxygen (SIMOX) process. The hydrogen annealing effects on epitaxial Si layer were studied. The hydrogen annealing could remove the surface damages of substrate caused by SIMOX process and provide a smoother epitaxial substrate. The number of dislocations and stacking faults in the epitaxial layer decreased remarkably by hydrogen annealing SOI substrate. Meanwhile, compared with other reports, our hydrogen annealing did not degrade the buried oxide layer and top Si layer of SOI substrate.     

Synthesis and characterization of amorphous silicon oxide nanowires embedded with Ni nanoparticles

The growth of silicon oxide nanowires (SiOxNWs) was obtained by thermal process of nickel (Ni) nanoparticles (NPs) deposited on silicon (Si) wafer in mixed gases of nitrogen (N₂) and hydrogen (H₂). TEM analysis showed that SiOxNWs had diameters ranging from 100 to 200 nm with lengths extending up to a few μm and their structure was amorphous. SiOxNWs were grown by the reaction between Ni NPs and Si wafer and Ni NPs acted as catalysts. Ni silicides (NixSi) were also formed inside the wafer by Ni diffusion into Si wafer.     

Analysis of gate oxide damage by ultraviolet light during oxide deposition in high density plasma

The UV-induced damages to the gate oxide in a commercially available high-density-plasma dielectric oxide deposition system for the ultra-large integrated circuit fabrication process were analyzed systematically using the metal-oxide-semiconductor capacitors with different antenna ratio. UV-induced damages exclusively in the gate oxide were evaluated by depositing 2500 Å thick oxide layer only once and twice on the two wafers separately and comparing the two results: the deposition of the oxide layer of only 2500 Å did not cause any degradation in the SPDM wafer while the double deposition revealed antenna-ratio dependent shift of the breakdown voltage. The deviation of the values of breakdown voltage of the damaged wafer from its normal ones was found mainly at the center of the wafer where the intensity of the UV light is generally higher in the inductively coupled plasma source.     

A new single-component low-cost emitter etch-back process for silicon wafer solar cells

A way of achieving lightly doped emitter is a combination of a heavy emitter diffusion and emitter etch back, which has an added advantage of phosphorous diffusion gettering. However, this chemical emitter etch-back process must fulfil some critical requirements, e.g. cost-effectiveness, near-conformal Si etching even after deep emitter etch back, controlled Si etch rate, post-etch clean Si surface and lowest safety issues in chemical handling and drainage. In this work, we report a new low-cost (less than 1 US Cents/wafer), single-chemical, non-acidic, high-throughput emitter etch-back process for tube-diffused emitters for crystalline Si wafers. This process uses only sodium hypochlorite solution at 80 °C as the Si etchant. This process is versatile with its applications on phosphorous and boron tube-diffused monocrystalline Si and phosphorous tube-diffused multicrystalline Si wafers. The preparation, usage and drainage of this highly diluted solution are easy and safe. The Si etching process leads to excellent spatial uniformity over large-area Si wafers (243 cm²). With deep etch back resulting in a change of sheet resistance by ~60 Ω/sq, the standard deviation value changes by only 2.7%. High surface conformity in the etch-back surface is evident from reflectance studies. Quasi-steady-state photoconductance and photoluminescence imaging are used to demonstrate improved electrical parameters of the etch-back wafers.     

Catalyst-referred etching of silicon

A Si wafer and polysilicon deposited on a Si wafer were planarized using catalyst-referred etching (CARE). Two apparatuses were produced for local etching and for planarization. The local etching apparatus was used to planarize polysilicon and the planarization apparatus was used to planarize Si wafers. Platinum and hydrofluoric acid were used as the catalytic plate and the source of reactive species, respectively. The processed surfaces were observed by optical interferometry, atomic force microscopy (AFM) and scanning electron microscopy (SEM). The results indicate that the CARE-processed surface is flat and undamaged.     

Catalytic synthesis of ZnO nanorods on patterned silicon wafer—An optimum material for gas sensor

ZnO nanorods have been synthesized over etch-patterned Si (110) wafer using annealed silver thin film as growth catalyst. The growth of ZnO nanorods were performed by a two-step process. Initially, the deposition of Zn thin film was done on the annealed silver catalyst film over etch-patterned Si (110) substrate by thermal evaporation, and then annealed at 800°C in air. The etching of the patterned Si (110) wafers was carried out by 50% aqueous KOH solution. The samples were investigated by optical microscopy, scanning electron microscopy, X-ray diffraction, Raman spectroscopy and room temperature photoluminescence spectroscopy. ‘V’ shaped grooves with no undercut were formed after etching due to the anisotropic nature of the KOH etchant. The etch-patterned wafer was used to provide larger surface area for ZnO growth by forming ‘V’-grooves. This ZnO film may be predicted as a very good material for gas sensor.     

Aktuelle Entwicklungen in der Zühtungstechnologie von CZ‐Si‐Kristallen

Current Developments in CZ Si Crystal Growing Technology The industrial growing of increasingly large and perfect silicon (Si) monocrystals for applications in microelectronics and photovoltaics requires continuous improvement of process control and growing technology. Continuous adaptation and optimization of system technology in terms of reliability, process flexibility and dimensioning are also necessary. The basic principles of industrial silicon crystal growing and the resultant requirements for the Si process andsystem technologies are described in the first part of this series of articles. The constantly increasing requirements for the performance and complexity of the electronic circuits (chips) in accordance with Moore's Law mean that the requirements for the perfection and dimensions of monocrystalline Si wafers and Si crystals are also continuously rising. After the introduction of the 300 mm Si wafer generation in recent years, the next Si wafer generation (450 mm) is therefore being discussed already. The technological and economic effects of these constantly increasing requirements for the necessary system technologies will be set out and discussed in the subsequent articles on the basis of current Si CZ crystal growing systems as well as new system concepts.     

Growth of high Ge content SiGe on (110) oriented Si wafers

Growth of high (above 40%) Ge content SiGe by applying silane and dichlorosilane as Si precursors on (110) Si is investigated. In the case of silane based processes Ge concentration is ~ 20% higher, whereas for dichlorosilane based processes it is ~ 30% lower on (110) Si compared to (100) Si. The morphology of the grown layers is found to be dependent on Ge concentration, layer thickness and process temperature. Use of optimized deposition parameters and adequate thickness results in high quality strained SiGe layers. Integration of high Ge content SiGe layers in multiple gate filed-effect transistor structures shows the expected differences in Ge content on the different Si planes forming Si fin. These differences can be avoided by adjusting the fin orientation on the Si wafer resulting in equal planes on the fin's top and sidewalls. When the investigated SiGe layers are incorporated in the buried channel field effect transistor structures on (110) Si wafers a significant thickening at the active windows edge is observed. It is speculated that this effect is connected with elastic SiGe relaxation caused by a non optimized process temperature.     

Cleavage Fracture of Brittle Semiconductors from the Nanometre to the Centimetre Scale

The objective of this paper is to present the fundamental phenomena occurring during the scribing and subsequent fracturing process usually performed when preparing surfaces of brittle semiconductors. In the first part, an overview of nano‐scratching experiments of different semiconductor surfaces (InP, Si and GaAs) is given. It is shown how phase transformation can occur in Si under a diamond tip, how single dislocations can be induced in InP wafers and how higher scratching load of GaAs wafer leads to the apparition of a crack network below the surface. A nano‐scratching device, inside a scanning electron microscope (SEM), has been used to observe how spalling (crack and detachment of chips) and/or ductile formation of chips may happen at the semiconductor surface. In the second part cleavage experiments are described. The breaking load of thin GaAs (100) wafers is directly related to the presence of initial sharp cracks induced by scratching. By performing finite element modelling (FEM) of samples under specific loading conditions, it is found that the depth of the median crack below the scratch determines quantitatively the onset of crack propagation. By carefully controlling the position and measuring the force during the cleavage, it is demonstrated that crack propagation through a wafer can be controlled. Besides, the influence of the loading configuration on crack propagation and on the cleaved surface quality is explained.     

Influence of plasma heating of wafer substrates on SiO2 deposition rate in a TEOS/O2 high-density plasma CVD system

The influence of plasma heating of the Si and glass wafer substrates on silicon dioxide (SiO₂) deposition rates by a tetraethylorthosilicate/O₂ supermagnetron (high-density) plasma CVD were investigated. With a fixed RF power of 100 W supplied to both upper and lower electrodes, the SiO₂ deposition rate on the Si wafer substrate decreased with increasing wafer-stage temperature, showing a negative activation energy for the deposition rate. When Si and glass wafers were attached to the electrode using adherent thermal conductors, the film thickness increased almost linearly with regard to the deposition time, and both deposition rates became almost the same (about 310 Å/min). When both wafers were simply laid on the electrode without an adhesive bond and hence with poor thermal contact, the film thickness increased nonlinearly with deposition time, showing a gradual decrease in deposition rate with time, being as low as 80 and 150 Å/min, respectively for Si and glass wafers, for a deposition time of 15 min. The difference between the two deposition rates on Si and glass wafers in the case of poor thermal contact to the lower electrode is thought to be caused by plasma heating and related mainly to differences in optical absorption characteristics of the two wafer substrates. Variations in measured thickness distributions across the substrate surface were attributed to an antisymmetric plasma density distribution in the direction perpendicular to the magnetic field lines caused by E×B electron drift.     

The effects of processing conditions on the density and microstructure of hot-pressed silicon powder

Silicon powder was hot pressed into polycrystalline wafers 1.5 in ( 3.8 cm) diameter using various processing conditions. The submicrometre powder used was a by-product of the fluidized bed decomposition process of silane (SiH₄) in the production of silicon pellets. The effect of temperature (1250–1300°C), pressure (2000–3000 p.s.i.; 13.18–20.67 N mm^–2) and ambient (argon, hydrogen, vacuum) on the density of the hot-pressed powder was studied. All wafers processed had densities >92% of the theoretical density of silicon as determined by Archimedes' density measurements. Hydrogen was found to increase the densification rate of powdered silicon. The mechanism by which this occurs is believed to be the reduction of the native oxide layer of the powders resulting in increased surface transport. The microstructure of the polycrystalline wafers was examined by scanning electron microscopy, and transmission electron microscopy. The general microstructure of the polycrystalline wafers consisted of micrometre-sized grains with twins, stacking faults, and dislocations within the grains. However, under hot-pressing conditions of 1300 °C, 2000 p.s.i., and a hydrogen ambient, the grains of the wafer were on the order of 1 mm. The silicon wafers contained iron, aluminium, carbon and oxygen impurities as determined by secondary ion mass spectroscopy.     

Nondestructive evaluation of large-area PZN-8%PT single crystal wafers for medical ultrasound imaging probe applications

A nondestructive quality evaluation and control procedure for large-area, (001)-cut PZN-8%PT wafers is described. The crystals were grown by the flux technique engineered to promote (001) layer growth of the crystals. The wafers were sliced parallel to the (001) layer growth plane. Curie temperature (Tc) variations, measured with matching arrays of dot electrodes (of 5.0 mm in center-to-center spacing), were found to be better than +/- 4.0 degrees C both within wafers and from wafer to wafer. After selective dicing to give final wafers of narrower Tc distributions (e.g., +/- 3.0 degrees C or better), the wafers were coated with complete electrodes and poled at room temperature at 0.7-0.9 kV/mm. Typical overall properties of the poled wafers were: K3T = 5,200 (+/- 10% from wafer to wafer), tan delta < 0.01 (all wafers), and kt = 0.55 (+/- 5%) (all percentage variations are in relative percentages). Then, the distributions of K3S, tan delta, and kt were measured by the array dot electrode technique. The variations in K3S (hence K3T) and kt within individual wafers were found to be within +/- 10% and +/- 5%, respectively. The dielectric loss values, measured at 1 kHz, were consistently low, being < 0.01 throughout the wafers. The kt values determined by the dot electrodes were found to be about 5% smaller than those obtained with the complete electrodes, which can be attributed to an increase in capacitance ratio due to the partial electroding. The k33 values, deduced using the relation K3S approximately (1 - k33(2))K3T, from the mean K3S and overall K3T values, average 0.94 (+/- 2%). The present work shows that the distribution of Tc within wafers can be used as a convenient check for the uniformity in composition and electromechanical properties of PZN-8%PT single crystal wafers. Our results show that, to control deltaK3T and deltakt within individual wafer to < or = 10% and 5%, respectively, the variation in Tc within the wafer should be kept within +/- 3.0 degrees C or better.     

Growth of 3C-SiC on 150-mm Si(100) substrates by alternating supply epitaxy at 1000 °C

To lower deposition temperature and reduce thermal mismatch induced stress, heteroepitaxial growth of single-crystalline 3C-SiC on 150 mm Si wafers was investigated at 1000 °C using alternating supply epitaxy. The growth was performed in a hot-wall low-pressure chemical vapor deposition reactor, with silane and acetylene being employed as precursors. To avoid contamination of Si substrate, the reactor was filled in with oxygen to grow silicon dioxide, and then this thin oxide layer was etched away by silane, followed by a carbonization step performed at 750 °C before the temperature was ramped up to 1000 °C to start the growth of SiC. Microstructure analyses demonstrated that single-crystalline 3C-SiC is epitaxially grown on Si substrate and the film quality is improved as thickness increases. The growth rate varied from 0.44 to 0.76 ± 0.02 nm/cycle by adjusting the supply volume of SiH₄ and C₂H₂. The thickness nonuniformity across wafer was controlled with ± 1%. For a prime grade 150 mm virgin Si(100) wafer, the bow increased from 2.1 to 3.1 μm after 960 nm SiC film was deposited. The SiC films are naturally n type conductivity as characterized by the hot-probe technique.     

Fabrication of high aspect ratio metal nanotips by nanosecond pulse laser melting

The authors have developed an approach to fabricate sharp and high aspect ratio metal tips using nanosecond pulse laser melting. A quartz wafer covered with a thin chromium (Cr) film was placed on top of a second wafer with a sub-micrometer gap between them and the Cr film facing the second wafer. Then an excimer laser pulse (308?nm wavelength, 20?ns pulse duration) was shone from the back of the quartz wafer and melted the Cr film momentarily (several hundred nanoseconds). It is found that the molten Cr films can self-form discrete metal pillars connecting the two wafers. After separating the two wafers, nanotips were formed at the broken pillar necks. The sharpest tip achieved has an apex diameter 10?nm and height 180?nm. The self-formation of Cr pillars between the two wafers was attributed to the attractive electrostatic force caused by the work function difference of two wafers that were in close proximity. This technique could be extended to other metals, and a periodic uniform tip array could be obtained by pre-patterning the metal into identical isolated mesas and precisely controlling the gap between the two wafers.     

The effect of thermal oxidation on the luminescence properties of nanostructured silicon

Herein is reported a detailed study of the luminescence properties of nanostructured Si using X-ray excited optical luminescence (XEOL) in combination with X-ray absorption near-edge structures (XANES). P-type Si nanowires synthesized via electroless chemical etching from Si wafers of different doping levels and porous Si synthesized using electrochemical method are examined under X-ray excitation across the Si K-, L(3,2) -, and O K-edges. It is found that while as-prepared Si nanostructures are weak light emitters, intense visible luminescence is observed from thermally oxidized Si nanowires and porous Si. The luminescence mechanism of Si upon oxidation is investigated by oxidizing nanostructured Si at different temperatures. Interestingly, the two luminescence bands observed show different response with the variation of absorption coefficient upon Si and O core-electron excitation in elemental silicon and silicon oxide. A correlation between luminescence properties and electronic structures is thus established. The implications of the finding are discussed in terms of the behavior of the oxygen deficient center (OCD) and non-bridging oxygen hole center (NBOHC).