A 60 mW per Lane, 4$,times,$23-Gb/s 2$ ^7 -$1 PRBS Generator

An ultra-low-power, 2$ ^7-$1 PRBS generator with four, appropriately delayed, parallel output streams was designed. It was fabricated in a 150-GHz$f_T$SiGe BiCMOS technology and measured to work up to 23 Gb/s. The four-channel PRBS generator consumes 235 mW from 2.5 V, which results in only 60 mW per output lane. The circuit is based on a 2.5-mW BiCMOS CML latch topology, which, to the best of our knowledge, represents the lowest power for a latch operating above 10 Gb/s. A power consumption and speed comparison of series and parallel PRBS generation techniques is presented. Low-power BiCMOS CML latch topologies are analyzed using the OCTC method.     

A Fully Integrated 0.13- $mu$m CMOS 40-Gb/s Serial Link Transceiver

A fully integrated 40-Gb/s transceiver fabricated in a 0.13-$mu$m CMOS technology is presented. The receiver operates at a 20-GHz clock performing half-rate clock and data recovery. Despite the low ${rm f}_{rm T}$ of 70 GHz, the input sampler achieves 10-mV sensitivity using pulsed latches and inductive-peaking techniques. In order to minimize the feedback latency in the bang-bang controlled CDR loop, the proportional control is directly applied to the VCO, bypassing the charge pump and the loop filter. In addition, the phase detection logic operates at 20 GHz, eliminating the need for the deserializers for the early/late timing signals. The four clock phases for the half-rate CDR are generated by a quadrature LC-VCO with microstrip resonators. A linear equalizer that tunes the resistive loading of an inductively-peaked CML buffer can improve the eye opening by 20% while operating at 39 Gb/s. The prototype transceiver occupies 3.4$, times ,$2.9 mm$^{2}$ with power dissipation of 3.6 W from a 1.45-V supply. With the equalizer on, the transmit jitter of the 39-Gb/s 2$^{15}-1$ PRBS data is 1.85 ${rm ps}_{rm rms}$ over a WB-PBGA package, an 8-mm PCB trace, an on-board 2.4-mm connector, and a 1 m-long 2.4-mm coaxial cable. The recovered divided-by-16 clock jitter is 1.77 ${rm ps}_{rm rms}$ and the measured BER of the transceiver is less than $10^{- 14}$ .      

4$,times,$25-Gb/s 40-km PHY at 1310 nm for 100 GbE Using SOA-Based Preamplifier

We present extensive numerical simulations of an optical link deploying four electroabsorption modulated lasers (EMLs) at 25 Gb/s over up to 40 km of standard single-mode fiber. The receiver comprises a semiconductor optical amplifier (SOA) as a preamplifier. We analyze the bit error ratio (BER) along different link lengths under varying conditions such as output power and extinction ratio of the EML transmitters, the noise figure of the SOA preamplifier and the bit and word alignment of the four wavelength channels. We demonstrate that the EML transmitters require a minimum extinction ratio of 8 to 10 dB and a minimum output power of +2 to +4 dBm in order to meet the BER requirements for 100 Gigabit Ethernet (100 GbE) using 4 times 25-Gb/s physical media dependent (PMD) devices. Furthermore, we show that single-channel performance analyses can be used to estimate the behavior for multichannel amplification in the SOA preamplifier.     

An 11 mm$^{2}$ , 70 mW Fully Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12$ mu$ m CMOS

With the rapid evolution of wireless standards and increasing demand for multi-standard products, the need for flexible RF and baseband solutions is growing. Flexibility is required to be able to adapt to unstable standards and requirements without costly hardware re-spins, and also to enable hardware reuse between products and between multiple wireless standards in the same device, ultimately saving both development cost and silicon area. In this paper a fully programmable baseband processor suitable for standards such as DVB-T/H and mobile WiMAX is presented. The processor is based on the SIMT architecture which utilizes a unique type of vector instructions to provide processing parallelism while minimizing the control complexity of the processor. The architecture has been demonstrated in a prototype chip which was proven in a complete DVB-T/H system demonstrator. The chip occupies 11 mm² in a 0.12 mum CMOS process. It includes 1.5 Mbit of single port SRAM and 200 k logic gates. The measured power consumption for the highest DVB-T/H data rate (31.67 MBit/s) is 70 mW at 70 MHz. This outperforms both area and power figures of previously presented non-programmable DVB-T/H solutions.     

4$,times,$25 Gb/s Frequency-Modulated DBR Laser Array for 100-GbE 40-km Reach Application

A monolithically integrated 100-Gb/s throughput (4 $,times,$25 Gb/s) laser array has been developed that employs frequency-modulated distributed Bragg reflector lasers. An optical filter converts a frequency-modulated signal to an amplitude-modulated signal with a high contrast ratio in addition to reducing the lasing spectrum bandwidth. A clear eye opening after 40-km transmission was observed with a 25-Gb/s nonreturn-to-zero signal in the 1550-nm region.      

An All-Digital RF Signal Generator Using High-Speed $DeltaSigma$ Modulators

An all-digital RF signal generator using DeltaSigma modulation and targeted at transmitters for mobile communication terminals has been implemented in 90 nm CMOS. Techniques such as redundant logic and non-exact quantization allow operation at up to 4 GHz sample rate, providing a 50 MHz bandwidth at a 1 GHz center frequency. The peak output power into a 100 Omega diff. load is 3.1 dBm with 53.6 dB SNDR. By adjusting the sample rate, carriers from 50 MHz to 1 GHz can be synthesized. RF signals up to 3 GHz can be synthesized when using the first image band. As an example, UMTS standard can be addressed by using a 2.6 GHz clock frequency. The measured ACPR is then 44 dB for a 5 MHz WCDMA channel at 1.95 GHz with output power of -16 dBm and 3.4% EVM. At 4 GHz clock frequency the total power consumption is 120 mW (49 mW for DeltaSigma modulator core) on a 1 V supply voltage, total die area is 3.2 mm² (0.15 mm² for the active area).     

A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18-$mu$m CMOS Technology

A 10-Gb/s current mode logic (CML) input/output (I/O) circuit for backplane interconnect is fabricated in 0.18-mu m 1P6M CMOS process. Comparing with conventional I/O circuit, this work consists of input equalizer, limiting amplifier with active-load inductive peaking, duty cycle correction and CML output buffer. To enhance circuit bandwidth for 10-GB/s operation, several techniques include active load inductive peaking and active feedback with current buffer in Cherry-Hooper topology. With these techniques, it reduces 30%-65% of the chip area comparing with on-chip inductor peaking method. This design also passes the interoperability test with switch fabric successfully. It provides 600- mV_pp differential voltage swing in driving 50-Omega output loads, 40-dB input dynamic range, 40-dB voltage gain, and 8-mV input sensitivity. The total power consumption is only 85 mW in 1.8-V supply and the chip feature die size is 700 mum times 400 mum.     

A Tunable Pseudo-Differential OTA With $-78~{hbox {dB}}$ THD Consuming 1.25 mW

A novel linear tunable transconductor based on a combination of linearization techniques is presented. The input signal is transferred to the V-I conversion element by means of a high-speed feedback loop. Then, the linear V-I conversion is accomplished using quasi-floating-gate MOS transistors biased in the triode region. Finally, the absence of current mirrors in the signal path provides low sensitivity to transistor mismatch and reduces the harmonic distortion. The operational transconductance amplifier (OTA) was fabricated in a 0.5-mum CMOS technology with a single 3.3-V supply voltage. Experimental results show a total harmonic distortion of -78 dB at 1 MHz with 1-V_pp input signal. High linearity of the OTA is obtained over a two octave tuning range with only 1.25-mW power consumption.     

Optimal Dual-$V_{T}$ Design in Sub-100-nm PD/SOI and Double-Gate Technologies

Dual-threshold-voltage (V_T) CMOS is an effective way to reduce leakage power in high-performance very-large-scale-integration circuits. In this paper, we explore the technology design space for dual-threshold-voltage transistor design in deep-sub-100-nm technology nodes. We propose a technique of achieving high-V_T (HVT) devices using thicker gate-sidewall offset spacers to increase the channel length without increasing the printed-gate length. The effectiveness of all the dual-V_T technology options-increasing channel doping, increasing gate length, and proposed technique of increasing spacer thickness-is analyzed at transistor and basic logic gate level. Results on 65-nm partially depleted silicon-on-insulator and double-gate technologies indicate that the proposed technique yields lower dynamic power consumption and lower performance penalty compared with longer gate length and high body-doping devices. Our proposed technique, however, incurs extra fabrication mask similar to achieving HVT by increasing body doping.     

A Differential Clapp-VCO in 0.13 $mu{rm m}$ CMOS Technology

A new differential voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 $mu{rm m}$ CMOS 1P8M process. The designed circuit topology is an all nMOS LC-tank Clapp-VCO using a series-tuned resonator. At the supply voltage of 0.9 V, the output phase noise of the VCO is $-$110.5 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 18.78 GHz, and the figure of merit is $-$188.67 dBc/Hz. The core power consumption is 5.4 mW. Tuning range is about 3.43 GHz, from 18.79 to 22.22 GHz, while the control voltage was tuned from 0 to 1.3 V.      

A 20 to 24 GHz $+$16.8 dBm Fully Integrated Power Amplifier Using 0.18 $mu{rm m}$ CMOS Process

A 20-24 GHz, fully integrated power amplifier (PA) with on-chip input and output matching is realized in 0.18 mum standard CMOS process. By cascading two cascode stages, the PA achieves 15 dB small signal gain, 10.7% power added efficiency, 16.8 dBm output saturation power and high power density per chip area of 0.137 W/mm², which is believed to be the highest power density to our knowledge. The whole chip area with pads is 0.35 mm², which is the smallest one compared to all reported paper.     

A 0.1 mm$^{2}$ , Wide Bandwidth Continuous-Time $SigmaDelta$ ADC Based on a Time Encoding Quantizer in 0.13 $mu$ m CMOS

The ADC shown in this paper uses an innovative sigma-delta (SigmaDelta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-SigmaDelta ADC prototype has been fabricated in 0.13 mum CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = Pwr/2 middot BW middot 2^ENOB) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm².     

10Gb/s CMOS时钟和数据恢复电路的设计

介绍了利用0.18μmCMOS工艺实现了应用于光纤传输系统SDHSTM-64级别的时钟和数据恢复电路。采用了电荷泵锁相环(CPPLL)结构,CPPLL中的鉴相器能够鉴测相位产生超前滞后逻辑,采样数据具有1∶2分接的功能。振荡器采用全集成LC压控振荡器,鉴相器采用半速率的结构。对应于10Gb/s的PRBS数据(231-1),恢复出的5GHz时钟的相位噪声为-112dBc/Hz@1MHz,同时10Gb/s的PRBS数据分接出两路5Gb/s数据。芯片面积仅为1.00mm×0.8mm,电源电压1.8V时功耗为158mW。     

Optical Interconnection Platform Composed of Fiber-Embedded Board, 90$^{circ}$-Bent Fiber Block, and 10-Gb/s Optical Module

An architecture of a passively assembled optical platform is suggested for a chip-to-chip optical interconnection system. The platform is constructed using all-fiber media for the optical paths: a fiber-embedded optical printed-circuit board (OPCB) and 90-bent fiber connector. The passive assembling was achieved by employing the guide pins/holes of commercialized ferrules in the optical link between the OPCB, 90-bent fiber connector, and the transmitter/receiver (Tx/Rx) module. From this interconnection scheme, a low total optical loss of was obtained. From an assembled platform with 10 Gb/s/ch 4 ch Tx/Rx modules, a 7-Gb/s/ch data transmission was demonstrated with a bit error rate below , involving the optical and electrical crosstalk arisen in the whole channel operation.     

Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS

This paper presents low-voltage circuit topologies for 40-Gb/s communications in 90-nm and 65-nm CMOS. A retiming flip-flop implemented in two different 90-nm CMOS technologies employs a MOS-CML Master-Slave latch topology with only two vertically stacked transistors. Operation at 40 Gb/s is achieved by a combination of low and high-V_T MOSFETs in the latch. Full-rate retiming with jitter reduction is demonstrated up to 40 Gb/s. Low-power broadband amplifiers based on resistor-inductor transimpedance feedback are realized in 90-nm and 65-nm CMOS to investigate the portability of high-speed building blocks between technology nodes. Experiments show that the transimpedance amplifier based on the CMOS inverter can reach 40-Gb/s operation with a record power consumption of 0.15 mW/Gb/s. A comparison between CMOS technologies underlines the importance of General Purpose rather than Low Power processes for high-speed digital design.     

A 3.3-V 21-Gb/s PRBS generator in AlGaAs/GaAs HBT technology

We present a pseudorandom bit sequence (PRBS) generator that outputs a 2⁷-1 bit pattern at rates up to 21 Gb/s. The circuit is implemented in a 40-GHz AlGaAs/GaAs heterojunction bipolar transistor (HBT) standard production process, operates from a single 3.3-V power supply, and consumes 1.1 W of power. We discuss variations of PRBS architecture and digital circuit topologies which exploit unique characteristics of AlGaAs/GaAs HBT devices. The work demonstrates the feasibility of using AlGaAs/GaAs HBT technology with low-voltage/low-power design techniques in complex high-speed circuits     

A 200-$mu$V/e$^{-}$ CMOS Image Sensor With 100-ke$^{-}$ Full Well Capacity

A high-sensitivity CMOS image sensor keeping a high full-well capacity has been developed by introducing a new pixel having a small floating diffusion (FD) capacitance connected to a lateral overflow integration capacitor (LOFIC) through a MOS switch. The conceptual advantage of the small FD approach over conventional column amplifier approaches is compared and demonstrated. To ensure both the high sensitivity and the high full-well capacity, the low-light and the bright-light signals (S1 and S2) are output and reproduced without a visible SNR degradation at the S1/S2 switching point. As the most critical problem, the increase of the conversion gain variation in this approach is suppressed by applying a self-aligned offset structure to the small FD. A 1/4-in VGA format CMOS image sensor fabricated through 0.18-mum 2P3M process achieves 2.2-e^- rms noise floor with 200-muV/e^- conversion gain and 100-ke^- full-well capacity.     

22.7-dB Gain $-$19.7-dBm $ICP_{1{rm dB}}$ UWB CMOS LNA

A fully differential CMOS ultrawideband low-noise amplifier (LNA) is presented. The LNA has been realized in a standard 90-nm CMOS technology and consists of a common-gate stage and two subsequent common-source stages. The common-gate input stage realizes a wideband input impedance matching to the source impedance of the receiver (i.e., the antenna), whereas the two subsequent common-source stages provide a wideband gain by exploiting RLC tanks. The measurements have exhibited a transducer gain of 22.7 dB at 5.2 GHz, a 4.9-GHz-wide B _3dB, an input reflection coefficient lower than -10.5 dB, and an input-referred 1-dB compression point of -19.7 dBm, which are in excellent agreement with the postlayout simulation results, confirming the approach validity and the design robustness.     

A 40-MHz Double Differential-Pair CMOS OTA With $-{hbox{60-dB}}$ IM3

A configuration of a linearized operational transconductance amplifier (OTA) for low-voltage and high-frequency applications is proposed. By using double pseudodifferential pairs and the source-degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from a small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability and thus reduces distortion caused b y common-mode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about -60-dB third-order inter-modulation (IM3) distortion for up to 0.9 V_pp at 40 MHz. This OTA was fabricated by the TSMC 180-nm deep n-well CMOS process. It occupies a small area of 15.1times10^-3 mm² and the power consumption is 9.5 mW under a 1.5-V supply voltage.     

A Large Swing, 40-Gb/s SiGe BiCMOS Driver With Adjustable Pre-Emphasis for Data Transmission Over 75 $Omega$ Coaxial Cable

A fully differential 40-Gb/s cable driver with adjustable pre-emphasis is presented. The circuit is fabricated in a production 0.18 mum SiGe BiCMOS technology. A distributed limiting architecture is used for the driver employing high-speed HBTs in the lower voltage predriver, and a high-breakdown MOS-HV-HBT cascode, consisting of a 0.18 mum n-channel MOSFET and a high-voltage HBT (HV-HBT), for the high voltage output stages. The circuit delivers up to 3.6 V peak-to-peak per side into a 75 Omega load with variable pre-emphasis ranging from 0 to 400%. S-parameter measurements show 42 dB differential small-signal gain, a 3-dB bandwidth of 22 GHz, gain peaking control up to 25 dB at 20 GHz and input and output reflection coefficients better than -10 dB up to 40 GHz. Additional features of the driver include output amplitude control (from 1 V_pp to 3.6 V_pp per side), pulse-width control (35% to 65%) and an adjustable input dc level (1.1 V to 1.8 V) allowing the circuit to interface with a SiGe BiCMOS or MOS-CML SERDES. The transmitter is able to generate an eye opening at 38 Gb/s after 10 m of Belden 1694 A coaxial cable which introduces 22 dB of loss at 19 GHz. Measurement results also demonstrate that the transmitter IC operates as a standalone equalizer for 10-Gb/s data transmission over 40 m of Belden cable without the need for receiver equalization.