Decoupling of cold-carrier effects in hot-carrier reliability assessment of HfO/sub 2/ gated nMOSFETs

To understand the intrinsic effect of a hot-carrier injection on high-/spl kappa/ dielectrics free from concurrent cold-carrier trapping, the authors have investigated a hot-carrier-induced damage with channel hot-carrier stresses and substrate hot-carrier stress. Compared to substrate hot-carrier stress, the channel hot-carrier stress shows a more significant cold-carrier-injection effect. By using a detrapping bias, they were able to decouple the effect of cold-carrier trapping from the permanent trap generation induced by the hot-carrier injection. As channel hot-carrier stress bias was reduced, a portion of cold-carrier trapping increased and a portion of interface trap generation decreased.     

Reliability characteristics of high-k dielectrics

In this paper, recent results of Weibull slopes, area scaling factors, and breakdown behaviors observed for both soft breakdown and hard breakdown are discussed. These results would help to shed light on the breakdown mechanism of HfO₂ gate dielectrics. The Weibull slope β of the hard breakdown for both the area dependence and the time-to-dielectric-breakdown distribution was found to be β=2, whereas that of the soft breakdown was about 1.4 (EOT=14 Å). We also integrated the time-to-breakdown characteristics of HfO₂ under unipolar AC voltage stress on MOS capacitors. The results show that longer lifetime of HfO₂ has been observed when compared to constant voltage stress. Higher frequency and lower duty cycle in the AC stress resulted in longer lifetime. As thickness decreases, the amount of lifetime enhancement decreases. The enhancement of unipolar t_BD is attributed to less charge trapping during the “on time”, t_on and charge detrapping during the off time, t_off. It is proposed that time (τ_in) for charge to be trapped in HfO₂ is longer than t_on of unipolar stress under high frequency. In addition to experimental results, possible solutions are discussed.     

New insights into the relation between channel hot carrier degradation and oxide breakdown short channel nMOSFETs

In this letter, we report new findings in the relation between channel hot-carrier (CHC) degradation and gate-oxide breakdown (BD) in short-channel nMOSFETS biased at V/sub G/>V/sub D/. We observe that the time-to-BD is strongly reduced in the hot carrier regime and that although the channel hot-electron injection into the oxide occurs mainly at the drain side, stress-induced leakage current (SILC) generation and oxide BD always occur at the source side. The results of these measurements indicate that not solely the energy of the injected electrons but also the oxide electric field is determinant in the oxide BD process.     

Behaviour of injected electrons in high-k dielectric layers

The programming operation in memory device consists of an injection of electrons into the gate dielectric (GD). In many cases, oxide–nitride–oxide (ONO) is used as a GD. A stability of the spatial profile of injected electrons (IE) determines the quality of the memory device. Computer simulations showed that injection of electrons into GD leads to the formation of small charge droplets out of the initial spatial profile of IE. Such a droplet is named as parasitic peak (PP). The simulation of IE redistribution in GD shows that the Coulomb scattering of newly injected carriers on PPs plays an important role in the evolution of the device parameters in conditions of long-term exploitation. The computer model of ONO with high-k layers (HKL) is developed to study the retention parameters of the device in dependence on the type of HKL and on the thickness of GD. The influence of scaling down of the dielectric film with HKL on IE redistribution in GD is investigated. Simulations showed that the possibility of scaling down the thickness of ONO stack with HKL depends not only on the tunnelling effects but also on the multiple scattering processes in ONO with HKL.     

一种具有高K栅介质与低k侧壁介质的PNPN型隧穿晶体管研究

本文提出了一种具有高K栅介质及低K侧壁介质的PNPN型隧穿场效应晶体管,并通过二维仿真研究了栅电场和侧壁电场对隧穿场效应晶体管性能的影响。结果表明高K栅介质可以增强栅对沟道的控制能力,同时低K侧墙介质有助于增大带带隧穿的几率。具有这种结构的隧穿场效应晶体管器件具有很好的开关特性、大的开态电流以及良好的工艺容差。该器件可以应用于低功耗领域,并有可能作为下一代CMOS技术的替代者之一。     

Density functional theory of high-k dielectric gate stacks

Density functional theory is the method of choice in theoretical materials science. It has also proved to be a useful tool in device engineering, particularly at nanoscale and when novel materials are involved. In this paper, we briefly review recent theoretical results in the area of the advanced gate stack materials engineering.     

Bond strain and defects at interfaces in high-k gate stacks

The performance and reliability of aggressively-scaled field effect transistors are determined in large part by electronically-active defects and defect precursors at the Si–SiO₂, and internal SiO₂–high-k dielectric interfaces. A crucial aspect of reducing interfacial defects and defect precursors is associated with bond strain-driven bonding interfacial self-organizations that take place during high temperature annealing in inert ambients. The interfacial self-organizations, and intrinsic interface defects are addressed through an extension of bond constraint theory from bulk glasses to interfaces between non-crystalline SiO₂, and (i) crystalline Si, and (ii) non-crystalline and crystalline alternative gate dielectric materials.     

Short channel effect in deep submicron PDSOI nMOSFETs

Deep submicron partially depleted silicon on insulator (PDSOI) nMOSFETs were fabricated based on the 0.35μm SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences (IMECAS). Mechanisms determining short-channel effects (SCE) in PDSOI nMOSFETs are clarified based on experimental results of threshold voltage dependence upon gate length. The effects of body bias, drain bias, temperature and body contact on the SCE have been investigated. The SCE in SOl devices is found to be dependent on body bias, drain bias and body contact. Floating body devices show a more severe reverse short channel effect (RSCE) than devices with body contact structure. Devices with low body bias and high drain bias show a more obvious SCE.     

Praseodymium based high-k dielectrics grown on Si and SiC substrates

High-k polycrystalline Pr₂O₃ thin films have been deposited by metal organic chemical vapor deposition (MOCVD) technique on Si(0 0 1) and 4H–SiC(0 0 0 1) substrates. MOCVD processes have been carried out from the Pr(tmhd)₃ (H-tmhd= 2,2,6,6-tetramethyl-3,5-heptandione) precursor. Complete structural and morphological characterization of films has been carried out using several techniques (X-ray diffraction (XRD), scanning electron microscopy (SEM), transmission electron microscopy (TEM)). Polycrystalline Pr₂O₃ films have been obtained and at the interface a praseodymium silicate amorphous layer has been observed on both substrates. The electrical properties of the dielectric praseodymium films have been evaluated.     

Reverse avalanche breakdown in gated diodes

A two dimensional study of reverse avalanche breakdown in high voltage gated diodes is presented. The numerical method uses the finite difference solution of Poisson's equation with appropriate boundary conditions. A modified two dimensional depletion region approximation is used to take into account the effects of accumulation and inversion near the insulator-semiconductor interface. It has been found that although the effects of surface states and accumulation on the breakdown is small, inversion changes the breakdown characteristics substantially. Breakdown voltage versus gate voltage curves are given for various geometries and doping properties. Good agreement has been achieved between the computed and experimental values of breakdown voltages for a large range of gate potentials.     

Hot carriers' effects in short channel devices

Experimental evidence for the impact of hot holes injection under pulsed voltage stress on the device degradation are presented. The transconductance lowering was supposed to be caused by an increase of the interface states density near the drain region. A field effect mobility decrease and an increase of the surface scattering factor by an amount larger for the shorter channel lengths were observed.     

ZrAlO ternary oxide as a candidate for high-k dielectrics

ZrAlO thin films were prepared by the pyrosol process. Four different cases were considered taking as basis a solution of 0.025 M zirconium acetylacetonate (ZrAAc) and 5 at% of aluminum acetylacetonate (AlAAc) dissolved in pure methanol. Films of case A, were deposited with the mentioned solution and subjected to rapid thermal annealing (RTA). For case B, a small volume of water was added to start solution. Case C, were similar samples of case B, but with a post-deposition RTA. Case D, were Si/Al₂O₃/ZrAlO/Al stacks with post-deposition RTA, using water in the start solution. XPS profiles show that the relative chemical composition of deposited materials is affected by the volume of water added (Vw). The aluminum concentration in the films acquires values as high as or higher than zirconium concentration for increasing Vw. All the prepared samples were amorphous as indicated by the X-ray diffraction (XRD) spectra, even for large integration times. Current–voltage (I–V) and capacitance measurements were carried out in metal–insulator–metal (MIM) devices (Corning-glass/TCO/ZrAlO/Al) and I–V and simultaneous capacitance–voltage (C–V) measurements were performed in metal–oxide–semiconductor (MOS) devices (Si/ZrAlO/Al and Si/Al₂O₃/ZrAlO/Al). Leakage currents of the order of 10⁻⁴ A/cm², were typically obtained in MIM devices, whereas for some MOS devices, leakage currents of the order of 10⁻⁷ A/cm² were obtained. Dielectric constant (k) values of the order of 24 were calculated for MIM devices and k values ranging from 12.5 up to 17 were calculated for MOS devices.     

深亚微米PDSOI nMOSFETs的短沟道效应

基于中国科学院微电子所开发的0.35µmSOI工艺制备了深亚微米PDSOI nMOSFET。根据阈值电压依赖沟道长度的测试结果阐述了决定PDSOI nMOSFET 短沟道效应的机理。研究了体偏置、漏偏置以及温度和体接触对PDSOI nMOSFET 短沟道效应的影响,发现短沟道效应依赖于体偏置、漏偏置以及体接触。浮体器件比有体接触结构的器件的反短沟道效应更严重,器件在低体偏和高漏偏下会表现出更明显的短沟道效应。     

Reduced reverse narrow channel effect in thin SOI nMOSFETs

The effects of narrow channel width on the threshold voltage of deep submicron silicon-on-insulator (SOI) nMOSFETs with LOCOS isolation have been investigated. The reverse narrow channel effect (RNCE) in SOI devices is found to be dependent on the thickness of the active silicon film. A thinner silicon film is found to depict less threshold voltage fall-off. These results can be explained by a reduced oxide/silicon interface area in the transistor width direction, thus the boron segregation due to silicon interstitials with high recombination rate is reduced     

Structural and interfacial properties of high-k HfOxNy gate dielectric films

The thermal stability and interfacial characteristics for hafnium oxynitride (HfO_xN_y) gate dielectrics formed on Si (1 0 0) by plasma oxidation of sputtered HfN films have been investigated. X-ray diffraction results show that the crystallization temperature of nitrogen-incorporated HfO₂ films increases compared to HfO₂ films. Analyses by X-ray photoelectron spectroscopy confirm the nitrogen incorporation in the as-deposited sample and nitrogen substitution by oxygen in the annealed species. Results of FTIR characterization indicate that the growth of the interfacial SiO₂ layer is suppressed in HfO_xN_y films compared to HfO₂ films annealed in N₂ ambient. The growth mechanism of the interfacial layer is discussed in detail.     

NBTI reliability on high-k metal-gate SiGe transistor and circuit performances

Negative-bias temperature instability (NBTI) on high-k metal-gate SiGe p-channel MOSFETs has been examined. SiGe p-MOSFETs shows reduced interface states and enhanced NBTI reliability compared to their Si p-channel control devices as evidenced by experimental data. Impact of NBTI reliability on digital and RF circuits has been also examined using extracted fresh and stressed BSIM4 model parameters in circuit simulation. High-k metal-gate SiGe pMOSFETs demonstrate less inverter pull-up delay, smaller noise figure of a cascode low-noise amplifier, and larger output power and power-added efficiency than their Si counterparts when subject to NBTI stress.     

Reliability screening of high-k dielectrics based on voltage ramp stress

High-k development moves towards integration into CMOS processes rising attention for the reliability assessment. In this paper, the methodology for reliability screening is discussed based on constant voltage stress and voltage ramp stress. It will be shown that both procedures yield equivalent results and the determined reliability parameters are compatible. Better control of the overall measurement time favours the voltage ramp stress as preferred fast screening method for integration of high-k dielectrics.     

高介电常数栅介质/二氧化硅界面偶极子成因研究

The formation of an electric dipole at the high-k/SiO2 interface is quantitatively analyzed. The band lineups and physical origin of dipole formation at the high-k/SiO2 interface are explained by the dielectric contact induced gap states(DCIGS). The charge neutrality level(CNL) of the DCIGS, which represents a distribution of high-k and SiO2 contact induced gap states, is utilized to study the dipole moment. The charge transfer due to different CNLs of high-k and SiO2 is considered as the dominant origin of dipole formation. The theoretically calculated dipole strengths of high-k/SiO2 systems based on this model are in good agreement with the experimental data.     

A fringing-capacitance model for deep-submicron MOSFET with high-k gate dielectric

An analytical model of fringing capacitances for deep-submicron MOSFET with high-k gate dielectric, including gate dielectric fringing-capacitance and gate electrode fringing-capacitance, is obtained by the conformal-mapping transformation method. It is demonstrated that the fringing-capacitance effect is enhanced as the thickness of gate electrode or the dielectric constant of either gate dielectric or sidewall spacer increases. Moreover, the influence of fringing-capacitance on threshold voltage is demonstrated.     

Design of field-plate terminated 4H-SiC Schottky diodes using high-k dielectrics

Silicon carbide (SiC) field-plate terminated Schottky diodes using silicon dioxide (SiO₂) dielectric experience high electric field in the insulator and premature dielectric breakdown, attributed to the lower dielectric constant of the oxide. To alleviate this problem we explore the use of high-k dielectrics, silicon nitride (Si₃N₄) and sapphire (Al₂O₃), on 4H-SiC by numerical simulations using Medici. The simulation results show significant improvement in blocking voltages by as much as 30% and much lower electric field within the dielectrics. There is also a slight reduction in the specific-on resistance (R_sp-on) and a small increase in the forward current density due to the formation of an accumulation layer in SiC where the metal overlaps the dielectric. This effect is enhanced with increasing dielectric constant and decreasing dielectric thickness for a given dielectric.