Strained ultrahigh performance fully depleted nMOSFETs with f/sub t/ of 330 GHz and sub-30-nm gate lengths

Ultrahigh performance fully depleted nMOSFETs have been fabricated on ultra-thin silicon-on-insulator (UTSOI) with a body thickness of 18 nm and channel lengths down to 20 nm. Uniaxial tensile stress induced in the channel using stressed contact liners and stress memorization was found to significantly improve ac performance, resulting in cutoff frequencies f/sub t/ as high as 330 GHz. This is the highest f/sub T/ value reported on fully depleted UTSOI MOSFETs and is among the highest f/sub T/ values for any Si-based field-effect transistor. Stress memorization and stressed contact liners were found to have little impact on gate to source capacitance indicating that the enhancement in f/sub T/ results primarily from stress-induced enhancements in transconductance.     

Nanoscale FinFETs with gate-source/drain underlap

Using two-dimensional numerical device simulations, we show that optimally designed nanoscale FinFETs with undoped bodies require gate-source/drain (G-S/D) underlap that can be effectively achieved via large, doable straggle in the S-D fin-extension doping profile without causing S-D punch-through. The effective underlap significantly relaxes the fin-thickness requirement for control of short-channel effects (SCEs) via a bias-dependent effective channel length (L/sub eff/), which is long in weak inversion and approaches the gate length in strong inversion. Dependence of L/sub eff/ on the S/D doping profile defines a design tradeoff regarding SCEs and S/D series resistance that can be optimized, depending on the fin width, via engineering of the doping profile in the S/D fin-extensions. The noted optimization is exemplified via a well-tempered FinFET design with an 18-nm gate length, showing further that designs with effective underlap yield minimal parasitic capacitance and reduce leakage components such as gate-induced drain leakage current.     

A new extraction algorithm for the metallurgical channel length ofconventional and LDD MOSFETs

A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFETs is presented, which is based on the well-known resistance method with a special technique to eliminate the uncertainty of the channel length and to reduce the influence of the parasitic source/drain resistance on threshold-voltage determination. In particular, the metallurgical channel length is determined from a wide range of gate-voltage-dependent effective channel lengths at an adequate gate overdrive. The 2-D numerical analysis clearly show that adequate gate overdrive is strongly dependent on the dopant concentration in the source/drain region. Therefore, an analytic equation is derived to determine the adequate gate overdrive for various source/drain and channel doping. It shows that higher and lower gate overdrives are needed to accurately determine the metallurgical channel length of conventional and LDD MOSFET devices, respectively. It is the first time that we can give a correct gate overdrive to extract L_met not only for conventional devices but also for LDD MOS devices. Besides, the parasitic source/drain resistance can also be extracted using our new extraction algorithm     

A CMOS-compatible rapid vapor-phase doping process for CMOS scaling

An advanced CMOS process, which used rapid vapor-phase doping (RVD) for pMOSFETs and solid-phase diffusion (SPD) for nMOSFETs, has been developed. Using the RVD technique, a 40-nm-deep p-type extension with a sheet resistance as low as 400 /spl Omega//sq has been realized. These RVD and SPD devices demonstrate excellent short-channel characteristics down to 0.1 /spl mu/m channel length and 40% higher drain current, compared with conventional devices with ion implanted source/drain (S/D) extensions, and high-speed circuit performance. We investigate the effect of the S/D extension structure on the device performance and find that a gate extension overlap of 25 nm enables excellent dc and high-speed circuit performance in 0.1-/spl mu/m devices.     

Tuning effective metal gate work function by a novel gate dielectric HfLaO for nMOSFETs

Using a novel HfLaO gate dielectric for nMOSFETs with different La composition, we report for the first time that TaN (or HfN) effective metal gate work function can be tuned from Si mid-gap to the conduction band to fit the requirement of nMOSFETs. This is explained by the change of interface states and Fermi pinning level by adding La into HfO/sub 2/. The superior performances of the nMOSFETs compared with those using pure HfO/sub 2/ gate dielectric are also reported, in terms of higher crystallization temperature and higher drive current I/sub d/ without sacrifice of very low gate leakage current, i.e. 5-6 orders reduction compared with SiO/sub 2/ at the same equivalent oxide thickness of /spl sim/1.2-1.8 nm.     

Highly reliable CVD-WSi metal gate electrode for nMOSFETs

In this paper, we first propose an improved chemical vapor deposition (CVD) WSi/sub x/ metal gate suitable for use in nMOSFETs. We studied the relationship between the Si/W ratio of CVD-WSi/sub x/ film and electrical properties of MOSFETs. As a result, it was found that the Si/W ratio strongly affects carrier mobility and the reliability of gate oxide. In the case of higher Si/W ratio, both electron and hole mobility can be improved. For CVD-WSi/sub 3.9/ electrode, electron mobility and hole mobility at 1.2 V of |V/sub g/-V/sub th/| are 331 and 78 cm/sup 2//V/spl middot/s, respectively. These values are almost the same as those for n/sup +/-poly-Si electrode. The improvement of carrier mobility by controlling the Si/W ratio is due to suppression of fluorine contamination in gate oxide. F contamination at the Si/W ratio of 3.9 is found to be less than that at the Si/W ratio of 2.4 from XPS analysis. Workfunction of CVD-WSi/sub 3.9/ gate estimated from C-V measurements is 4.3 eV. In CVD-WSi/sub 3.9/ gate MOSFETs with gate length of 50 nm, a drive current of 636 /spl mu/A//spl mu/m was achieved for off-state leakage current of 35 nA//spl mu/m at power supply voltage of 1.0 V. By using CVD-WSi/sub 3.9/ gate electrode, highly reliable metal gate nMOSFETs can be realized.     

Electron Mobility and Short-Channel Device Characteristics of SOI FinFETs With Uniaxially Strained (110) Channels

We have successfully fabricated uniaxially strained SOI (SSOI) FinFETs with high electron mobility and low parasitic resistance. The high electron mobility enhancement on the (110) fin sidewall surfaces was obtained by utilizing effective subband engineering through uniaxial tensile strain along $ langlehbox{110}rangle$, while the substantial reduction of the parasitic resistance was achieved by selective Si epitaxy on the source and drain regions. It was experimentally found that the electron mobility on the (110) sidewall surfaces was significantly enhanced (2.6$times$ ) and even surpassed the (100) universal mobility (1.2$times$ ). This high mobility enhancement is mainly attributed to the electron repopulation from fourfold valleys having a heavier mass along $langlehbox{110}rangle$ to twofold valleys having a lighter one. In addition, the effective mass reduction of the twofold valleys due to conduction band warping and/or the suppressed surface roughness scattering can also be responsible for the mobility enhancement. Thanks to these high electron mobility enhancement and low parasitic resistance large performance enhancement of 35% was realized in uniaxially SSOI FinFETs with a gate length of 50 nm. This enhancement was evaluated to be as high as $sim$80% $(= hbox{35}%/hbox{45}%)$ of the intrinsic strain-induced enhancement of the short-channel device performance (45%) at the same strain level (0.8%, $sim$1.5 GPa) and gate length.      

Design optimization of AlInAs-GalnAs HEMTs for low-noise applications

In order to optimize the low-noise performance of 50-nm-gate AlInAs-GalnAs high-electron mobility transistors (HEMTs), by using an ensemble Monte Carlo simulation we study the influence of three important technological parameters on their noise level: the doping of the /spl delta/-doped layer, the width of the devices and the length of the recess. The noise behavior of the devices is firstly analyzed in terms of the physics-based P, R, and C parameters, and then characterized from a practical (circuit oriented) point of view through their four noise parameters: minimum noise figure, F/sub min/, noise resistance, R/sub n/, and complex input admittance, Y/sub opt/ (or reflection coefficient, /spl Gamma//sub opt/). We have observed an enhancement of the noise when the /spl delta/-doping or the device width are increased (a deterioration parallel to that of f/sub max/). Thus, the optimum noise operation is obtained for the lowest possible values of the /spl delta/-doping and device width. However, for small width the effect of the offset parasitic capacitances makes F/sub min/ increase, thus, imposing a limit for the reduction of the noise. Moreover, the increase of R/sub n/ for small W makes the noise tuning condition critical to reach the optimum low-noise operation. We have also confirmed that when shortening the recess length from 100 to 20 nm at each side of the gate F/sub min/ is reduced, with a slight deterioration of f/sub max/, while the static characteristics are not modified.     

Correlating drain-current with strain-induced mobility in nanoscale strained CMOSFETs

The correlation between channel mobility gain (/spl Delta//spl mu/), linear drain-current gain (/spl Delta/I/sub dlin/), and saturation drain-current gain (/spl Delta/Idsat) of nanoscale strained CMOSFETs are reported. From the plots of /spl Delta/I/sub dlin/ versus /spl Delta/I/sub dsat/ and ballistic efficiency (Bsat,PSS), the ratio of source/drain parasitic resistance (R/sub SD,PSS/) to channel resistance (R/sub CH,PSS/) of strained CMOSFETs can be extracted. By plotting /spl Delta//spl mu/ versus /spl Delta/I/sub dlin/, the efficiency of /spl Delta//spl mu/ translated to /spl Delta/I/sub dlin/ is higher for strained pMOSFETs than strained nMOSFETs due to smaller RSD,PSS-to-RCH,PSS ratio of strained pMOSFETs. It suggests that to exploit strain benefits fully, the RSD,PSS reduction for strained nMOSFETs is vital, while for strained pMOSFETs the /spl Delta/I/sub dlin/-to-/spl Delta//spl mu/ sensitivity is maintained until R/sub SD,PSS/ becomes comparable to/or higher than R/sub CH,PSS/.     

Mobility enhancement in surface channel SiGe PMOSFETs with HfO/sub 2/ gate dielectrics

We report for the first time drive current enhancement and higher mobilities than the universal mobility for SiO/sub 2/ on Si in compressively strained Si/sub 1-x/Ge/sub x/-on-Si surface channel PMOSFETs with HfO/sub 2/ gate dielectrics, for gate lengths (L/sub G/) down to 180 nm. Thirty six percent drive current enhancement was achieved for Si/sub 0.8/Ge/sub 0.2/ channel PMOSFETs compared to Si PMOSFETs with HfO/sub 2/ gate dielectric. We demonstrate that using Si/sub 1-x/Ge/sub x/ in the channel may be one way to recover the mobility degradation due to the use of HfO/sub 2/ on Si.     

A robust spacer gate process for deca-nanometer high-frequency MOSFETs

This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 μm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 μS/μm with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 μA/μm. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.     

RF CMOS modeling: a scalable model of RF-MOSFET with different numbers of fingers

A novel scalable model for multi-finger RF MOSFETs modeling is presented. All the parasitic components,including gate resistance, substrate resistance and wiring capacitance, are directly determined from the layout. This model is further verified using a standard 0.13μm RF CMOS process with nMOSFETs of different numbers of gate fingers, with the per gate width fixed at 2.5 μm and the gate length at 0.13μm. Excellent agreement between measured and simulated S-parameters from 100 MHz to 20 GHz demonstrate the validity of this model.     

Is gate line edge roughness a first-order issue in affecting the performance of deep sub-micro bulk MOSFET devices?

An experimental study of the effects of gate line edge roughness (LER) on the electrical characteristics of bulk MOSFET devices was performed. Device simulation had previously predicted that gate LER causes off-state current to increase. In our experiments, gate LER was deliberately introduced in devices with 40 nm or longer physical gate length, and we found about 3X I/sub OFF/ increase (for 40 nm gate length) in the I/sub OFF/-I/sub ON/ plot. In our devices, Source/Drain (S/D) extensions are produced by implants self-aligned to gate edges. Simulation results indicate that what really matters is the roughness induced of the S/D to channel junctions by gate LER. Implantation scattering and dopant diffusion cause the S/D to channel junctions to be smoother than the gate edges. This will partially reduce the differences in the I/sub OFF/-I/sub ON/ curves caused by differing amounts of gate LER. By optimizing our process flows, we obtained a minimized gate LER (EdgeRMS<2 nm). We believe that the consequence of this minimized LER is secondary to the impact of other process variations across wafer for devices with 40 nm or longer gate length.     

Mobility enhancement in local strain channel nMOSFETs by stacked a-Si/poly-Si gate and capping nitride

A local strained channel nMOSFET has been fabricated by a stress control technique utilizing a stacked a-Si/poly-Si gate and a SiN capping layer. It is found that the transconductance (G/sub M/) of nMOSFETs increases as the thickness of a-Si is increased. We also found that the G/sub M/ of devices with the SiN capping layer exhibits a 17% increase compared to that of its counterparts. The stacked gate a-Si/poly-Si with the capping layer can improve the G/sub M/ further to 29% more than the single-poly-Si gate structure without SiN capping layer.     

On the scaling limit of ultrathin SOI MOSFETs

In this paper, a detailed study on the scaling limit of ultrathin silicon-on-insulator (SOI) MOSFETs is presented. Due to the penetration of lateral source/drain fields into standard thick buried oxide, the scale-length theory does not apply to thin SOI MOSFETs. An extensive two-dimensional device simulation shows that for a thin gate insulator, the minimum channel length can be expressed as L/sub min//spl ap/4.5(t/sub Si/+(/spl epsiv//sub Si///spl epsiv//sub I/)t/sub I/), where t/sub Si/ is the silicon thickness, and /spl epsiv//sub I/ and t/sub I/ are the permittivity and thickness of the gate insulator. With t/sub Si/ limited to /spl ges/ 2 nm from quantum mechanical and threshold considerations, a scaling limit of L/sub min/=20 nm is projected for oxides, and L/sub min/=10 nm for high-/spl kappa/ dielectrics. The effect of body doping has also been investigated. It has no significant effect on the scaling limit.     

Extraction of the series resistance and the effective mobility in enhancement MOSFETs from weak to strong inversion using a single transistor

This work presents a new approach for the simultaneous determination of the effective channel mobility and the parasitic series resistance as a function of gate voltage in enhancement MOSFETs. The proposed method is applicable for short channel devices as well as long channel ones. It also takes into consideration the effect of interface traps and the dependence of the effective channel length on gate bias. The method is based on the measurement of the dynamic transconductance, gate-channel capacitance and the ohmic region drain current all on a single MOS transistors. The obtained results suggest a peak for the effective mobility versus gate voltage near threshold. The parasitic series resistance for short channel devices shows only slight dependence on the gate bias in the whole strong inversion region. On the contrary, for long channel devices, the series resistance significantly decreases with increasing gate voltage at the onset of strong inversion and then tends to level off as the device is pushed deeper in strong inversion.     

Analysis of the subthreshold current of pocket or halo-implanted nMOSFETs

In this work, we analyzed the subthreshold current (I/sub D/) of pocket implanted MOSFETs using extensive device simulations and experimental data. We present an analytical model for the subthreshold current applicable for any type of FET and show that the subthreshold current of nMOSFETs, which is mainly due to diffusion, is determined by the internal two-dimensional hole distribution across the device. This hole distribution is affected by the electric potential of the gate and the doping concentration in the channel. The results obtained allow accurate modelling of the subthreshold current of future generation MOS devices.     

A physically based analytical model for the threshold voltage of strained-Si n-MOSFETs

A physically based analytic model for the threshold voltage V/sub t/ of long-channel strained-Si--Si/sub 1-x/Ge/sub x/ n-MOSFETs is presented and confirmed using numerical simulations for a wide range of channel doping concentration, gate-oxide thicknesses, and strained-Si layer thicknesses. The threshold voltage is sensitive to both the electron affinity and bandgap of the strained-Si cap material and the relaxed-Si/sub 1-x/Ge/sub x/ substrate. It is shown that the threshold voltage difference between strained- and unstrained-Si devices increases with channel doping, but that the increase is mitigated by gate oxide thickness reduction. Strained Si devices with constant, high channel doping have a threshold voltage difference that is sensitive to Si cap thickness, for thicknesses below the equilibrium critical thickness for strain relaxation.     

动态阈值nMOSFET阈值电压随温度退化特性

对动态阈值nMOSFET阈值电压随温度退化特性进行了一阶近似推导和分析。动态阈值nMOSFET较之普通nMOSFET,降低了阈值电压温度特性对温度、沟道掺杂浓度及栅氧厚度等因素的敏感程度。讨论了动态阈值nMOSFET优秀阈值电压温度特性的内在机理。动态阈值nMOSFET优秀的阈值电压随温度退化特性使之非常适合工作于高温恶劣环境。     

In-depth characterization of the hole mobility in 50-nm process-induced strained MOSFETs

This letter presents the first experimental study of the mobility in 50-nm gate length (L/sub G/) pMOSFETs highly strained by a contact etch stop layer. Thanks to an advanced characterization method, the mobility is in-depth studied versus the inversion charge density, the gate length and the temperature. The physical origin of the more than 50% mobility enhancement at L/sub G/=50 nm is proven to be the low effective mass of the top valence band rather than any scattering modification. This mobility gain is maintained even at high effective field. This explains the 30% I/sub ON/ enhancement at 50-nm gate length, which is among the best results at such a dimension.