Characterization of the CH4/H2/Ar high density plasma etching process for ZnSe

High density plasma etching of zinc selenide using CH₄/H₂/Ar plasma chemistries is investigated. Mass spectrometry, using through-the-platen sampling, is used to identify and monitor etch products evolving from the surface during etching. The identifiable primary etch products are Zn, Se, ZnH₂, SeH₂, Zn(CH₃)₂, and Se(CH₃)₂. Their concentrations are monitored as ion and neutral fluxes (both in intensity and composition), ion energy, and substrate temperature are varied. General insights about the surface chemistry mechanisms of the etch process are given from these observations. Regions of process parameter space best suited for moderate rate, anisotropic, and low damage etching of ZnSe are proposed. Code 6752 Code 6174     

Gate metallurgy effects in InAs/AlSb HFETs: Preliminary results and demonstration of surface fermi level shifts

The effect of gate metallurgy on depletion-mode InAs/AlSb heterostructure field-effect transistors (HFETs) is studied for the first time by carefully comparing the characteristics of Al- and Ti/Au-gate transistors. HFETs fabricated simultaneously from the same molecular beam epitaxial layers and processed identically, but differing only in the metal used for the gate electrode, feature very different gate and drain I-V characteristics. The metal dependence indicates that the Fermi level is not completely pinned at the surface of InAs/AlSb quantum wells. We also show that the gate metal modifies the charge control properties of InAs/AlSb HFETs: Al-gate HFETs exhibit an enhanced kink effect accompanied by a marked transconductance compression at zero gate bias, whereas the Ti/Au-gate devices exhibit nearly kink-free drain characteristics. The gate metal dependence is shown to be a consequence of the increased channel equilibrium electron concentration accompanying the Al-metallization.     

Analysis of charge density and Fermi level of AlInSb/InSb single-gate high electron mobility transistor

A compact model is proposed to derive the charge density of the AlInSb/InSb HEMT devices by considering the variation of Fermi level, the first subband, the second subband and sheet carrier charge density with applied gate voltage. The proposed model considers the Fermi level dependence of charge density and vice versa. The analytical results generated by the proposed model are compared and they agree well with the experimental results. The developed model can be used to implement a physics based compact model for an InSb HEMT device in SPICE applications.     

High‐quality surface passivation of silicon solar cells in an industrial‐type inline plasma silicon nitride deposition system

We have studied the surface passivation of silicon by deposition of silicon nitride (SiN) in an industrial‐type inline plasma‐enhanced chemical vapor deposition (PECVD) reactor designed for the continuous coating of silicon solar cells with high throughput. An optimization study for the passivation of low‐resistivity p‐type silicon has been performed exploring the dependence of the film quality on key deposition parameters of the system. With the optimized films, excellent passivation properties have been obtained, both on undiffused p‐type silicon and on phosphorus‐diffused n⁺ emitters. Using a simple design, solar cells with conversion efficiencies above 20% have been fabricated to prove the efficacy of the inline PECVD SiN. The passivation properties of the films are on a par with those of high‐quality films prepared in small‐area laboratory PECVD reactors. Copyright © 2004 John Wiley & Sons, Ltd.     

Textured silicon surface passivation by high‐rate expanding thermal plasma deposited SiN and thermal SiO2/SiN stacks for crystalline silicon solar cells

Expanding thermal plasma (ETP) deposited silicon nitride (SiN) with optical properties suited for the use as antireflection coating (ARC) on silicon solar cells has been used as passivation layer on textured monocrystalline silicon wafers. The surface passivation behavior of these high‐rate (>5 nm/s) deposited SiN films has been investigated for single layer passivation schemes and for thermal SiO₂/SiN stack systems before and after a thermal treatment that is normally used for contact‐firing. It is shown that as‐deposited ETP SiN used as a single passivation layer almost matches the performance of a thermal oxide. Furthermore, the SiN passivation behavior improves after a contact‐firing step, while the thermal oxide passivation degrades which makes ETP SiN a better alternative for single passivation layer schemes in combination with a contact‐firing step. Moreover, using the ETP SiN as a part of a thermal SiO₂/SiN stack proves to be the best alternative by realizing very low dark saturation current densities of <20 fA/cm² on textured solar‐grade FZ silicon wafers and this is further improved to <10 fA/cm² after the anneal step. Optical and electrical film characterizations have also been carried out on these SiN layers in order to study the behavior of the SiN before and after the thermal treatment. Copyright © 2008 John Wiley & Sons, Ltd.     

A study of the role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O2 based high density plasma for advanced DRAMs

The role of HBr and oxygen on the etch selectivity and the post-etch profile in a polysilicon/oxide etch using HBr/O₂ based high density plasma was studied. HBr/O₂-based polysilicon etch process used in this study seems to be highly selective to the underlying oxide and produce a dielectric fill-friendly post-etch profile depending on the flow rates of HBr and oxygen. When appropriate amounts of HBr and oxygen (∼30 sccm of HBr and ∼3 sccm of oxygen) are present in the etch plasma, brominated silicon oxide seems to be deposited on the original gate oxide and the gate stack sidewall from the reaction of SiBr_x (reaction product during polysilicon etch step) and oxygen during the HBr/O₂-based oxide etch process. The deposited brominated oxide on the thin gate oxide seems to make the HBr/O₂-based plasma etch process extremely selective to the thin gate oxide by protecting the underlying gate oxide. The deposited brominated oxide on the gate stack sidewall seems to prevent the notching by protecting the sidewall during gate stack etching. The etch rate of the brominated oxide seems to be much faster than that of the thermal oxide during the 200:1 diluted HF cleaning. However, the deposited brominated oxide on the thin gate oxide and the gate stack sidewall during the plasma etching survived the following 1 min 200:1 diluted HF cleaning, as was observed in a TEM micrograph (Fig. 2(a)).     

Role of interface chemistry and growing surface stoichiometry on the generation of stacking faults in ZnSe/GaAs

The existence of Zn-As and vacancy-contained Ga-Se interfacial layers are suggested by transmission electron microscopy of Zn-and Se-exposed (or - reacted) ZnSe/GaAs interfaces, respectively. A very low density of faulted defects in the range of ∼10⁴cm² was obtained in samples with Zn passivation on an Asstabilized GaAs-(2 × 4). However, the density of As precipitates increases as the surface coverage of c(4 × 4) reconstruction increased on the Zn-exposed Asstabilized GaAs-(2 × 4) surface and this is associated with an increase of the density of extrinsic-type stacking faults bound by partial edge dislocations with a core structure terminated on additional cations. On the other hand, densities of extrinsic Shockley-and intrinsic Frank-type stacking faults are of ∼5 × 10⁷/cm² in samples grown on Se-exposed Ga-rich GaAs-(4 × 6) surfaces. Annealing on this Se-exposed Ga-rich GaAs-(4 × 6) generated a high density of vacancy loops (1 × 10⁹/cm²) and an increase of the densities of both Shockley-and Frank-type stacking faults (>5 × 10⁸/cm²) after the growth of the films. Furthermore, we have studied the dependence of the generation and structure of Shockley-type stacking faults on the beam flux ratios in samples grown on Zn-exposed As-stabilized GaAs-(2 × 4) surfaces. Cation-and anion-terminated extrinsic-type partial edge dislocations were generated in samples grown under Zn-and Se-rich conditions, respectively. However, an asymmetric distribution on defect density under varied beam flux ratios (0.3 ≤ P_Se/P_Zn ≤ 10) is obtained.     

GaAs半导体表面的S-N混合等离子体钝化及在激光器工艺上的应用

利用射频(RF)等离子方法,对GaAs半导体表面进行 了S-N混合等离子体钝化实验,并对工作压强、RF 功率进行了优化。光致发光(PL)测试结果表明,经过S-N混合等离子体钝化的GaAs样品PL 强度提高135%。将本文 钝化方法应用到980nm波长InGaAs应变量子阱(QW)激光器的制备工艺 ,器件的COD阈值功率明显增加。     

Local charge neutrality condition, Fermi level and majority carrier density of a semiconductor with multiple localized multi-level intrinsic/impurity defects

For semiconductors with localized intrinsic/impurity defects,intentionally doped or unintentionally incorporated, that have multiple transition energy levels among charge states,the general formulation of the local charge neutrality condition is given for the determination of the Fermi level and the majority carrier density.A graphical method is used to illustrate the solution of the problem.Relations among the transition energy levels of the multi-level defect are derived using the graphical method.Numerical examples are given for p-doping of the CdTe thin film used in solar panels and semi-insulating Si to illustrate the relevance and importance of the issues discussed in this work.     

Local charge neutrality condition, Fermi level and majority carrier density of a semiconductor with multiple localized multi-level intrinsic/impurity defects

For semiconductors with localized intrinsic/impurity defects, intentionally doped or unintentionally incorporated, that have multiple transition energy levels among charge states, the general formulation of the local charge neutrality condition is given for the determination of the Fermi level and the majority carrier density. A graphical method is used to illustrate the solution of the problem. Relations among the transition energy levels of the multi-level defect are derived using the graphical method. Numerical examples are given for p-doping of the CdTe thin film used in solar panels and semi-insulating Si to illustrate the relevance and importance of the issues discussed in this work.     

紧束缚带半导体中载流子浓度和费米能量解析近似研究

本文给出了紧束缚带半导体中载流子浓度和费米能量之间的解析近似表达式。借助贝塞尔函数我们获得载流子浓度的系列展开公式,该公式具有快速收敛性。采用高斯积分方法获得了简单和高精度的费米能量解析近似表达式。由解析公式计算的结果与精确数值解吻合得很好,精度为10^-5量级。该解析公式可以方便地用于计算微带超晶格的电子输运和超晶格器件模拟。     

Extremely low surface recombination velocities on low‐resistivity n‐type and p‐type crystalline silicon using dynamically deposited remote plasma silicon nitride films

Extremely low upper‐limit effective surface recombination velocities (S_eff.max) of 5.6 and 7.4 cm/s, respectively, are obtained on ~1.5 Ω cm n‐type and p‐type silicon wafers, using silicon nitride (SiN_x) films dynamically deposited in an industrial inline plasma‐enhanced chemical vapour deposition (PECVD) reactor. SiN_x films with optimised antireflective properties in air provide an excellent S_eff.max of 9.5 cm/s after high‐temperature (>800 °C) industrial firing. Such low S_eff.max values were previously only attainable for SiN_x films deposited statically in laboratory reactors or after optimised annealing; however, in our case, the SiN_x films were dynamically deposited onto large‐area c‐Si wafers using a fully industrial reactor and provide excellent surface passivation results both in the as‐deposited condition and after industrial‐firing, which is a widely used process in the photovoltaic industry. Contactless corona‐voltage measurements reveal that these SiN_x films contain a relatively high positive charge of (4–8) × 10¹² cm⁻² combined with a relatively low interface defect density of ~5 × 10¹¹ eV⁻¹ cm⁻². Copyright © 2012 John Wiley & Sons, Ltd.     

SiOyNx/SiNx stack: a promising surface passivation layer for high‐efficiency and potential‐induced degradation resistant mc‐silicon solar cells

A thin SiO_yN_x film was inserted below a conventional SiN_x antireflection coating used in c‐Si solar cells in order to improve the surface passivation and the solar cell's resistance to potential‐induced degradation (PID). The effect of varying the flow ratio of the N₂O and SiH₄ precursors and the deposition temperature for the SiO_yN_x thin film upon material properties were systematically investigated. An excellent surface passivation was obtained on FZ p‐type polished silicon wafers, with the best results obtained with a SiO_yN_x film deposited at a very low temperature of 130 °C and with an optical refractive index of 1.8. In the SiO_yN_x/SiN_x stack structure, a SiO_yN_x film with ~6 nm thickness is sufficient to provide excellent surface passivation with an effective surface recombination velocity S_eff < 2 cm/s. Furthermore, we applied the optimized SiO_yN_x/SiN_x stack on multicrystalline Si solar cells as a surface passivation and antireflection coating, resulting in a 0.5% absolute average conversion efficiency gain compared with that of reference cells with conventional SiN_x coating. Moreover, the cells with the SiO_yN_x/SiN_x stack layers show a significant increase in their resistance to PID. Nearly zero degradation in shunt resistance was obtained after 24 h in a PID test, while a single SiN_x‐coated silicon solar cell showed almost 50% degradation after 24 h. Copyright © 2016 John Wiley & Sons, Ltd.     

一种Ka频段高密度高集成瓦式T组件的设计

介绍了一种Ka频段瓦式T组件的设计方法和关键技术.采用多层印制电路板(Printed Cir-cuit Board,PCB)技术,实现了无源网络和馈电网络集成在同一块多层电路板上,滤波功能层和天线一体化集成,利用毛纽扣实现了组件的三维垂直互联.采用互补金属氧化物半导体(Complementary Metal Oxide...     

Influence of the additives argon, O2, C4F8, H2, N2 and CO on plasma conditions and process results during the etch of SiCOH in CF4 plasma

Reactive ion etch processes for modern interlevel dielectrics become more and more complex, especially for further scaling of interconnect dimensions. The materials will be damaged within such processes with the result of an increase in their dielectric constants. The capability of selected additives to minimize the low-k sidewall damage during reactive ion etching (RIE) of SiCOH materials in fluorocarbon plasmas was shown in different works in the past. Most of the investigated additive gases alter the fluorine to carbon ratio as well as the dissociation of the parent gas inside the etch plasma. The result is a changed etch rate, a modified polymerization behavior and other characteristics of the process induced SiCOH damage. Heavy inert ions like argon will be accelerated to the sample surface in the cathode dark space and enhance therewith the sputter yield on the SiCOH network [1]. In this paper the additives Ar, O₂, C₄F₈, H₂, N₂ and CO were added to a conventional CF₄ etch plasma. We try to provoke different changes in the plasma conditions and therewith in the process results. Contact angle measurements, spectroscopic ellipsometry, Hg-probe analysis, FTIR measurements and SEM cross-sections were used to overview the additive induced modifications. To understand the influences of the additives gases more exactly, changes in the physical and chemical plasma behavior must be analyzed. Therefore quadrupole mass spectrometry (QMS) and quantum cascade laser absorption spectroscopy (QCLAS) were used.     

Analysis of high temperature effects on performances and hot-carrier degradation in DC/AC stressed 0.35 μm n-MOSFETs

The transistor performances and hot-carrier reliability in n-MOSFETs are investigated at high temperature in the range 25–125 °C. A careful analysis of the temperature dependence of the device parameters shows that transistor performances are significantly reduced and that the Fermi potential, the mobility and current reductions, contribute to decrease the device sensitivity to the hot-carrier damage at high temperature. Different degradation behaviors are found between DC and AC stressing depending on the degradation mechanisms i.e. whether the interface trap generation or oxide charge trapping dominates which consequently exhibits a strong temperature dependence through their magnitude and localization. It is pointed out that the reduction of the ionization rate significantly impacts the degradation behaviors at elevated temperature. Even if the amount of generated damage is slightly larger than what effectively influences the transistor characteristics, the parameter insensitivity to given at high temperature improves the transistor reliability. This improvement is determined in the value of the device lifetime at 125 and 70 °C using inverter and pass transistor operations in a 0.35 μm LDD complementary metal-oxide semiconductor (CMOS) technology suitable for 3.3 V operation.     

高厚径比板湿制程主要失效模式及预防控制

高层次、高厚径比板具有较高的附加值,现已成为我公司主要制作产品之一。文章主要是简述此类型板在我公司湿制程过程中出现的一些异于其它普通板的失效模式及其预防控制方式。     

利用CH4/H2/Ar及Cl2高密度等离子体对InSb的高速率刻蚀研究（英文）

利用感应耦合等离子体(ICP)进行了InSb刻蚀研究。为了实现高的刻蚀速率同时保证光滑的刻蚀表面,研究中在CH4/H2/Ar气氛中引入了Cl2。研究发现,对InSb的刻蚀速率随Cl2含量及ICP功率的升高而线性增加。当Cl2含量增加到超过12%或ICP功率大于900 W时,刻蚀表面变得粗糙,而易引起刻蚀损伤的直流偏压随ICP功率的升高而降低。此现象归因于刻蚀副产物InCl3在样品表面的聚集进而妨碍均匀刻蚀反应所致。当样品温度从20℃提高到120℃,刻蚀速率及表面粗糙度无明显变化。通过试验研究,实现了对InSb的高速率、高垂直度刻蚀,刻蚀速率大于500 nm/min,对SiO2掩模刻蚀选择比大于6,刻蚀表面光洁,刻蚀垂直度可达80°。     

Percolation and excitonic luminescence in SiO<Subscript>2</Subscript>/ZnO two-phase structures with a high density of quantum dots randomly distributed over a spherical surface

The results of studies of structures formed of silica (SiO₂) nanospheres and ZnO quantum dots randomly distributed over the nanosphere surface to cover an ∼0.45 fraction of the surface area are given. Because of the large surface energy of the spheres, the quantum dots formed on their surface are shaped as disks, wherein charge carriers are influenced by the quantum-confinement effect despite the large disk radii. The disk height is calculated by the effective mass method. The height is found to be comparable with the diameter of excitons in bulk ZnO. Analysis of the optical spectra shows that, at the above-indicated surface area covered with quantum dots, excitons in the array of quantum dots are above the percolation level. The use of some concepts of the percolation theory and knowledge of the topological arrangement of the samples make it possible to obtain quantitative parameters that describe this phenomenon.     

Accurate surface potential determination in Schottky diodes by use of correlated current and capacitance voltage measurements. Application to n–InP

Based on current voltage (I-V_g) and capacitance voltage (C-V_g) measurements, a reliable procedure is proposed to determine the effective surface potential V_d.V_g/ in Schottky diodes. In the framework of thermionic emission, our analysis includes both the effect of the series resistance and the ideality factor, even voltage dependent. This technique is applied to n-type indium phosphide (n-InP) Schottky diodes with and without an interfacial layer and allows us to provide an interpretation of the observed peak on the C-V_g measurements. The study clearly shows that the depletion width and the flat band barrier height deduced from C-V_g, which are important parameters directly related to the surface potential in the semiconductor, should be estimated within our approach to obtain more reliable information.