Prelayout interconnect yield prediction

Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges.     

Sequential delay budgeting with interconnect prediction

Delay budgeting is a process of determining upper bounds for net delays to guide timing-driven placement. The existing approaches deal de facto only with combinational circuits. However, incorporating retiming into delay budgeting introduces more freedom to optimize sequential circuits. In this paper, we propose an approach for budgeting sequential circuits. We propose a new linear programming formulation for timing-aware sequential budgeting, which guarantees that the clock period constraints are met. We demonstrate the usefulness of our approach in the context of field-programmable gate arrays placement flow. We have performed two experiments. The first experiment compares sequential budgeting with traditional budgeting and retiming. The results show that the new placement flow reduces budget violations by 16% and improves timing by 9%. In the second experiment, we demonstrate methods of interconnect length prediction that are useful to estimate delay and to decide net weighting in sequential budgeting. We compare net delay predictions using traditional delay budgeting, the Donath's method, and mutual contraction. The results from this experiment show that sequential budgeting, using the new net weighting and predicted delays, can improve circuit speeds on average by 12.29%, compared to traditional timing-driven placement. The new net weighting method also performs better than a uniform weighting method.     

Multiple block structure-preserving reduced order modeling of interconnect circuits

In this paper, we propose a generalized multiple-block structure-preserving reduced order interconnect macromodeling method (BSPRIM). Our approach extends the structure-preserving model order reduction (MOR) method SPRIM [R.W. Freund, SPRIM: structure-preserving reduced-order interconnect macromodeling, in: Proceedings of International Conference on Computer Aided Design (ICCAD), 2004, pp. 80-87] into more general block forms. We first show how an SPRIM-like structure-preserving MOR method can be extended to deal with admittance RLC circuit matrices and show that the 2q moments are still matched and symmetry is preserved. Then we present the new BSPRIM method to deal with more circuit partitions for linear dynamic circuits formulated in impedance and admittance forms. The reduced models by BSPRIM will still match the 2q moments and preserve the circuit structure properties like symmetry as SPRIM does. We also show that BSPRIM can build the compact models with similar size and accuracy of that produced by traditional projection based methods but using less computation costs. Experimental results show that BSPRIM outperforms SPRIM in terms of accuracy with more partitions and outperforms PRIMA with less CPU times for generating the same accurate models.     

A comparison of various terminal-gate relationships for interconnect prediction in VLSI circuits

Over the years, different interpretations of Rent's rule and different ways of estimating the Rent parameters have emerged. In general, these parameters are extracted from the average terminal-gate relationship for a set of circuit modules. We show that this relationship (the Rent characteristic) strongly depends on the definition of the circuit modules. These can be generated in many different ways, either from the topology of the circuit graph or, in a geometric way, by cutting regions from a circuit layout. The resulting Rent parameters can be quite far apart. This paper discusses the fundamental differences between the topological and the two geometric interpretations of the Rent characteristic that are expected to be most appropriate for current wirelength estimation techniques. Our discussion is based on experimental data, as well as on a theoretical model that can be used to estimate certain geometric Rent characteristics from the topological Rent parameters. Using this model, we derive a theoretical lower limit to the value of the average geometric Rent exponent. We also study the impact of the placement approach and placement quality on the geometric Rent characteristics.     

Waveform analysis and delay prediction for a CMOS gate driving RLC interconnect load

This paper deals with the problem of estimating the performance of a CMOS gate driving RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is used for the representation. The CMOS gate is modeled by an Alpha Power law model, whereas the distributed RLC interconnect is represented by an equivalent π-model. The output waveform and the propagation delay of the inverter are analytically calculated and compared with SPICE simulations. The analytical driver-interconnect load model gives sufficiently close results to SPICE simulations for two different cases of slow and fast input ramps. For each case of stimulation, the model gives an insight to four regions of operation of the CMOS gate. The voltage waveform at the end of an interconnect line is obtained for each region of operation. The SPICE and analytical results for the output voltage waveform and propagation delay match very closely.     

Probabilistic prediction of wiring demand and routing requirementsfor high density interconnect substrates

Estimation of wiring and routability requirements for high density substrates is crucial for the development of new technologies, design, CAD tools, and optimization. This paper describes a new approach to wireability estimation that goes beyond Rent's rule. This approach depends on data flow and placement information available at early stages of the design process. Bus and random wiring are modeled explicitly. Excellent overall agreement is demonstrated between our predictions and published wiring data for two MCM systems. The relationship between placement and wireability will be presented through an optimization study by taking wiring parameters and their distributions as metrics. The application of this approach to the estimation of the required signal layers will be demonstrated     

Efficient and accurate crosstalk prediction via neural net-basedtopological decomposition of 3-D interconnect

Crosstalk-related issues have become increasingly important with deep submicron downscaling of ICs and wafer scale integration. In today's systems-on-a-chip, the delay through a wire is often greater than the delay through the gate driving it. Furthermore, because of significant parasitic effects, crosstalk between signals on wires can cause major problems. Improved management of the EMI problem is made possible via EDA tools which have the capability of accurately and efficiently modeling electromagnetic interference effects in nanoscale VLSI. However, existing tools are computationally expensive and do not have broad application. The novel methodology proposed in this paper involves topological decomposition of small portions of interconnect (referred to as wirecells) at an extreme level of detail and the creation of parameterized models of these primitive interconnect structures using modular artificial neural networks (MANNs). The technique uses a finite element method program coupled with a circuit simulator and a neural network multi-paradigm prototyping system to produce a library of standard MANN-based wirecell models. It is especially attractive because none of the existing approaches is capable of fully modeling the simultaneous effect on delay and crosstalk of several uncorrelated variables such as interconnect length, width, thickness, separation, metal and insulating medium conductivity and relative permittivity for multiple systems of conductors. The library models derived are used to predict delay noise and crosstalk resulting from interconnect structures embedded in actual analog and digital circuitry     

Compression of image block means for non-equal block partition schemes using Delaunay triangulation and prediction

An approach based on applying Delaunay triangulation to the compression of mean values of image blocks that have non-identical shape and size is proposed. It can be useful for image compression methods that require the use of image partition schemes with non-equal block sizes, such as fractal and DCT-based image coding. Some aspects of practical realisation of the proposed method are discussed. Evaluation of the performance of the proposed method is carried out and comparisons with some conventional methods are made, demonstrating the potential of the method.     

HEVC帧内预测模式和分组码的视频信息隐藏

为了在最新的视频压缩标准－高效视频编码(HEVC) 下实现信息隐藏并在保证隐秘信息嵌入容量的前提下减少对宿 主信息的修改,提出基于帧内预测模式和分组码的HEVC视频信息隐藏方法。首先,利用分组 码的标准阵 列译码方法,建立(4,3)码标准阵列译表;然后,根据译码表与预测模式的映射关系,调 制帧内4×4亮 度块的预测模式嵌入隐秘信息;最后,对调制后的4×4亮度块重新编码,使得在连续4个4× 4帧内亮度 块嵌入3bit隐秘信息,平均修改1.25位预测模式,减小因调制预测模式对视频造成的影响 。实验结果表 明:所提算法的PSNR值下降在0.05 dB以内,码率增长在1%左右 ,算法能很好的保证视频主客观质量,对视频的编码比特率影响很小。     

Jointly optimized spatial prediction and block transform for video and image coding

This paper proposes a novel approach to jointly optimize spatial prediction and the choice of the subsequent transform in video and image compression. Under the assumption of a separable first-order Gauss-Markov model for the image signal, it is shown that the optimal Karhunen-Loeve Transform, given available partial boundary information, is well approximated by a close relative of the discrete sine transform (DST), with basis vectors that tend to vanish at the known boundary and maximize energy at the unknown boundary. The overall intraframe coding scheme thus switches between this variant of the DST named asymmetric DST (ADST), and traditional discrete cosine transform (DCT), depending on prediction direction and boundary information. The ADST is first compared with DCT in terms of coding gain under ideal model conditions and is demonstrated to provide significantly improved compression efficiency. The proposed adaptive prediction and transform scheme is then implemented within the H.264/AVC intra-mode framework and is experimentally shown to significantly outperform the standard intra coding mode. As an added benefit, it achieves substantial reduction in blocking artifacts due to the fact that the transform now adapts to the statistics of block edges. An integer version of this ADST is also proposed.     

Two-pole approximation for interconnect design and optimization

Firstly, an approach to find two approximate poles for capturing the system behaviour of interconnect network is presented. Secondly, two parameters, the damping ratio and natural undamped frequency, are expressed as functions of the two poles. These two parameters are used to define an objective function and constraints, which form a constrained multivariable nonlinear optimization problem. The optimization problem is solved using a gradient projection method. One major advantage of our approach is the ability to explicitly control the maximum overshoots at the observation points.     

Decoder-based interconnect structure for multi-context FPGAs

Multi-context FPGAs could be a convenient approach for run-time reconfiguration, but they suffer from large area occupation. To overcome this limitation a new decoder-based interconnection architecture has been studied. Both a multi-context memory cell and a decoder scheme are presented to achieve minimum area occupation.     

2001 needs for multi-level interconnect technology

Looks at the materials and thermal alternatives for scaled, next-century VLSI/ULSI interconnects. It is shown that ad hoc executions of programs to calculate interconnect parameters for VLSI/ULSI design and analysis are too time-consuming to be practical. The tool used in this study to model a hypothetical interconnect system was Hewlett Packard's HTVE (HP Interconnect Value Extractor)     

Linear prediction receiver for differential space-time block codes with spatial correlation

The differential space-time block code is well-known to provide full spatial diversity and allows simple differential detection. Recent results have shown performance degradation when the channel is time-varying. The letter shows the effect on error performance of spatial correlation between transmit antennas. A generalized receiver which exploits spatial correlation information, is proposed and shown to outperform an existing receiver in terms of frame error rate for slowly varying channels with moderate to high spatial correlation.     

A PREDICTION BASED ALL—ZERO BLOCK DETECTION METHOD FOR H．263

In this letter,a novel method based on Temporal and Spatial Prediction(TSP)to detect all-zero DCT coefficients based on temporal and spatial prediction between neighboring blocks is proposed.The presented algorithm uses the knowledge of all-zero block distribution in the previous frame combined with the Sum of Absolute Difference(SAD)of the corresponding macroblock as a criterion .The algorithm almost needs no additional computation ,and it shows an excellent overall detection performance in simulations.     

Coding schemes for chip-to-chip interconnect applications

Increasing demand for high-speed interchip interconnects requires faster links that consume less power. The Shannon limit for the capacity of these links is at least an order of magnitude higher than the data rate of the current state-of-the-art designs. Channel coding can be used to approach the theoretical Shannon limit. Although there are numerous capacity-approaching codes in the literature, the complexity of these codes prohibits their use in high-speed interchip applications. This work studies several suitable coding schemes for chip-to-chip communication and backplane application. These coding schemes achieve 3-dB coding gain in the case of an additive white Gaussian noise (AWGN) model for the channel. In addition, a more realistic model for the channel is developed here that takes into account the effect of crosstalk, jitter, reflection, inter-symbol interference (ISI), and AWGN. Interestingly, the proposed signaling schemes are significantly less sensitive to such interference. Simulation results show coding gains of 5-8 dB for these methods with three typical channel models. In addition, low-complexity decoding architectures for implementation of these schemes are presented. Finally, circuit simulation results confirm that the high-speed implementations of these methods are feasible.     

基于LSTM流量预测的路由规划和切换

随着近年网络技术的不断发展和演进,用户对网络资源的需求体量越来越大,内容越来越复杂,传统的网络架构很难满足当前灵活的网络需求。软件定义网络的革命性技术思想赋予了网络可编程性和可演进性,实现网络资源更灵活的管理。为了提高网络资源利用率,提出了基于LSTM模型的流量预测,为路由规划提供理论依据。通过提前预测网络流量,在流量激增之前进行防御措施保证网络的安全性和稳定性。实现基于流量预测的路由规划、无损路径切换等功能。     

Projecting interconnect electromigration lifetime for arbitrarycurrent waveforms

A vacancy-relaxation model is proposed. It predicts the DC lifetime, pulse DC (arbitrary unidirectional waveform) lifetime, pure AC lifetime, and AC-plus-DC-bias lifetime for all waveforms and all frequencies above 1 kHz. The predictions are verified by experiments and significantly raise the projected lifetimes beyond the widely assumed A_dc T/J_rms^m. The pure AC lifetimes of aluminum interconnect are experimentally found to be more than 10³ times larger than DC lifetime for the same current density. In addition, AC stress lifetimes are observed to follow the same dependences on current magnitude and temperature, for T<300°C, as the DC stress lifetime