Design and optimization of CMOS RF power amplifiers

A CMOS radio-frequency power amplifier including on-chip matching networks has been designed in a 0.6-μm n-well triple-metal digital CMOS process, and optimized using a simulated-annealing-based custom computer-aided design tool. A compact inductor model enables the incorporation of parasitics as an integral part of the parasitic-aware design and CAD optimization; low-Q metal3 spiral inductors are used in the input and output matching networks. A 3-V 85-mW balanced fully integrated Class-C power amplifier with a measured drain efficiency of 55% at 900 MHz has been designed, optimized, integrated, and tested     

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.     

0.6V CMOS低噪声放大器的设计与优化*

采用SMIC 0.18 μm CMOS工艺设计了一个低电压低功耗的低噪声放大器(Locked Nucleic Acid,LNA).分析了在低电压条件下LNA的线性度提高及噪声优化技术.使用Cadence SpectreRF仿真表明,在2.4 GHz的工作频率下,功率增益为19.65 dB,输入回波损耗S11为-12.18 dB,噪声系数NF为1.2 dB,1 dB压缩点为-17.99 dBm,在0.6V的供电电压下,电路的静态功耗为2.7 mW,表明所设计的LNA在低电压低功耗的条件下具有良好的综合性能.     

Design optimization methodology for deep-submicrometer CMOS deviceat low-temperature operation

The design optimization for 0.3-μm channel CMOS technology at liquid-nitrogen temperature (77 K) is described. The tradeoff between circuit performance and reliability for deep-submicrometer CMOS devices at low-temperature operation is theoretically and experimentally examined. A simulator, which selects power-supply voltage and process/device parameters for low-temperature operation, has been developed. Based upon the simulated results, design optimization for low-temperature operation has been proposed to determine power-supply voltage and various process and device parameters. The optimized design has been demonstrated on a 0.3-μm CMOS device, by utilizing electron beam (EB) lithography· Excellent device characteristics and a functional ring oscillator circuit have been obtained at 77 K     

一种超宽带CMOS除二电路及其优化方法

本文提出了一种新型的基于轮换触发的除二电路及其基于大信号分析的优化方法。通过减小跟随相输出节点的RC常数,增大锁存相输出节点的RC常数,减小内部信号摆幅和补偿锁存相输出节点漏电流的损失等电路技术,大大拓宽了其工作频带。本论文在SMIC 0.13μm RF CMOS工艺条件下设计了一款原型电路,其后仿工作频率可以达到320MHz到29.6GHz。此外,这款除二电路还应用于两款整数分频锁相环芯片中,分别对频率为4224MHz和10GHz的信号进行分频。测试结果表明,这款除二电路可以对其进行正确分频,而且整体锁相环的带内相噪分别为-94dBC/Hz@10kHz和-84dBc/Hz@10kHz.     

Design and optimization of an ultra-wide frequency range CMOS divide-by-two circuit

A novel toggled flip-flop(TFF) divide-by-two circuit(DTC) and its optimization method based on a large-signal analysis approach are proposed.By reducing the output RC constant in tracking mode and making it large in latching mode,compressing the internal signal swing as well as compensating the current leaked in the latching mode, the operating frequency range is greatly expanded.Implemented in a SMIC 0.13μm RF CMOS process with a 1.2 V power supply,it can work under an ultra-wide frequency band ranging ...     

Design methodology and optimization of gate-driven NMOS ESDprotection circuits in submicron CMOS processes

This paper describes the design methodology for gate driven NMOS ESD protection in submicron CMOS processes. A new PNP Driven NMOS (PDNMOS)-protection scheme is presented. Without requiring any additional process steps or introducing any additional impedance in signal path, the PDN-MOS is effective even for small analog/mixed-signal designs. SPICE simulations are used to optimize the design. High ESD performance of the PDNMOS protection in both nonsilicided and silicided submicron processes is demonstrated in this work     

CMOS circuit optimization

In this paper, optimization algorithms for CMOS circuits are described, from the propagation delay time viewpoint. The propagation delay time for a CMOS in erter is calculated for a step function input. A classical model of I–V characteristics for a MOSFET and the worst case Sah model for inter-electrode capacitances of a MOSFET are used for this deduction.     

Design and optimization of high voltage LDMOS transistors on 0.18 μm SOI CMOS technology

In this paper, we have studied the effect of systematic downscaling of MOS channel length of the performance of the hybrid GaN MOS-HEMT with numerical simulations. The improvement in on-state conduction, together with concomitant short channel effects, including drain induced barrier lowering (DIBL) is quantitatively evaluated. A specific on-resistance of 2.1 mΩ cm² has been projected for a MOS channel length of 0.38 μm. We also have assessed the impact of high-k gate dielectrics, such as Al₂O₃. In addition, we have found that adding a thin GaN cap layer on top of AlGaN barrier can help reducing short channel effects.     

Magnetotransistor in CMOS technology

An investigation of the magnetic-field sensitivity of a lateral double-base contact n-p-n magnetotransistor compatible with CMOS technology is reported. An approximate theoretical analysis of the sensitivity is made. Two physical mechanisms are considered: current deflection and injection modulation. The deflection mechanism is more significant. It yields a sensitivity proportional either to the Hall mobility of the minority carriers if the accelerating field is weak, or to the sum of the Hall mobilities of both carrier types if tile field is strong. The sensitivity is also proportional to the base length. Experimental results corroborate the theoretical predictions. Relative sensitivities of the collector current as high as 1.5 µA/µA . T are measured.     

Design of a DPCM codec for VLSI realization in CMOS technology

Current perspectives on broad-band communication services have made the realization of a DPCM system for video coding on a single integrated circuit particularly important. A nonadaptive intraframe DPCM system is designed for reducing video transmission bit rate by a factor of two. All functional blocks of a DPCM codec have been specified, and modifications have been investigated for reducing speed requirements. Alternative realizations of functional blocks, e.g., adders, subtractors, table look-up operations, are compared with respect to speed by a simple delay model. A one-chip VLSI implementation of an efficient DPCM codec will be possible with a 2-µm CMOS technology.     

Design and modelling of a multi-standard fractional PLL in CMOS/SOI technology

This paper deals with the design of a fractional PLL for wireless multi-standard applications. This circuit has been produced using CMOS/SOI technology, with body voltage to control power consumption and phase noise performance. Five standards are covered by this structure: GSM (900 MHz), DCS (1.8 GHz), Bluetooth (2.45 GHz) and 802.11a (5.8 GHz). Based on multi-engine simulators, associated with a hierarchical models library, a virtual RF system platform, which allows designing complex SoCs, is also presented. The PLL, including digital and analogue parts, constitutes a very good benchmark to validate this platform.     

High-voltage solutions in CMOS technology

This paper presents trends on CMOS high-voltage techniques for power integrated circuits (PICs). Several fully CMOS compatible drain engineering techniques will be presented. Experimental devices were fabricated in standard CMOS processes from three different lithography generations (2, 0.7 and 0.5 μm) without resorting to any extra processing steps. MOS devices layout specificity towards performance improvement, namely breakdown, parasitic effects and degradation, will be emphasized.A recently developed technique used to enlarge high-voltage devices safe-operating area and reduce leakage current will also be presented due to the very promising experimental results.Comparison with more sophisticated and expensive technologies still reveals CMOS as a highly accessible and versatile technology for future PICs.     

Synchronization reliability in CMOS technology

The synchronization performance of CMOS circuits is examined theoretically and experimentally. Criteria for maximizing CMOS gain are determined and are then compared with NMOS gain curves. The phase characteristics of metastability are identified. Experimental measurements of error rate are made on a CMOS test circuit, and the gain-bandwidth product for the circuit is determined from these data.     

高性能单光子雪崩二极管在180 nm CMOS工艺中的设计与实现

为了实现大阵列电路集成,文中设计和实现了一种能与主动淬火电路集成的宽光谱范围和快速的单光子雪崩二极管(SPAD)芯片.一个精确的单光子雪崩二极管电路模型模拟了其在盖革模式下的静态和动态行为.该有源区直径为8 μm的单光子雪崩二极管器件是基于上海宏利GSMC 180 nm CMOS图像传感器(CIS)技术实现的.由于采用有效的器件结构,其击穿电压是15.2 V,淬灭时间是7.9 ns.此外,该器件实现了宽的光谱灵敏度,其在低过电压下的光子探测概率(PDP)从470 nm到680 nm光波长段最高可达15.7%.并且它在室温下的暗计数率相当低.     

Stacked inductors and transformers in CMOS technology

A modification of stacked spiral inductors increases the self-resonance frequency by 100% with no additional processing steps, yielding values of 5 to 266 nH and self-resonance frequencies of 11.2 to 0.5 GHz. Closed-form expressions predicting the self-resonance frequency with less than 5% error have also been developed. Stacked transformers are also introduced that achieve voltage gains of 1.8 to 3 at multigigahertz frequencies. The structures have been fabricated in standard digital CMOS technologies with four and five metal layers     

应用于2.4GHz无线传感网的带ESD保护CMOS低噪声放大器的设计与优化

本文给出一种新的带ESD保护源极电感负反馈低噪声放大器优化方法,可以实现在功耗受限条件下的噪声和输入同时匹配,并给出了输入阻抗和噪声参数的分析。采用该方法设计并优化了一个基于0.18-μm RF CMOS工艺、应用于无线传感网的2.4GHz低噪声放大器。测试结果表明,低噪声放大器的噪声系数为1.69dB,功率增益为15.2dB,输入1dB压缩点为-8dBm,输入三阶截点为1dBm,1.8V电源电压下的工作电流为4mA。     

Design and optimization of CMOS LNA with ESD protection for 2.4 GHz WSN application

A new optimization method of a source inductive degenerated low noise amplifier(LNA) with electrostatic discharge protection is proposed.It can achieve power-constrained simultaneous noise and input matching. An analysis of the input impedance and the noise parameters is also given.Based on the developed method,a 2.4 GHz LNA for wireless sensor network application is designed and optimized using 0.18-μm RF CMOS technology. The measured results show that the LNA achieves a noise figure of 1.59 dB,a power gain of 14.12 dB, an input 1 dB compression point of-8 dBm and an input third-order intercept point of 1 dBm.The DC current is 4 mA under a supply of 1.8 V.     

工作在0.5V电压下用于无线传感网的低噪声放大器设计与优化

本文阐述了一款用于无线传感器网络可工作在0.5V电压下的低噪声放大器芯片的设计和优化方法。该芯片采用0.13 um CMOS工艺实现。本文中对其电路进行了详细分析,并提出了一种新的优化设计方法。该芯片的测试结果显示,此款低噪声放大器的功率增益为14.13dB,噪声系数最低为1.96dB,直流功耗3mW,输入1dB压缩点为-19.9dBm。S11和S22均在-10dB以下。测试结果显示此款低噪放完全适用于低电压低功耗应用。