On the feasibility of CMOS multiband phase shifters for multiple-antenna transmitters

We present the design of an integrated multiband phase shifter in RF CMOS technology for phased array transmitters. The phase shifter has an embedded classical distributed amplifier for loss compensation. The phase shifter achieves a more than 180/spl deg/ phase tuning range in a 2.4-GHz band and a measured more than 360/spl deg/ phase tuning range in both 3.5-GHz and 5.8-GHz bands. The return loss is less than -10dB at all conditions. The feasibility for transmitter applications is verified through measurements. The output power at a 1-dB compression point (P/sub 1 dB/) is as high as 0.4dBmat 2.4GHz. The relative phase deviation around P/sub 1 dB/ is less than 3/spl deg/. The design is implemented in 0.18-/spl mu/mRF CMOS technology, and the chip size is 1200/spl mu/m /spl times/ 2300 /spl mu/m including pads.     

RF MEMS phase shifters based on PCB MEMS technology

An X-band main-line type loaded line RF MEMS phase shifter fabricated using printed circuit based MEMS technology is reported. The phase shifter provides a phase shift of 31.6/spl deg/ with a minimum insertion loss of 0.56 dB at 9 GHz for an applied DC bias voltage of 40 V. These phase shifters are suitable for monolithic integration with low-cost phased arrays on Teflon or Polyimide such as low dielectric constant substrates.     

Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology

In this paper, we present the design of a 32-b arithmetic and log unit (ALU) that allows low-power operation while supporting a design-for-test (DFT) scheme for delay-fault testability. The low-power techniques allow for 18% reduction in ALU total energy for 180-nm bulk CMOS technology with minimal performance degradation. In addition, there is a 22% reduction in standby mode leakage power and 23% lower peak current demand. In the test mode, we employ a built-in DFT scheme that can detect delay faults while reducing the test-mode automatic test equipment clock frequency.     

Inter-Device Radiation-Induced Leakages in the Bulk 180-nm CMOS Technology

Russian Microelectronics - This article deals with a study of radiation-induced leakages between n-regions of various types using test structures fabricated according to the 0.18-µm CMOS...     

The effect of mutual coupling between RF SQUID's in distributedJosephson inductance phase shifters

A brief overview of the principles behind the behavior of the recently reported distributed Josephson inductance phase shifter is given. Simulation results of a typical phase shifter are presented. A model for the mutual flux coupling between adjacent RF SQUID sections is derived and the results are used to predict the effect of the coupling on the phase shift of the device. Distortion of the output signal is related to the time variation of the dynamic inductance of the transmission line     

An Ultra-Low-Power Integrated RF Energy Harvesting System in 65-nm CMOS Process

In recent years, radio frequency (RF) energy harvesting systems have gained significant interest as inexhaustible replacements for traditional batteries in RF identification and wireless sensor network nodes. This paper presents an ultra-low-power integrated RF energy harvesting circuit in a SMIC 65-nm standard CMOS process. The presented circuit mainly consists of an impedance-matching network, a 10-stage rectifier with order-2 threshold compensation and an ultra-low-power power manager unit (PMU). The PMU consists of a voltage sensor, a voltage limiter and a capacitor-less low-dropout regulator. In the charge mode, the power consumption of the proposed energy harvesting circuit is only 97 nA, and the RF input power can be as low as \(-\)21.4 dBm \((7.24\,\upmu \hbox {W})\). In the burst mode, the device can supply a 1.0-V DC output voltage with a maximum 10-mA load current. The simulated results demonstrate that the modified RF rectifier can obtain a maximum efficiency of 12 % with a 915-MHz RF input. The circuit can operate over a temperature range from \(-40\hbox { to }125\,^{\circ }\hbox {C}\) which exceeds the achievable temperature performance of previous RF energy harvesters in standard CMOS process.     

A 5-GHz fully integrated ESD-protected low-noise amplifier in 90-nm RF CMOS

A fully integrated 5-GHz low-power ESD-protected low-noise amplifier (LNA), designed and fabricated in a 90-nm RF CMOS technology, is presented. This 9.7-mW LNA features a 13.3-dB power gain at 5.5 GHz with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB. An on-chip inductor, added as "plug-and-play," i.e., without altering the original LNA design, is used as ESD protection for the RF pins to achieve sufficient ESD protection. The LNA has an ESD protection level up to 1.4 A transmission line pulse (TLP) current, corresponding to 2-kV Human Body Model (HBM) stress. Experimental results show that only minor RF performance degradation is observed by adding the inductor as a bi-directional ESD protection device to the reference LNA.     

0.15-μm RF CMOS technology compatible with logic CMOS forlow-voltage operation

Radio Frequency (RF) CMOS is expected to replace bipolar and GaAs MESFETs in RF front-end ICs for mobile telecommunications devices in the near future. In order for the RF CMOS to be popularly used in this application, compatibility of its process for high-speed logic CMOS and low supply voltage operation are important for low fabrication cost and low power consumption. In this paper, a 0.15-μm RF CMOS technology compatible with logic CMOS for low-voltage operation is described. Because the fabrication process is the same as the high-speed logic CMOS, manufacturability of this technology is excellent. Some of the passive elements can be integrated without changing the process and others can be integrated with the addition of a few optional processes. Mixed RF and logic CMOS devices in a one-chip LSI can be realized with relatively low cost. Excellent high-frequency characteristics of small geometry silicon MOSFETs with low-power supply voltage are demonstrated. Cutoff frequency of 42 GHz of n-MOSFETs, which is almost the same level at that of general high-performance silicon bipolar transistors, was obtained. N-MOSFET's maintained enough high cutoff frequency of 32 GHz even at extremely low supply voltage of 0.5 V. Moreover, it was confirmed that degradation of minimum noise figure for deep submicron MOSFETs with 0.5 V operation is sufficiently small compared with 2.0 V operation. These excellent high-frequency characteristics of small geometry silicon MOSFETs under low-voltage operation are suitable for mobile telecommunications applications     

Phase modulation efficiency and transmission loss of silicon optical phase shifters

This paper focuses on understanding the phase efficiency and optical loss of MOS-capacitor-based silicon waveguide phase shifters. A total of nine designs have been fabricated using poly-silicon and characterized at wavelengths around 1.55 /spl mu/m. Detailed comparison of design parameters shows that scaling down the waveguide dimensions, placing the capacitor gate oxide near the center of the optical mode, and reducing the oxide thickness significantly enhance phase modulation efficiency. Our best design to date demonstrates a /spl pi/-radian phase shift with 0.8-cm device length and 3-V drive. This phase shifter has a transmission loss of 15 dB, the primary source of which is the poly-silicon regions inside the device. An improved material can reduce loss to as little as 4 dB.     

RF CMOS active inductor band pass filter with post fabrication calibration

This paper presents an active inductor bandpass filter (BPF) architecture with selectable 50 Ω driving capability and post fabrication calibration for gain, center frequency, and quality factor. The design details, and performance assessment that facilitate selecting an offline calibration mode to measure and tune post fabrication BPF performance are discussed. A specific design example for a L1/L2 channel GPS receiver is included with a BPF that is required to pass the L2 signal centered at 1.227 GHz with a gain of approximately16 dB at the center frequency, have a 3 dB bandwidth of 30 MHz (Q = 41) and rejection of the L1 signal at 1.575 GHz by at least 60 dB relative to the center frequency. A multistage active inductor BPF 90 nm CMOS design is presented that meets these specifications with typical process parameters. It is demonstrated that the post fabrication design based on typical corner analysis can be re-tuned to the desired performance for process variations across the slow and fast corners using the offline measuring and tuning control inputs.     

An analysis of high-frequency noise in RF active CMOS mixers

An analysis of high-frequency noise in RF active CMOS mixers including single-balanced and double-balanced architectures is presented. The analysis investigates the contribution of non-white gate-induced noise to the output noise power as well as the spot noise figure (NF) of the RF CMOS mixer. It accounts for the non-zero correlation between the gate-induced noise and the channel’s thermal noise. The noise contribution of the RF transconductor and the switching pair to the output noise power is studied. Experimental results verify the accuracy of the analytical model. Payam Heydari (S’98–M’00) received the B.S. and M.S. degrees in electrical engineering from the Sharif University of Technology, in 1992, 1995, respectively. He received the Ph.D. degree in electrical engineering from the University of Southern California, in 2001. During the summer of 1997, he was with Bell-Labs, Lucent Technologies, where he worked on noise analysis in deep submicrometer very large-scale integrated (VLSI) circuits. During the summer of 1998, he was with IBM T. J. Watson Research Center, Yorktown Heights, NY, where he worked on gradient-based optimization and sensitivity analysis of custom-integrated circuits. Since August 2001, he has been an Assistant Professor of Electrical Engineering at the University of California, Irvine, where his research interest is the design of high-speed analog, RF, and mixed-signal integrated circuits. Dr. Heydari has received the 2005 National Science Foundation (NSF) CAREER Award, the 2005 IEEE Circuits and Systems Society Darlington Award, the 2005 Henry Samueli School of Engineering Teaching Excellence Award, the Best Paper Award at the 2000 IEEE International Conference on Computer Design (ICCD), the 2000 Honorable Mention Award from the Department of EE-Systems at the University of Southern California, and the 2001 Technical Excellence Award in the area of Electrical Engineering from the Association of Professors and Scholars of Iranian Heritage (APSIH). He was recognized as the 2004 Outstanding Faculty at the EECS Department of the University of California, Irvine. His name was included in the 2006 Who’s Who in America. Dr. Heydari Professor Heydari has been the Associate Editor of IEEE TRANS. ON CIRCUITS AND SYSTEMS, I, since 2006. He currently serves on the Technical Program Committees of International Symposium on Low-Power Electronics and Design (ISLPED), International Symposium on Quality Electronic Design (ISQED), and the Local Arrangement Chair of the ISLPED conference. He was the Student Design Contest Judge for the DAC/ISSCC Design Contest Award in 2003, the Technical Program Committee member of the IEEE Design and Test in Europe (DATE) from 2003 to 2004, and International Symposium on Physical Design (ISPD) in 2003.     

Radiation-induced shallow trench isolation leakage in 180-nm flash memory technology

The effects of total ionizing dose (TID) irradiation on the inter-device and intra-device leakage current in a 180-nm flash memory technology are investigated. The positive oxide trapped charge in the shallow trench isolation (STI) oxide is responsible for the punch-through leakage increase and punch-through voltage decrease. Nonuniform radiation-induced oxide trapped charge distribution along the STI sidewall is introduced to analyze the radiation responses of input/output (I/O) device and high voltage (HV) device. At low dose level, the inversion near the STI corner caused by the trapped charge occurs more easily due to the lower doping concentration in this region, which gives rise to the subthreshold hump effect. With total dose level increase, more charge at deep region of the STI oxide is accumulated, predominating the intra-device off-state leakage current. It has been discussed that the STI corner scheme and substrate doping profile play important roles on influencing the device’s performance after radiation.     

Dual-band RF receiver for GPS-L1 and compass-B1 in a 55-nm CMOS

A fully integrated dual-band RF receiver with a low-IF architecture is designed and implemented for GPS-L 1 and Compass-Bl in a 55-nm CMOS process. The receiver incorporates two independent IF channels with 2 or 4 MHz bandwidth to receive dual-band signals around 1.57 GHz respectively. By implementing a flexible frequency plan, the RF front-end and frequency synthesizer are shared for the dual-band operation to save power consumption and chip area, as well as avoiding LO crosstalk. A digital automatic gain control （AGC） loop is utilized to improve the receiver＇s robustness by optimizing the conversion gain of the analog-to-digital converter （ADC）. While drawing about 20 mA per channel from a 1.2 V supply, this RF receiver achieves a minimum noise figure （NF） of about 1.8 dB, an image rejection （IMR） of more than 35 dB, a maximum voltage gain of about 122 dB, a gain dynamic range of 82 dB, and an maximum input-referred 1 dB compression point of about -36.5 dBm with an active die area of 1.5 × 1.4 mm2 for the whole chip.     

High-speed monolithically integrated silicon photoreceivers fabricated in 130-nm CMOS technology

A complementary metal-oxide-semiconductor (CMOS) monolithically integrated photoreceiver is presented. The circuit was fabricated in a 130-nm unmodified CMOS process flow on 2-/spl mu/m-thick silicon-on-insulator substrates. The receiver operated at 8 Gb/s with 2-dBm average input optical power and a bit error rate of less than 10/sup -9/. The integrated lateral p-i-n photodetector was simultaneously realized with the amplifier and had a responsivity of 0.07 A/W at 850 nm. The measured receiver sensitivities at 5, 3.125, 2, and 1 Gb/s, were -10.9, -15.4, -16.5, and -19 dBm, respectively. A 3-V single-supply operation was possible at bit rates up to 3.125 Gb/s. The transimpedance gain of the receivers was in the range 53.4-31 dB/spl Omega/. The circuit dissipated total power between 10 mW and 35 mW, depending on the design.     

The impact of BTI aging on the reliability of level shifters in nano-scale CMOS technology

On-chip level shifters are the interface between parts of an Integrated Circuit (IC) that operate in different voltage levels. For this reason, they are indispensable blocks in Multi-Vdd System-on-Chips (SoCs). In this paper, we present a comprehensive analysis of the effects of Bias Temperature Instability (BTI) aging on the delay and the power consumption of level shifters. We evaluate the standard High-to-Low/Low-to-High level shifters, as well as several recently proposed level-shifter designs, implemented using a 32 nm CMOS technology. Through SPICE simulations, we demonstrate that the delay degradation due to BTI aging varies for each level shifter design: it is 83.3% on average and it exceeds 200% after 5 years of operation for the standard Low-to-High and the NDLSs level shifters, which is 10 × higher than the BTI-induced delay degradation of standard CMOS logic cells. Similarly, we show that the examined designs can suffer from an average 38.2% additional power consumption after 5 years of operation that, however, reaches 180% for the standard level-shifter and exceeds 163% for the NDLSs design. The high susceptibility of these designs to BTI is attributed to their differential signaling structure, combined with the very low supply voltage. Moreover, we show that recently proposed level-up shifter design employing a voltage step-down technique are much more robust to BTI aging degradation. To the best of our knowledge, this is the first work addressing the effects of BTI on the the delay and power consumption of level shifters.     

Self-switching in Mach-Zehnder interferometers with SOA phase shifters

A self-switching mechanism in Mach-Zehnder interferometers (MZIs) is described. The input light signal is distributed unequally over the interferometer arms using an multimode interference (MMI) coupler. In the arms, semiconductor optical amplifiers are placed as nonlinear phase shifters. Unequal intensities yield a nonlinear phase shift. The signals from the two arms are then recombined in an output MMI coupler. If an obtained nonlinear phase shift in the arms can compensate the coupler-induced phase difference between the arms, the signals are in phase at the output port. Choosing an appropriate output coupler, 2/spl times/1 and 2/spl times/2 devices can be obtained. The 2/spl times/2 and 2/spl times/1 MZIs can be used as pattern effect compensators and 2R-regenerators or low-loss combiner circuits, respectively. An active-passive integration technique is applied in order to realize the interferometric structures. Fabrication, simulation, and characterization of these devices are presented in this letter.     

A 140-GHz fundamental mode voltage-controlled oscillator in 90-nm CMOS technology

Fundamental mode voltage-controlled oscillators in F-band (90-140GHz) were fabricated using the UMC 90-nm logic CMOS process. The maximum operating frequencies of these three oscillators are 110, 123, and 140GHz, respectively. The 140-GHz voltage controlled oscillator provides -22 to -19-dBm output power, a frequency tuning range of 1.2GHz and phase noise of -85dBc/Hz at 2-MHz offset from the carrier, while consuming 8mA from a 1.2-V supply.     

GaAs active structures with applications to microwave wideband 90° phase shifters and bandstop filters

Lumped-element second-order active filters are presented which can either be tuned to an all-pass response and then especially used in 90° phase shifters, or tuned to a bandstop response. Their structures have been chosen so that they can be easily implemented in the microwave domain. Preliminary simulations have shown that the filter having the highest-frequency capabilities results in a 90^° phase shifter operating up to the (6 GHz, 1O GHz) band, and that its centre frequency can be tuned up to 15 GHz when it is used as a bandstop filter.