Redundancy in LSI memory array

The probability of array yield for a large-scale integrated memory array is considered. The calculation assumes the random distribution of defective cells and the discretionary wiring of good rows and columns. Under the above conditions, the calculation shows that the most efficient use of redundancy is to have more row or column redundancy along the longer dimension of the array.     

A reconfigurable multifunction computing cache architecture

A considerable portion of a microprocessor chip is dedicated to cache memory. However, not all applications need all the cache storage all the time, especially the computing bandwidth-limited applications. In addition, some applications have large embedded computations with a regular structure. Such applications may be able to use additional computing resources. If the unused portion of the cache could serve these computation needs, the on-chip resources would be utilized more efficiently. This presents an opportunity to explore the reconfiguration of a part of the cache memory for computing. Thus, we propose adaptive balanced computing (ABC)-dynamic resource configuration on demand from application-between memory and computing resources. In this paper, we present a cache architecture to convert a cache into a computing unit for either of the following two structured computations: finite impulse response and discrete/inverse discrete cosine transform. In order to convert a cache memory to a function unit, we include additional logic to embed multibit output lookup tables into the cache structure. The experimental results show that the reconfigurable module improves the execution time of applications with a large number of data elements by a factor as high as 50 and 60     

Indirectly-compared cache tag memory using a shared tag in a TLB

A shared tag by which both translation lookaside buffers (TLBs) and caches can be accessed is presented. This architecture reduces the chip area of conventional cache tags and also improves the speed of cache systems. To validate the proposed architecture, the authors measured both the area and speed based on VLSI circuits     

Energy-efficient dual-port cache architecture with improved performances

Low leakage current and area-efficient dual-port cache design, which uses isolation nodes and local sense amplifiers to facilitate dual-port accesses without duplicating the bit lines for the second port, is presented. Compared with conventional hardwired dual-port cache designs, the average bit line leakage current can be reduced by 50%     

A 32 kbyte integrated cache memory

The system, circuit, layout and device levels of an integrated cache memory (ICM), which includes 32 kbyte DATA memory with typical address to HIT delay of 18 ns and address to DATA delay of 23 ns, are described. The ICM offers the largest memory size and the fastest speed ever reported in a cache memory. The device integrates a 32 kbyte DATA INSTRUCTION memory, a 34 kbit TAG memory, an 8 kbit VALID flat, a 2 kbit least recently used (LRU) flag, comparators, and CPU interface logic circuits on a chip. The inclusion of the DATA memory is crucial in improving system cycle time. The device uses several novel circuit design technologies, including a double-word-line scheme, low-noise flush clear, a low-power comparator, noise immunity, and directly testable memory design. Its newly proposed way-slice architecture increases both flexibility and expandability     

A defect-tolerant design for full-wafer memory LSI

Automatic defect-tolerant techniques are described for the realization of full-wafer LSI. These techniques, which are based on duplication redundancy, feature automatic inspection, detection, shift, and selection. Using these techniques, a 1.5-Mb frame static memory on a 4-in. silicon wafer (512/spl times/512 dot plane, 64 color) has been realized. The device has been fabricated using n-well CMOS technology with double-level polysilicon, double-level aluminum, and photolithography of 3-/spl mu/m dimensions. It provides typical access time of 520 ns and operating power of 5.8 W.     

A process-tolerant cache architecture for improved yield in nanoscale technologies

Process parameter variations are expected to be significantly high in a sub-50-nm technology regime, which can severely affect the yield, unless very conservative design techniques are employed. The parameter variations are random in nature and are expected to be more pronounced in minimum geometry transistors commonly used in memories such as SRAM. Consequently, a large number of cells in a memory are expected to be faulty due to variations in different process parameters. We analyze the impact of process variation on the different failure mechanisms in SRAM cells. We also propose a process-tolerant cache architecture suitable for high-performance memory. This technique dynamically detects and replaces faulty cells by dynamically resizing the cache. It surpasses all the contemporary fault tolerant schemes such as row/column redundancy and error-correcting code (ECC) in handling failures due to process variation. Experimental results on a 64-K direct map L1 cache show that the proposed technique can achieve 94% yield compared to its original 33% yield (standard cache) in a 45-nm predictive technology under /spl sigma//sub Vt-inter/=/spl sigma//sub Vt-intra/=30 mV.     

Flash memory architecture

Flash memories entered the nonvolatile memory scenario only a few years ago, and now these kind of memories are battling to substitute either EEPROM or EPROM. In fact, their peculiarities are becoming quite interesting in present day applications.In system updating, low power consumption, embedded algorithm for program and erase, high density, low cost packages are some of the items which are making the Flash grow in the nonvolatile memory market share.Some words must be spent in explaining what the market is asking of Flash, which are the main applications for these memories, and how their architecture is arranged.The Flash memory cell behaviour will be described, then the fundamental operations (read, program and erase) are explained and some words are used to introduce the redundancy and device testability concept.     

A fault-tolerant cache architecture based on binary set partitioning

Caches, which are comprised much of a CPU chip area and transistor counts, are reasonable targets for transient single and multiple faults induced from energetic particles. This paper presents: (1) a new fault detection scheme for tag arrays of cache memories and (2) an architectural cache to improve performance as well as dependability. In this architecture, cache space is divided into sets of different sizes and different tag lengths. Using the proposed fault detection scheme, i.e., GParity, when single and multiple errors are detected in a word, the word is rewritten by its correct data from memory and its GParity code is recomputed. The error detection scheme and the cache architecture have been evaluated using a trace driven simulation with soft error injection and SPEC 2000 applications. Moreover, reliability and mean-time-to-failure (MTTF) equations are derived and estimated. The results of GParity code are compared with those of other protection codes and memory systems without redundancies and with single parity codes. The results show that error detection improvement varies between 66% and 96% as compared with the already available single parity in microprocessors.     

Image processing on a memory array architecture

In this paper we examine the usefulness of a simple memory array architecture to several image processing tasks. This architecture, called theAccess Constrained Memory Array Architecture (ACMAA) has a linear array of processors which concurrently access distinct rows or columns of an array of memory modules. We have developed several parallel image processing algorithms for this architecture. All the algorithms presented in this paper achieve a linear speed-up over the corresponding fast sequential algorithms. This was made possible by exploiting the efficient local as well as global communication capabilities of the ACMAA.     

Fault-tolerant architecture with dynamic wavelength and bandwidth allocation scheme in WDM-EPON

This study proposes a novel cost-based fault-tolerant WDM-EPON (CFT-WDM-EPON) to provide overall protection. It only equips a backup feeder fiber to recover the system failure. Additionally, a prediction-based fair wavelength and bandwidth allocation (PFWBA) scheme is proposed to enhance the differentiated services for WDM-EPON based on dynamic wavelength allocation (DWA) and prediction-based fair excessive bandwidth reallocation (PFEBR) from our previous work. PFEBR involves an early-DBA mechanism, which improves prediction accuracy by delaying report messages of unstable traffic optical network units (ONUs), and assigns linear estimation credit to predict the arrival of traffic during waiting time. DWA can operate in coordination with an unstable degree list to allocate the available time of wavelength precisely. Simulation results show that the proposed PFWBA scheme outperforms WDM IPACT-ST and DWBA3 in terms of packet delay, jitter performance, throughput, wasted bandwidth, gain ratio of bandwidth, and packet loss.

A 6-ns cycle 256-kb cache memory and memory management unit

A 6-ns cycle, 7.7-ns access cache memory and memory management unit (CAMMU) chip has been developed. The circuit includes two 5-ns 128-kb cache memories, two 4-ns 64-entry fully associative translation lookaside buffers (TLBs), two 4-ns 64-line tag RAMs, comparators, registers, and control logic. The TLB design contains a line encoder and valid bits with flash clear. Timing control allows read, write, associative accesses, and invalid search accesses with identical timings. The two caches time-share data input and sense amplifier circuits for improved density, and they are pipelined to allow a new access to start before the previous access is complete     

MNOS LSI memory device data retention measurements and projections

The retention characteristics of an MNOS LSI memory device are interpreted from the properties of its basic MNOS transistor. A technique is developed for measuring and predicting retention properties of large quantity device lots. A production lot test method for determining the 10 000-h data retention properties of LSI memory devices is proposed. Also included in the paper are measured failure rates, identifying the retention failures and reliability for a specific LSI memory device.     

A 20 kbit associative memory LSI for artificial intelligencemachines

A 20 kb (512 words×40 b) CMOS associative-memory LSI is described. This LSI performs large-scale parallelism for highly efficient associative operations in artificial intelligence machines. Relational search, large-bit-length data treatment, and quick garbage collection are realized on the single-chip associative-memory LSI. A cell array structure has been designed in order to reduce the chip area. A newly designed simple accelerator circuit allows for high-speed search operations. The LSI is fabricated using 1.2 μm double-aluminium-layer CMOS process technology. 284000 devices have been integrated on a 5.3×7.9 mm² chip. The measured minimum cycle time and power dissipation at 10 MHz operation are 85 ns and 250 mW, respectively. The associative memory, with its highly efficient associative operation capabilities, promises to be a large step toward the development of high-performance artificial intelligence machines     

Fault-tolerant vibration control in a networked and embedded rocket fairing system

Active vibration control using piezoelectric actuators in a networked and embedded environment has been widely applied to solve the rocket fairing vibration problem. However, actuator failures may lead to performance deterioration or system dysfunction. To guarantee the desired system performance, the remaining actuators should be able to coordinate with each other to compensate for the damaging effects caused by the failed actuator in a timely manner. Further, in the networked control environment, timing issues such as sampling jitter and network-induced delay should be considered in the controller design. In this study, a timing compensation approach is implemented in an adaptive actuator failure compensation controller to maintain the fairing system performance by also considering the detrimental effects from real-time constraints. In addition, time-delay compensation in the networked control system is discussed, which is able to reduce damaging effects of network-induced delays.     

Fault-tolerant control for automated highway systems

Increasing highway traffic congestion and real estate costs that limit the building of new highways has brought about a renewed interest in an automated highway system (AHS) where the vehicle steering task (“lateral control”) and the braking/throttle tasks (“longitudinal control”) are taken over by computers to increase the throughput of existing highways. Since safety plays a key role in the development of an AHS, fault-tolerant control is vital. In this paper, we develop a robust longitudinal sliding-mode control algorithm and prove that this control algorithm is stable for a certain class of faults. In addition, we show that intervehicle spacing errors will not become amplified along the AHS in the event of a loss of lead vehicle information. The performance of the sliding-mode controller is demonstrated through a series of simulations incorporating various vehicle and AHS faults     

A new diagnostic test for operating margin problems in LSI memory

A new diagnostic test technique for operating margin problems in LSI memory has been developed that makes it possible to distinguish the failed circuit block exactly even if plural failed blocks exist. This method consists of two techniques using a newly developed time domain method (TDM). One is a technique that divides the multiple failure due to the plural failed circuit blocks into single failures. The other is a technique that distinguishes the single failure mode and then locates the failed circuit block. Moreover, a detailed diagnostic technique, combining bit mapping with the new diagnostic test technique, has also been developed. This technique enables distinguishing the failure mode more precisely. It is shown that 50 percent of the distinguished failure modes have 1-block resolution and 33 percent of them have 2-block resolution. For practical purposes, the failed circuit block can almost be distinguished with 1-block resolution by investigating the failure modes in connection with the physical layout.     

A reconfigurable multilevel parallel texture cache memory with75-GB/s parallel cache replacement bandwidth

Recently, the level of realism in PC graphics applications has been approaching that of high-end graphics workstations, necessitating a more sophisticated texture data cache memory to overcome the finite bandwidth of the AGP or PCI bus. This paper proposes a multilevel parallel texture cache memory to reduce the required data bandwidth on the AGP or PCI bus and to accelerate the operations of parallel graphics pipelines in PC graphics cards. The proposed cache memory is fabricated by 0.16-μm DRAM-based SOC technology. It is composed of four components: an 8-MB DRAM L2 cache, 8-way parallel SRAM L1 caches, pipelined texture data filters, and a serial-to-parallel loader. For high-speed parallel L1 cache data replacement, the internal bus bandwidth has been maximized up to 75 GB/s with a newly proposed hidden double data transfer scheme. In addition, the cache memory has a reconfigurable architecture in its line size for optimal caching performance in various graphics applications from three-dimensional (3-D) games to high-quality 3-D movies     

A pair of bipolar memory LSI chips for mainframe computers

A pair of bipolar memory chips has been developed. One is an LSI consisting of a 3072 bit RAM and 470 logic gates on the same chip. It has a typical address access time of 6.7 ns and a typical power dissipation of 3.9 W. It is used in the translation lookaside buffer and the buffer address array of Hitachi's M200H computer to speed up dynamic address translation and buffer storage control. The other chip is a standard 1K bit RAM with a typical address access time of 5.5 ns and a typical power dissipation of 800 mW. It is used in the buffer storage. The primary fabrication process employs oxide isolation with double layer metallization, with minimum line width-plus-spacing of 8 /spl mu/m.     

CRISP: a pipelined 32-bit microprocessor with 13-kbit of cache memory

The implementation and architecture of a 172, 163-transistor single-chip general-purpose 32-b microprocessor is described. The 16-MHz chip is fabricated using a single-metal double-poly 1.75-/spl mu/m CMOS technology and is capable of a peak execution rate of over one instruction/clock. Multiple on-chip catches, pipelining, and a one-cycle I/O protocol are utilized.