An 8-bit 50-MHz CMOS subranging A/D converter with pipelinedwide-band S/H

An 8-b video-rate subranging analog-to-digital (A/D) converter with pipelined wideband sample-and-hold (S/H) amplifiers is described. The chip architecture is based on a newly developed subranging technique that combines a digital-to-analog subconverter and a subtractor in one body. The development of a bandwidth enhancement technique for the S/H amplifier yields a wide effective resolution bandwidth using 1-μm CMOS technology. An effective resolution bandwidth of 25 MHz was achieved, as well as a small input capacitance of 1.5 pF, due to the high performance of the S/H circuit developed     

A 10-b 15-MHz CMOS recycling two-step A/D converter

A two-step recycling technique is applied to implement a 10-b CMOS analog-to-digital (A/D) converter with a video conversion rate of 15 Msample/s. In a prototype digitally corrected converter, one capacitor-array multiplying digital-to-analog converter (MDAC) is used repeatedly as a sample-and-hold (S/H) amplifier, a DAC, and a residue amplifier so that the proposed converter may obtain linearity with the capacitor-array matching. An experimental fully differential A/D converter implemented using a double-poly 1-μm CMOS technology consumes 250 mW with a 5-V single supply, and its active die area, including all digital logic and output buffers, is 1.75 mm² (2700 mil²). Because the conversion accuracy of the proposed architecture relies on a capacitor-array MDAC linearity, high-resolution CMOS A/D conversions are feasible at high frequencies if sophisticated circuit techniques are further developed. For high-speed two-phase versions, the system can be easily modified to use multiplexing and/or pipelining techniques with a separate S/H amplifier and/or two separate flash converters     

A fully parallel 10-bit A/D converter with video speed

Describes a 20 MHz conversion speed, fully parallel, analog-to-digital converter device which has been designed for use at video speed. Laser trimming technology has been adopted to improve nonlinearity errors brought about by reference voltage distortion to less than 1 mV to realize a /SUP 1///SUB 2/ LSB accuracy for the 10-bit A/D converter. The large number of comparator stages required by a parallel converter leads to a high number of components and large power dissipation. Therefore, a circuit with a reduced number of components and optimized power has been used. The process employed is a 3 /spl mu/m bipolar process, which integrates about 40000 elements onto a 9.2/spl times/9.8 mm chip.     

A 500-MHz 8-bit D/A converter

An ultrafast monolithic 8-bit DAC is designed and fabricated. To realize this DAC, a new high-speed conversion technique, referred to as the data multiplexing method, and a variation of the segmented DAC (J.A. Shoeff, 1979) for low glitch are developed. The DAC is fabricated with shallow-groove-isolated 3-/spl mu/m VLSI technology with peak f/SUB T/'s of 4.5 GHz. An experimental 8-bit DAC features a conversion rate of over 500 MHz, a full-scale settling time to 1% of 2 ns, rise/fall times of 0.6 ns, and a glitch energy of 20 ps-V without input latches or a deglitcher.     

A low glitch 10-bit 75-MHz CMOS video D/A converter

A low glitch 10-bit 75-MHz CMOS current-output video digital-to-analog Converter (DAC) for high-definition television (HDTV) applications is described. In order to achieve monotonicity and low glitch, a special segmented antisymmetric switching sequence and an innovative asymmetrical switching buffer have been used. The video DAC has been fabricated by using 0.8 μm single-poly double-metal CMOS technology. Experimental results indicated that the conversion rate is above 75 MHz, and nearly 50% of samples have differential and integral linearity errors less than 0.24 LSB and 0.6 LSB, respectively. The glitch has been reduced to be less than 3.9 pV·s and the settling time within ±0.1% of the final value is less than 13 ns. The video DAC is operated by a single 5 V power supply and dissipates 1.70 mW at 75 MHz conversion rate (140 mW in the DAC portion). The chip size of video DAC is 1.75 mm×1.2 mm (1.75 mm×0.7 mm for the DAC portion)     

A 14-bit 10-μs subranging A/D converter with S/H

A microprocessor-compatible, 14-bit, 10-μs subranging analog-to-digital converter with a sample/hold amplifier (SHA) is described. The chip architecture is based on a five-cycle subranging flash technique using both analog and digital error correction. The conversion speed is enhanced by an analog correction method, whereby redundant bit currents allow digital/analog converter updates without changing bits determined in previous cycles. The residue signal path uses simple circuitry and is highly differential. Prototype performance has been demonstrated     

An 8-bit 150-MHz CMOS A/D converter

This paper describes an 8-bit 5-stage pipelined and interleaved analog-to-digital converter that performs analog processing only by means of open-loop circuits such as differential pairs and source followers to achieve a high conversion rate. The concept of sliding interpolation is proposed to obviate the need for a large number of comparators or interstage digital-to-analog converters and residue amplifiers. The pipelining scheme incorporates distributed sampling between the stages so as to relax the linearity-speed tradeoffs in the sample-and-hold circuits, A clock edge reassignment technique is also introduced that suppresses timing mismatches in interleaved systems, and a punctured interpolation method is proposed that reduces the integral nonlinearity error with negligible speed or power penalty. Fabricated in a 0.6-μm CMOS technology, the converter achieves differential and integral nonlinearities of 0.62 and 1.24 LSB, respectively, and a signal-to-(noise+distortion) ratio of 43.7 dB at a sampling rate of 150 MHz. The circuit draws 395 mW from a 3.3-V supply and occupies an area of 1.2×1.5 mm²     

An 80-MHz 8-bit CMOS D/A converter

A high-speed 8-bit D/A converter has been fabricated in a 2-/spl mu/m CMOS technology. In order to achieve high accuracy, a current-cell matrix configuration and a switching sequence called symmetrical switching have been used. The mismatch problem of small-size transistors has been relaxed by this matrix configuration. The linearity error caused by an undesirable current distribution of the current sources has been reduced by symmetrical switching. A high-speed decoding circuit and a fast-setting current source have been developed. The experimental results show that the maximum conversion rate is 80 MHz, a typical DC integral linearity error is 0.38 LSB, a typical DC differential linearity error is 0.22 LSB, and the maximum power consumption is 145 mW. The chip size is 1.85 mm/spl times/2.05 mm.     

A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

This paper describes a 10-bit 200-MS/s CMOS parallel pipeline analog-to-digital (A/D) converter that can sample input frequencies above 200 MHz. The converter utilizes a front-end sample-and-hold (S/H) circuit and four parallel interleaved pipeline component A/D converters followed by a digital offset compensation. By optimizing for power in the architectural level, incorporating extensively parallelism and double-sampling both in the S/H circuit and the component ADCs, a power dissipation of only 280 mW from a 3.0-V supply is achieved. Implemented in a 0.5-μm CMOS process, the circuit occupies an area of 7.4 mm². The converter achieves a differential nonlinearity and integral nonlinearity of ±0.8 LSB and ±0.9 LSB, respectively, while the peak spurious-free-dynamic-range is 55 dB and the total harmonic distortion better than 46 dB at a sampling rate of 200 MS/s     

An 8-MHz CMOS subranging 8-bit A/D converter

A 8-bit subranging converter (ADC) has been realized in a 3-/spl mu/m silicon gate, double-polysilicon capacitor CMOS process. The ADC uses 31 comparators and is capable of conversion rates to 8 MHz at V/SUB DD/=5 V. Die size is 3.2/spl times/2.2 mm/SUP 2/.     

A 10-bit pipelined switched-current A/D converter

A modified RSD algorithm has been implemented in a switched-current pipelined A/D converter. The offset insensitivity of the RSD Converter reduces the effect of several nonidealities proper to current copier cells. Moreover, the benefits resulting from the large tolerances inherent to the RSD algorithm and the pipelined architecture result in an improved conversion rate. Measurements on a first prototype give an integral nonlinearity error less than 0.8 LSB for 10-bit accuracy. Power dissipation is 20 mW and silicon area is 2.5 mm² . The measured sampling rate is 550 kS/s. It is an improvement by a factor of twenty compared to known equivalent CMOS switched-current converters. It is nevertheless still well below the predicted conversion rate of 4.5 MHz, which should be obtained once this A/D converter is integrated into an analog front-end. Full compatibility with standard digital technologies makes this kind of converter attractive for low power, medium-fast converters with 10-bit accuracy     

A 10-b 300-MHz interpolated-parallel A/D converter

A monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz is described. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor V_be matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within ±0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of -59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0-mm×4.2-mm chip integrating 36 K elements, which consumes 4.0 W using a 1.0-μm-rule, 25-GHz f_t, double-polysilicon self-aligned bipolar technology     

一种低功耗10位流水线结构的CMOS A/D转换器的设计

本文设计了一种可满足视频速度应用的低电压低功耗10位流水线结构的CMOS A/D转换器.该转换器由9个低功耗运算放大器和19个比较器组成,采用1.5位/级共9级流水线结构,级间增益为2并带有数字校正逻辑.为了提高其抗噪声能力及降低二阶谐波失真,该A/D转换器采用了全差分结构.全芯片模拟结果表明,在3V工作电压下,以20MHz的速度对2MHz的输入信号进行采样时,其信噪失调比达到53dB,功率消耗为28.7mW.最后,基于0.6μm CMOS工艺得到该A/D转换器核的芯片面积为1.55mm2.     

A 10 b 50 MHz pipelined CMOS A/D converter with S/H

A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 μm CMOS technology     

A 10-b 50-MHz CMOS D/A converter with 75-Ω buffer

A 10-b 50-MHz digital-to-analog (D/A) converter for video applications that is based on a dual-ladder resistor string is presented. This approach allows the linearity requirements to be met without the need for selection or trimming. The D/A decoding scheme reduces the glitch energy, and signal-dependent switch signals reduce high-frequency distortion. The output buffer allows driving 1 V_pp to 75 Ω. The chip consumes 65 mW at maximum clock frequency and a full-swing output signal. The device is processed in a standard 1.6-μm CMOS process with a single 5-V supply voltage. The double-ladder architecture allows the requirements for small cell area and high linearity to be separated. Compensation techniques have been applied to reduce the second- and third-order distortion components; at 5-MHz signal frequency the total harmonic distortion is -53 dB     

A 10-b, 75-MHz two-stage pipelined bipolar A/D converter

A 4-b flash first quantizer is cascaded with an efficient 7-b second quantizer to attain 10-b resolution after error correction. As the second quantizer itself embodies analog subranging through folding and interpolation, its complexity is comparable with that of the first quantizer. An input track and hold preceding the first quantizer acquires dynamic signals with low distortion, and a second track and hold delays the analog residue signal to pipeline the operation of the two quantizers. This collection of components, accompanied by all necessary digital circuits for encoding and error correction is fabricated on an all-NPN 4-GHz f_T bipolar IC measuring 4×4 mm, which dissipates 800 mW from ±5-V supplies. At a 75-MEPi conversion rate, the untrimmed ADC exhibits 59 db S/(N+D) with a 6-MHz full-scale input, which diminishes by only 3 dB when the input frequency rises to 50 MHz     

一种10位100-MS/s CMOS流水折叠式A/D转换器

采用流水折叠结构设计了一种10位100-MSample/s A/D转换器。失调取消技术和电阻平均插值网络提高了转换器的线性度。级联结构放宽了折叠放大器的带宽要求,采用分布式级间跟踪保持放大器实现流水线技术来获得更高的转换精度。基于SMIC 0.18 μm CMOS工艺的测试结果如下：INL和DNL的峰值分别为0.48 LSB and 0.33 LSB。输入电压范围VP-P为1.0 V,芯片面积2.29 mm2。100 MHz采样,20 MHz输入信号下,ENOB为9.59位,SNDR为59.5 dB,SFDR为82.49 dB。1.8V电源电压下功耗仅为95 mW。     

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than ±0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-μm CMOS technology and has an active area of only 0.35 mm²     

A 10-bit 100-MS/s CMOS pipelined folding A/D converter

This paper presents a 10-bit 100-MSample/s analog-to-digital（A/D） converter with pipelined folding architecture.The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network.Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution.In SMIC 0.18μm CMOS,the A/D converter is measured as follows:the peak integral nonlinearity and differential nonlinearity are±0.48 LSB and±0.33 LSB,respectively.Input range is 1.0 V_P-P with a 2.29 mm² active area.At 20 MHz input @ 100 MHz sample clock,9.59 effective number of bits,59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved.The dissipation power is only 95 mW with a 1.8 V power supply.     

A monolithic 14-bit D/A converter

A monolithic 14-bit D/A converter using `dynamic element matching' to obtain a high accuracy and good long-term stability is described. Over a temperature range from -50/spl deg/ to 70/spl deg/C the nonlinearity is less than one-half least significant bit (/SUP 1///SUB 2/LSB). Dynamic tests show a distortion at a level of about -90 dB with respect to the maximum sinewave output. Nearly no glitches are found, so the converter can be operated without a deglitcher circuit. The chip, with a size of 3.1/spl times/3.2 mm, contains all elements needed, except the output amplifier and digital input latches.