Novel Design of a 2.5-GHz Fully Integrated CMOS Butler Matrix for Smart-Antenna Systems

This paper presents a novel design of monolithic 2.5-GHz 4 $,times,$4 Butler matrix in 0.18- $mu$m CMOS technology. To achieve a full integration of smart antenna system monolithically, the proposed Butler matrix is designed with the phase-compensated transformer-based quadrature couplers and reflection-type phase shifters. The measurements show an accurate phase distribution of ${hbox{45}}{pm}{hbox{3}}^{circ}, ~{hbox{135}} pm {hbox{4}}^{circ}, ~ -{hbox{45}} pm {hbox{3}}^{circ}, ~{hbox{and}}~ -{hbox{135}} pm {hbox{4}}^{circ}$ with amplitude imbalance less than 1.5 dB. The antenna beamforming capability is also demonstrated by integrating the Butler matrix with a 1$,times,$ 4 monopole antenna array. The generated beams are pointing to $-{hbox{45}}^{circ}, ~ -{hbox{15}}^{circ}$ , 15$^{circ}$, and 45$^{circ}$, respectively, with less than 1$^{circ}$ error, which agree very well with the predictions. This Butler matrix consumes no dc power and only occupies the chip area of 1.36 $,times,$1.47 mm$^{2}$ . To our knowledge, this is the first demonstration of the single-chip Butler matrix in CMOS technology.      

A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios

The design of a 100 kHz frequency reference based on the electron mobility in a MOS transistor is presented. The proposed low-voltage low-power circuit requires no off-chip components, making it suitable for application in wireless sensor networks (WSN). After a single-point calibration, the spread of its output frequency is less than 1.1% (3$sigma $) over the temperature range from $-{hbox{22}},^{circ}{hbox{C}}$ to 85$,^{circ}{hbox{C}}$ . Fabricated in a baseline 65$~$nm CMOS technology, the frequency reference circuit occupies 0.11$ hbox{mm}^{2}$ and draws 34 $ muhbox{A}$ from a 1.2 V supply at room temperature.      

High Heat Flux Two-Phase Cooling in Silicon Multimicrochannels

This paper presents performances of two-phase cooling of a chip at very high heat flux with refrigerant R236fa in a silicon multimicrochannel heat sink. This heat sink was composed of 134 parallel channels, 67 $mu {hbox {m}}$ wide, 680 $mu {hbox {m}}$ high, and 20 mm long, with 92-$mu {hbox {m}}$ -thick fins separating the channels. The base heat flux was varied from 3 to 255 ${hbox {W/cm}}^{2}$ , the volume flow rate from 0.18 to 0.67 l/min, and the exit vapor quality from 0 to 80%. The working pressure and saturation temperature were set at 273 kPa and 25 $^{circ}{hbox {C}}$, respectively. The present database includes 1040 local heat transfer coefficients. The base temperature of the chip could be maintained below 52 $^{circ}{hbox {C}}$ while dissipating 255 ${hbox {W/cm}}^{2}$ with 10 $~^circ{hbox {C}}$ of inlet subcooling and 90 kPa of pressure drop. A comparison of the respective performances with an extrapolation of the present results shows that two-phase cooling should be able to cool the chip 13 K lower than liquid cooling for the same pumping power at a base heat flux of 350 ${hbox {W/cm}}^{2}$.      

Compact $S$ -/$Ka$-Band CMOS Quadrature Hybrids With High Phase Balance Based on Multilayer Transformer Over-Coupling Technique

This paper presents compact CMOS quadrature hybrids by using the transformer over-coupling technique to eliminate significant phase error in the presence of low-$Q$ CMOS components. The technique includes the inductive and capacitive couplings, where the former is realized by employing a tightly inductive-coupled transformer and the latter by an additional capacitor across the transformer winding. Their phase balance effects are investigated and the design methodology is presented. The measurement results show that the designed 24-GHz CMOS quadrature hybrid has excellent phase balance within ${pm}{hbox{0.6}}^{circ}$ and amplitude balance less than ${pm} {hbox{0.3}}$ dB over a 16% fractional bandwidth with extremely compact size of 0.05 mm$^{2}$. For the 2.4-GHz hybrid monolithic microwave integrated circuit, it has measured phase balance of ${pm}{hbox{0.8}}^{circ}$ and amplitude balance of ${pm} {hbox{0.3}}$ dB over a 10% fractional bandwidth with a chip area of 0.1 mm$^{2}$ .      

Low-Threshold Strained Quantum-Well GaSb-Based Lasers Emitting in the 2.5- to 2.7-$mu$ m Wavelength Range

GaInAsSb–GaSb strained quantum-well (QW) ridge waveguide diode lasers emitting in the wavelength range from 2.51 to 2.72 $ mu{hbox {m}}$ have been grown by molecular beam epitaxy. The devices show ultralow threshold current densities of 44 $hbox{A}/{hbox {cm}}^{2}$ (${L}rightarrow infty $) for a single QW device at 2.51 $ mu{hbox {m}}$, which is the lowest reported value in continuous-wave operation near room temperature (15 $^{circ}hbox{C}$) at this wavelength. The devices have an internal loss of 3 ${hbox {cm}}^{-1}$ and a characteristic temperature of 42 K. By using broader QWs, wavelengths up to 2.72 $mu{hbox {m}}$ could be achieved.      

Active Matrix OTFT Display With Anodized Gate Dielectric

A complete process for an active-matrix (AM) organic thin-film transistor (OTFT) polymer dispersed liquid crystal (PDLC) display is presented. Evaporated pentacene is used as semiconductor. The display comprises 64$times$64 pixel, each with a pixel pitch of $({hbox{312.5}} times {hbox{312.5}}) mu{hbox{m}}^2$. The AM display is fabricated with standard photolithographic processes. Since all process temperatures are below 180$^{circ}$C the processes for the AM backplane can be easily transferred to plastic substrates like PEN or PET. Due to the thin anodically oxidized ${hbox{Al}}_2$ ${hbox{O}}_3$ gate dielectric with a thickness of 60 nm and $varepsilon_{rm r}=9$, driving voltages between 10 and 12 V are sufficient. To protect the pentacene against the PDLC, it is encapsulated with sputtered ${hbox{Ta}}_2 {hbox{O}}_5$ layer. After the passivation a field effect mobility of 0.2 ${hbox{cm}}^{2}/{hbox{V}}cdot{hbox{s}}$ is obtained for the OTFTs.      

A Temperature-to-Digital Converter Based on an Optimized Electrothermal Filter

This paper describes the design of a CMOS temperature-to-digital converter (TDC). It operates by measuring the temperature-dependent phase shift of an electrothermal filter (ETF). Compared to previous work, this TDC employs an ETF whose layout has been optimized to minimize the thermal phase spread caused by lithographic inaccuracy. To minimize electrical phase spread, the TDC's front-end consists of a wide bandwidth gain-boosted transconductor. The transconductor's output current is then digitized by a phase-domain $Sigma Delta $ modulator whose phase-summing node is realized by a chopper demodulator. To minimize the residual offset caused by the demodulator's switching action, the demodulator is located at the virtual ground nodes established by the transconductor's gain-boosting amplifiers. Measurements on 16 samples (within one batch) show that the TDC has an untrimmed inaccuracy of less than $pm hbox{0.7} ,^{circ}hbox{C}$ ($3sigma $) over the military range ($- hbox{55} ,^{circ}hbox{C}$ to 125$ ,^{circ}hbox{C}$).      

Very High-Temperature Joints Between Si and Ag–Copper Substrate Made at Low Temperature Using InAg System

We present a fluxless bonding process between silicon and Ag–copper dual-layer substrate using electroplated indium/silver solder. The nucleation mechanism of In plated over Ag layer is first investigated. It is interesting to discover that In atoms react with underlying Ag to from ${hbox {AgIn}}_{2}$ compound layer during electroplating. A novel Ag laminating technique on Cu substrates is developed. The Ag cladding functions as a strain buffer to manage the large mismatch in coefficient of thermal expansion (CTE) between semiconductors such as Si (3 ${hbox {ppm}}/^{circ}{hbox {C}}$) and Cu (17 ${hbox {ppm}}/^{circ}{hbox {C}}$) substrates. To bond Si chips to the Ag layer on copper substrates, In-based alloy (InAg) is used. A fluxless bonding process is developed between Si/Cr/Au/Ag and Cu/Ag/In/Ag. The process is performed in 50-militorr vacuum to suppress solder oxidation. No flux is used. The resulting joints consist of three distinct layers of Ag, ${hbox {Ag}}_{2}{hbox {In}}$ and Ag. Microstructure and composition of the joints are examined using scanning electron microscope (SEM) with energy dispersive X-ray spectroscopy (EDX). Bonded samples are further annealed to convert the ${hbox {Ag}}_{2}{hbox {In}}$ phase into solid solution phase (Ag). The joint has a melting temperature above 850 $^{circ}{hbox {C}}$. This technique presents our success in overcoming the very large CTE mismatch between silicon and copper. It can be applied to mounting numerous high-power silicon devices to Cu substrates for various industrial applications.      

$S$ - and $C$ -Band Ultra-Compact Phase Shifters Based on All-Pass Networks

Ultra-compact phase shifters are presented. The proposed phase-shifting circuits utilize the lumped element all-pass networks. The transition frequency of the all-pass network, which determines the size of the circuit, is set to be much higher than the operating frequency. This results in a significantly small chip size of the phase shifter. To verify this methodology, 5-bit phase shifters have been fabricated in the $S$ - and $C$ -band. The $S$ -band phase shifter, with a chip size of 1.87 mm $,times,$0.87 mm (1.63 mm $^{2}$), has achieved an insertion loss of ${hbox{6.1 dB}} pm {hbox{0.6 dB}}$ and rms phase-shift error of less than 2.8$^{circ}$ in 10% bandwidth. The $C$ -band phase shifter, with a chip size of 1.72 mm $,times,$0.81 mm (1.37 mm $^{2}$), has demonstrated an insertion loss of 5.7 dB $pm$ 0.8 dB and rms phase-shift error of less than 2.3 $^{circ}$ in 10% bandwidth.      

Interfacial Reaction Between Molten Sn-Bi Based Solders and Electroless Ni-P Coatings for Liquid Solder Interconnects

This paper reports on the interfacial reactions and lifetime of electroless Ni-P coatings in contact with molten Sn-Bi based solders. A layer of approximately 4 $mu{hbox{m}}$ thick electroless Ni-P in contact with the molten Sn-58Bi solder began to fail at 48 h at temperatures between 200 $^{circ}{hbox{C}}$ and 240 $^{circ}{hbox{C}}$ . Elemental additions to modify the solder, included 1–2wt.% of Al, Cr, Si, Zn, Ag, Au, Ru, Ti, Pt, Nb, and Cu. Of these, only Cu modified the interfacial intermetallic compound growth from ${hbox{Ni}}_{3}{hbox{Sn}}_{4}$ to $({hbox{Cu,Ni}})_{6}{hbox{Sn}}_{5}$ , resulting in significantly decreased consumption rates of the Ni-P substrate in contact with the molten solder and increasing the lifetime of the Ni-P layer to between 430 and 716 h. Micro cracks were observed in all but the thinnest Ni-P layers, allowing the solder to penetrate.      

An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops

An edge missing compensator (EMC) is proposed to approach the function of an ideal PD with $pm 2 ^{N-1} times 2pi $ linear range with $N$-bit EMC. A PLL implemented with a 9-bit EMC achieves 320 MHz frequency hopping within 10 $~mu{hbox {s}}$ logarithmically which is about 2.4 times faster than the conventional design. The reference spur of the PLL is ${-}{hbox {48.7~dBc}}$ and the phase noise is ${-}hbox{88.31~dBc/Hz}$ at 10 kHz offset with $K_{rm VCO}= -$ 2 GHz/V.      

A $Q$ -Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$mu{{hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.      

A Sub-0.2$^{circ}/$ hr Bias Drift Micromechanical Silicon Gyroscope With Automatic CMOS Mode-Matching

This paper describes a system architecture and CMOS implementation that leverages the inherently high mechanical quality factor (Q) of a MEMS gyroscope to improve performance. The proposed time domain scheme utilizes the often-ignored residual quadrature error in a gyroscope to achieve, and maintain, perfect mode-matching (i.e., $sim$0 Hz split between the high-Q drive and sense mode frequencies), as well as electronically control the sensor bandwidth. A CMOS IC and control algorithm have been interfaced with a 60 $mu{hbox {m}}$ thick silicon mode-matched tuning fork gyroscope $({rm M}^{2}mathchar"707B {rm TFG})$ to implement an angular rate sensing microsystem with a bias drift of 0.16$^{circ}/{hbox{hr}}$. The proposed technique allows microsystem reconfigurability—the sensor can be operated in a conventional low-pass mode for larger bandwidth, or in matched mode for low-noise. The maximum achieved sensor Q is 36,000 and the bandwidth of the microsensor can be varied between 1 to 10 Hz by electronic control of the mechanical frequencies. The maximum scale factor of the gyroscope is 88 ${hbox{mV}}/^{circ}/{hbox{s}}$ . The 3$~$ V IC is fabricated in a standard 0.6 $ mu{hbox {m}}$ CMOS process and consumes 6 mW of power with a die area of 2.25 ${hbox {mm}}^{2}$.      

Enhanced Hot Spot Cooling Using Bonded Superlattice Microcoolers With a Trench Structure

In this paper, we describe how to use Si/SiGe superlattice microcoolers to cool the target hot spots and how a trench structure could enhance its cooling performance. The microcooler chip is gold fusion bonded with a 65 $mu{hbox {m}}$ -thick silicon chip, where heaters are fabricated on the opposite of fusion bonding layer to simulate the hot spots. Our 3-D electrothermal simulations showed that with a trench structure, the maximum cooling and cooling power density could be doubled at hot spot region. Our experimental prototype also demonstrated a maximum cooling of ${sim 2}~^{circ} {hbox {C}}$ reduction at hot spot or a maximum cooling power density of 110 $~{hbox {W/cm}}^{2}$ with trench structure as compared with the 0.8 $^{circ}{hbox {C}}$ cooling without trench structure. This two-chip bonded configuration will allow the integration of spot coolers and ICs without impact on microelectronics processing process. It could be a potential on-chip hot spot cooling solution.      

A Floating-Gate-Based Programmable CMOS Reference

We describe a compact programmable CMOS reference, where the reference is determined by the charge difference between two floating-gate transistors, thereby making the reference insensitive to temperature and other environmental effects. Using floating-gate transistors adds programmability making a wide range of reference voltages possible with negligible long-term drift. A prototype circuit has been implemented in a 0.35-$mu{hbox {m}}$ CMOS process, and reference voltages ranging from 50 mV to 0.6 V have been achieved. We demonstrate a voltage reference programming accuracy of $pm40 muhbox{V}$ . Experimental results indicate a temperature sensitivity of approximately 53 $muhbox{V}/^{circ}hbox{C}$ for a nominal reference voltage of 0.4 V over a temperature range of $-60 ^{circ}hbox{C}$–$140 ^{circ}hbox{C}$.      

A Single-Ended Fully Integrated SiGe 77/79 GHz Receiver for Automotive Radar

A single-ended 77/79 GHz monolithic microwave integrated circuit (MMIC) receiver has been developed in SiGe HBT technology for frequency-modulated continuous-wave (FMCW) automotive radars. The single-ended receiver chip consists of the first reported SiGe 77/79 GHz single-ended cascode low noise amplifier (LNA), the improved single-ended RF double-balanced down-conversion 77/79 GHz micromixer, and the modified differential Colpitts 77/79 GHz voltage controlled oscillator (VCO). The LNA presents 20/21.7 dB gain and mixer has 13.4/7 dB gain at 77/79 GHz, and the VCO oscillates from 79 to 82 GHz before it is tuned by cutting the transmission line ladder, and it centres around 77 GHz with a tuning range of 3.8 GHz for the whole ambient temperature variation range from $- hbox{40},^{circ}{hbox{C}}$ to $+ hbox{125},^{circ}{hbox{C}}$ after we cut the lines by tungsten-carbide needles. Phase noise is $-$90 dBc/Hz@1 MHz offset. Differential output power delivered by the VCO is 5 dBm, which is an optimum level to drive the mixer. The receiver occupies 0.5 ${hbox{mm}}^{2}$ without pads and 1.26 ${hbox{mm}}^{2}$ with pads, and consumes 595 mW. The measurement of the whole receiver at 79 GHz shows 20–26 dB gain in the linear region with stable IF output signal. The input ${rm P}_{rm 1dB}$ of the receiver is $-$35 dBm.      

Electrical Properties of $hbox{Bi}_{5}hbox{Nb}_{3} hbox{O}_{15}$ Thin Film Grown on $hbox{TiN}/hbox{SiO}_{2}/ hbox{Si}$ at Room Temperature for Metal–Insulator–Metal Capacitors

Buckling was observed in $hbox{Bi}_{5}hbox{Nb}_{3}hbox{O}_{15}$ (BiNbO) films grown on $hbox{TiN}/hbox{SiO}_{2}/hbox{Si}$ at 300 $^{circ}hbox{C}$ but not in films grown at room temperature and annealed at 350 $^{circ}hbox{C}$. The 45-nm-thick films showed a high capacitance density and a low dissipation factor of 8.81 $hbox{fF}/muhbox{m}^{2}$ and 0.97% at 100 kHz, respectively, with a low leakage current density of 3.46 $hbox{nA}/hbox{cm}^{2}$ at 2 V. The quadratic and linear voltage coefficients of capacitance of this film were 846 $hbox{ppm}/hbox{V}^{2}$ and 137 ppm/V, respectively, with a low temperature coefficient of capacitance of 226 $hbox{ppm}/^{circ}hbox{C}$ at 100 kHz. This suggests that a BiNbO film grown on a $hbox{TiN}/ hbox{SiO}_{2}/hbox{Si}$ substrate is a good candidate material for high-performance metal–insulator–metal capacitors.      

$hbox{TiN/ZrO}_{2}$/Ti/Al Metal–Insulator–Metal Capacitors With Subnanometer CET Using ALD-Deposited $hbox{ZrO}_{2}$ for DRAM Applications

We provide the first report of the structural and electrical properties of $hbox{TiN/ZrO}_{2}$/Ti/Al metal–insulator–metal capacitor structures, where the $hbox{ZrO}_{2}$ thin film (7–8 nm) is deposited by ALD using the new zirconium precursor ZrD-04, also known as Bis(methylcyclopentadienyl) methoxymethyl. Measured capacitance–voltage ($C$– $V$) and current–voltage ( $I$–$V$) characteristics are reported for premetallization rapid thermal annealing (RTP) in $hbox{N}_{2}$ for 60 s at 400 $^{circ}hbox{C}$, 500 $^{circ}hbox{C}$, or 600 $^{ circ}hbox{C}$. For the RTP at 400 $^{circ}hbox{C}$ , we find very low leakage current densities on the order of nanoamperes per square centimeter at a gate voltage of 1 V and low capacitance equivalent thickness values of $sim$ 0.9 nm at a gate voltage of 0 V. The dielectric constant of $ hbox{ZrO}_{2}$ is 31 $pm$ 2 after RTP treatment at 400 $^{circ}hbox{C}$.      

Fluxless Bonding of Silicon to Ag–Copper Using In–Ag With Two UBM Designs

A fluxless process of bonding silicon to Ag-cladded copper using electroplated In–Ag multilayer structure is developed. The Ag cladding on the copper substrate is a stress buffer to deal with the large mismatch in coefficient of thermal expansion (CTE) between semiconductors such as Si (3 ${hbox {ppm}}/^{circ}{hbox {C}}$) and Cu (17 ${hbox {ppm}}/^{circ}{hbox {C}}$). To manufacture Ag on copper substrate, two techniques are developed. The first is an electroplating process to fabricate a thick Ag layer. The second technique is a novel laminating process that bonds Ag foil directly on Cu substrate. On Si chips, two underbump metallurgy (UBM) structures are designed, Si/Cr/Au and Si/Cr/Ni/Au. To produce a solder layer, Si chips are electroplated with In followed by thin Ag. The thin Ag cap layer prevents oxidation of the inner In region. To achieve a fluxless feature, the bonding process is performed in a vacuum environment (50 mtorrs) to suppress indium oxidation. Compared to bonding in air, the oxygen content is reduced by a factor of 15 200. Using Cr/Au UBM structure, the silicon chip was detached from Cu substrate. The broken interface lies between Si/Cr and ${hbox {Ag}}_{2}{hbox {In}}$ IMC on Cu substrate. Using a new UBM design of Si/Cr/Ni/Au, high-quality joints are produced that comprise of three distinct layers of ${hbox {In}}_{7}{hbox {Ni}}_{3}$, ${hbox {Ag}}_{2}{hbox {In}}$ , and Ag. Microstructure and composition of the joints are studied using a scanning electron microscope (SEM) with energy dispersive X-ray spectroscopy (EDX).      

A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS

This paper describes a reconfigurable 4-way SIMD engine fabricated in 45 nm high-k/metal-gate CMOS, targeted for on-die acceleration of vector processing in power-constrained mobile microprocessors. The SIMD accelerator is reconfigured to perform 4-way 16b$,times, $16b multiplies, 32b$,times, $32b multiply, 4-way 16b additions, 2-way 32b additions or 72b addition with single-cycle throughput and wide supply voltage range of operation (1.3 V–230 mV). A reconfigurable 2 $,times,$2 tile of signed 2's complement 16b multipliers, with conditional carry gating in the 72b sparse tree adder, dual-supplies for voltage hopping, and fine-grained power-gating enables peak energy efficiency of 494GOPS/W (measured at 300 mV, 50 $,^{circ}{hbox{C}}$) with a dense layout occupying 0.081 ${hbox {mm}}^{2}$ while achieving: (i) scalable performance up to 2.8 GHz, 278 mW measured at 1.3 V; (ii) fast single-cycle switching between any operating/idle mode; (iii) configuration-dependent power reduction of up to 41% in total power and 6.5$times$ in active leakage power; (iv) 10 $times$ standby leakage reduction during idle mode; (v) deep subthreshold operation measured at 230 mV, 8.8 MHz, 87 $mu{hbox {W}}$; and (vi) compensation for up to 3$times$ performance variation in ultra-low voltage mode.