Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding

NAND Flash memory has become the most widely used non-volatile memory technology. We focus on multi-level cell (MLC) NAND Flash memories because they have high storage density. Unfortunately MLC NAND Flash memory also has reliability problems due to narrower threshold voltage gap between logical states. Errors in these memories can be classified into data retention (DR) errors and program interference (PI) errors. DR errors are dominant if the data storage time is longer than 1 day and these errors can be reduced by refreshing the data. PI errors are dominant if the data storage time is less than 1 day and these errors can be handled by error control coding (ECC). In this paper we propose a combination of data refresh policies and low cost ECC schemes that are cognizant of application characteristics to address the errors in MLC NAND Flash memories. First, we use Gray code based encoding to reduce the error rates in the four subpages (MSB-even, LSB-even, MSB-odd, LSB-odd) of a 2-bit MLC NAND Flash memory. Next, we apply data refresh techniques where the refresh interval is a function of the program/erase (P/E) frequency of the application. We show that an appropriate choice of refresh interval and BCH based ECC scheme can minimize memory energy while satisfying the reliability constraint.     

一种用于NAND闪存的奇偶位线块编程补偿算法

为改善数据保持干扰和编程干扰对NAND闪存可靠性的影响,提出了一种新的奇偶位线块编程补偿算法。该算法利用编程干扰效应来补偿由数据保持引起的阈值漂移,修复NAND闪存因数据保持产生的误码,提高了NAND闪存的可靠性。将该算法应用于编程擦除次数为3k次的1x-nm MLC NAND闪存。实验结果表明,在数据保持时间为1年的条件下,与传统奇偶交叉编程算法相比,采用该补偿算法的NAND闪存的误码降低了93%;与读串扰恢复算法相比,采用该补偿算法的NAND闪存的误码下降了38%。     

3D NAND闪存数据保持力与初始状态依赖性研究

数据保持力是NAND闪存重要的可靠性指标,本文基于用户在使用模式下,通过设计测试方法,研究了电荷捕获型3D NAND闪存初始阈值电压-2V至3V的范围内数据保持力特性.结果表明初始状态为编程态时,可以有效降低NAND闪存高温数据保留后的误码率,特别是随着擦写次数的增加,不同初始状态下电荷捕获型3D NAND闪存数据保持力差异更加明显,结论表明闪存最适宜存放的状态为0-1V,电荷捕获型3D NAND闪存器件应避免长期处于深擦除状态.并基于不同初始状态闪存高温数据保留后的数据保持力特性不同的现象进行了建模和演示,通过设计实验验证,机理解释模型符合实验结果.该研究可为电荷捕获型3D NAND闪存器件的长期存放状态提供理论参考.     

Least Squares Based Coupling Cancelation for MLC NAND Flash Memory with a Small Number of Voltage Sensing Operations

The cell-to-cell interference (CCI) becomes the major source of distortion in NAND Flash memory as the feature size continuously decreases. As a result, removing the interference is crucial to ensure storage reliability while increasing the memory density. Along with the CCI, data retention also becomes a problem because only a small number of charges are stored at each cell. In this research, we propose a CCI cancelation algorithm that can remove or mitigate the CCI even when the data retention noise is fairly large. The coefficients for the proposed CCI canceler are adaptively found by minimizing the estimation error of the CCI, and the least squares method is used for the optimization. To reduce the number of voltage sensing operations, optimal multi-level memory sensing schemes for the proposed CCI canceler are studied. The developed algorithm is applied to both simulated and real NAND Flash memory, and it is demonstrated that the CCI canceler significantly lowers the bit error rate (BER) of multi-level cell (MLC) NAND Flash memory.     

基于FPGA的NAND控制器设计与实现

在基于NAND型固态存储系统的开发中,接口芯片直接影响储存系统的性能,为了最大限度地提高读写性能,需对NAND控制器进行自主设计。通过分析NAND Flash的接口特性和NAND控制器的组成结构,采用了状态机对NAND控制器的主逻辑以及常用编程命令进行了描述,同时运用FPGA对该状态机逻辑进行实现,并对NAND主要操作命令进行了仿真试验。试验结果表明,该设计符合NAND Flash的操作时序要求。     

NAND Flash与AT91RM9200的接口设计

以三星公司的与非型闪存(NAND Flash)器件K9K8G08U0A为例,介绍了NAND Flash的存储结构和接口信号以及AT91RM9200对NAND Flash的接口支持,分析了NAND Flash两种接口方式的优缺点,阐述了AT91RM9200对NAND Flash的初始化过程,重点以表格形式说明了接口时序的设计,最后对坏块的概念和ECC校验算法原理做了简单的介绍。NAND Flash的复用I/O接口为更新更高密度的器件提供了相同的引线,使得系统的扩展性大大提高。     

基于嵌入式USB主机的飞控数据记录器设计及实现

针对无人机飞行训练的需要,设计了一种基于嵌入式USB主机的飞行数据固态记录器。介绍了飞控数据固态数据器的工作原理、三星NAND FLASH芯片(K91G08U0M)的嵌入式文件系统和嵌入式USB主机的软件设计。实验证明,该数据记录器设计方案可行,且与传统的数据记录器相比:一方面,具有NAND FLASH存储块管理的FAT文件系统,实现对NAND FLASH数据存储的保护;另一方面,实现了USB主机接口直接与大容量设备进行文件和数据交换,极大地方便数据卸载。     

Embedded TFT nand-Type Nonvolatile Memory in Panel

A new NAND-type nonvolatile memory with a field-enhancing tip structure embedded in low-temperature polycrystalline silicon (LTPS) panel was demonstrated on a glass substrate for the first time. A thin-film transistor (TFT) metal-oxide-nitride-oxide-silicon (MONOS) device based on sequential lateral solidification crystallization with a fully depleted poly-Si channel, an oxide-nitride-oxide stack gate dielectric, and a metal gate is integrated into a NAND array. A NAND test array based on p-channel LTPS TFTs exhibits good cycling endurance and data retention properties and negligible program and read disturbance. These results strongly support the claim that this TFT-MONOS device is a promising candidate for use in embedded nonvolatile memory for system-on-panel and 3-D IC applications     

一种基于AMBA总线的 NAND FLASH控制接口电路设计

NAND FLASH采用8根I／O信号线复杂的传送控制、地址和数据信息,其控制逻辑需要专门设计。该接口设计基于ARM 7TDMI核,AMBA AHB总线结构,支持1bit ECC校验和位宽转换。接口设计中的状态机由命令字发送状态组完成对NAND FLASH命令字发送,地址发送状态组完成写地址发送,读状态组完成读操作,写状态组完成写操作。该设计已通过仿真和芯片验证测试,功能符合NAND FLASH操作规范。     

Analysis of 3D NAND technologies and comparison between charge-trap-based and floating-gate-based flash devices

NAND flash chips have been innovated from two-dimension (2D) design which is based on planar NAND cells to three-dimension (3D) design which is based on vertical NAND cells. Two types of NAND flash technologies–charge-trap (CT) and floating-gate (FG) are presented in this paper to introduce NAND flash designs in detail. The physical characteristics of CT-based and FG-based 3D NAND flashes are analyzed. Moreover, the advantages and disadvantages of these two technologies in architecture, manufacture, interference and reliability are studied and compared.     

基于FPGA和NAND Flash的嵌入式存储系统设计

为了有效解决恶劣工作环境下对体积有特殊要求的数据存储问题,设计了基于FPGA和NAND Flash的小尺寸嵌入式存储系统。系统选用FPGA为控制核心,以NAND Flash作为存储介质,采用LVDS接口存储和回放数据,通过以千兆网与计算机通信,以文件方式管理数据,并采用坏块管理和ECC技术保证数据完整性。实测表明,该系统具有高带宽、体积小等特点,同时具有实时存储、回放、加载、卸载和管理功能,并可在恶劣环境下稳定工作。     

Modeling of $V_{rm th}$ Shift in nand Flash-Memory Cell Device Considering Crosstalk and Short-Channel Effects

A threshold-voltage (V_th) shift of sub-100-nm NAND flash-memory cell transistors was modeled systematically, and the modeling was verified by comparing with the data from measurement and 3-D device simulation. The V_th shift of the NAND flash-memory cell was investigated by changing parameters such as gate length, width, drain voltage, dielectric material between cells, space between cells, lightly doped-drain depth, and adjacent-cell bias. The proposed model covers two dominant device physics: capacitance coupling effect between adjacent cells and short-channel effect. Our model showed an accurate prediction of the V_th shift of NAND flash-memory array and a good agreement with the data from simulation and measurement.     

Influence of metal gate and capping film stress on TANOS cell performance

In this work it is shown that film stress in the gate stack of TANOS NAND memories plays an important role for cell device performance and reliability. Tensile stress induced by a TiN metal gate deteriorates TANOS cell retention compared to TaN gate material. However, the erase saturation level as well as cell endurance is improved by the use of a TiN gate. This trade-off between retention and erase saturation for TANOS cells is elaborated in detail.     

针对固态硬盘应用的多通道闪存控制器实现

本文介绍一种基于MLC闪存和AHB总线的高速大容量数据控制系统的硬件实现方法,所提出的闪存控制器实现带8个8K字节缓冲器的高效率缓冲管理控制器来管理8个通道,每个通道可以连接8个闪存芯片。文中还介绍了快闪存储器存储单元的空白检查和交叉存取操作。实验结果证明该固态盘控制器的最高读速度为230．2MB／s,最高写速度为101．9MB／s．最后给出了控制器的综合结果和功耗分析,在24比特BCH纠错与一个通道的配置条件下,控制器的实现需要315K逻辑门。     

Reliability improvements in 50 nm MLC NAND flash memory using short voltage programming pulses

For the first time, an innovative programming methodology based on the use of ultra-short voltage pulses is applied in NAND flash architecture. The methodology starts from the physics of SILC dynamics and oxide damage, and relies on the trade-off between duration and amplitude of short voltage programming pulses, minimizing the creation of new traps in the tunnel oxide. The short pulses programming technique is applied on a small 50 nm NAND array designed for multibit application. Benefits of the short-pulse operation lie in that data retention and endurance which show meaningful improvements. The result is relevant for application in multibit technology, and opens the way to more aggressive cell scaling rules.     

Variability-insensitive scheme for NAND flash memory interfaces

A novel NAND flash memory interface (NFMI) scheme to cope with uncertainty due to process, voltage and temperature (PVT) variations is proposed. The new NFMI scheme introduces a signal called data valid strobe to replace the signal read enable bar, which is a read strobe in the standard NFMI protocol. Experimental results show that the proposed scheme is insensitive to PVT variations, unlike the existing NFMI scheme, and hence substantially increases system performance as well as reliability     

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

An inductive-coupling programmable bus for NAND flash memory access in solid state drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuit-layout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 ?m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.     

大容量闪存器件K9KAG08U0M与DSP的接口设计

大容量闪存器件以其体积小、容量大、易于扩展等优点在存储器领域得到广泛应用,介绍2G字节容量NANDFlash K9KAG08UOM的特点和使用方法,并以某激光惯导计算机板设计为例,重点阐述其与数字信号处理器（DSP）TMS320C6713B的硬件接口和软件设计方法。湖试和海试试验结果表明该接口设计方法可靠性高。可扩展能力强。易于编程。具有较高的实用价值。     

多通道NAND闪存控制器的硬件实现

本文提出了在一款片上系统(SOC)芯片设计中的多通道NAND闪存控制器实现方案。在对NAND闪存控制器的结构和实现方法的研究上,闪存控制器利用带两个16K字节缓冲器的高效率缓冲管理控制器来管理4个通道,每个通道可以连接4片闪存芯片。控制器内嵌16比特BCH纠错模块,支持AMBAAHB总线与MLC闪存。文中还介绍了行地址计算与快闪存储器存储单元的初始化。结果分析里给出了控制器的仿真波形、功耗分析和综合结果。在一个存储组与一个通道的配置条件下,控制器的实现只需要71K逻辑门。     

基于FPGA和FLASH ROM的图像信号发生器设计

以XC2V1500—FPGA为硬件架构,设计了一种图像信号发生器,作为自适应光学系统波前处理机的信号源,为波前处理机的调试和算法验证提供支持。系统采用大容量的NAND型FLASH存储数据,存储容量为1GB。图像数据通过USB总线预存入FLASH ROM,在FPGA控制逻辑作用下循环读出,并通过Camera Link接口输出。该Camera Link接口支持base,medium,full三种模式,输出像素时钟频率可以达到70MHz。