3D MIM电容器原子层沉积可控生长及电学性能

为提高电容器的比电容,设计了基于三维(3D)结构的金属-绝缘体-金属(MIM)电容器.采用原子层沉积(ALD)技术制备电容器功能薄膜层,通过建立3D结构原子层沉积理论模型,拟舍得到了原子层沉积过程中薄膜覆盖率与3D结构之间的依赖关系.基于该模型优化了工艺参数,制备了不同介质层厚度的电容器,并对器件进行了C-V和I-V特性测试,得到电容器击穿场强和介电常数均值分别为6.68 MV/cm和7.95.同时,制备的3D MIM电容器的比电容达到212.5 fF/μm2,相比常规平面电容器,其电容密度提高了一个数量级.且该电容器击穿场强和介电常数与薄膜厚度之间具有良好的线性关系,表明理论模型合理,实现了基于3D结构的原子层沉积薄膜可控生长.     

基于SiC基底的Y2O3/Al2O3堆栈MOS 电容的特性研究

通过在n型碳化硅(SiC)晶圆上用物理气相沉积法(PVD)和原子层沉积法(ALD)分别沉积 Y2O3介质和Al2O3，形成金属/Al2O3/Y2O3/SiC高k介质堆栈结构MOS电容，X射线光电子能谱(XPS)分析研究Al2O3/Y2O3堆栈结构氧化层介质之间以及氧化层与SiC晶圆之间的相互扩散和反应关系，研究不同金属电极MOS电容的C-V特性，Ni电极MOS电容具有良好的稳定性，对介质层的相对介电常数影响最小，Mg电极MOS电容的理想平带电压最小，同时氧化层陷阱密度最小，随着C-V测试频率的降低，氧化层电容Cox逐渐增加Al2O3/Y2O3介质层的相对介电常数逐渐增大，等效氧化层厚度(EOT)减小，平带电容电压减小。     

N_2和NH_3退火对铪铝氧栅介质C-V特性的影响

采用原子层淀积(ALD)的方法在Si(100)衬底上制备了铪铝氧(HfAlO)高介电常数介质,并研究了N2和NH3退火对于介质薄膜的影响。改变原子层淀积的工艺,制备了三组含有不同Al∶Hf原子比的铪铝氧(HfAlO)高介电常数介质。电容电压特性(C-V)测试表明,薄膜的积累电容密度随着薄膜中Al∶Hf原子比的减少而增加。实验表明,用N2和NH3对样品进行淀积后退火,可以减小等效电容厚度(CET)、降低固定正电荷密度以及减小滞回电压,从而有效地提高了介质薄膜的电学特性。     

基于原子层淀积Al2O3及多层TiN结构的MIS电容早期失效研究及工艺优化

研究采用化学气相沉积多层TiN薄膜、原子层沉积Al2O3及半球型晶粒多晶硅制备金属－绝缘体－硅结构的电容器。并研究了沉积工艺及后处理对金属－绝缘体－硅电容器的TDDB(时间相关电介质击穿)性能的影响。通过优化前驱物为Al(CH3)3和O3的原子层淀积工艺制备得到Al2O3薄膜,利用俄歇电子能谱分析没有发现碳残留,且二次离子质谱分析结果表明氢含量可降低至约9 1019atoms/cm3。电容器上极板是利用反应物为TiCL4和NH3的化学气相沉积制备的多层结构TiN, 且每层TiN薄膜经过120秒的氨气氛后处理。因多层结构TiN可获得更薄的非晶态层从而成为更好的扩散阻碍层,能有效地阻碍杂质元素扩散到Al2O3导致其介电性能退化。X射线色散谱分析结果表明,该电容器的TiN薄膜中未发现氯残留。该电容器工作电压区间的漏电流低于1 10-12 A/cm2。在与时间相关的加压加温可靠性测试条件下无早期失效现象。该新型电容器因其更低杂质成分从而有着优良的可靠性,可应用到先进的动态随机存储器技术。     

原位XPS分析Al2O3作为势垒层的Er2O3/Si结构

在超高真空条件下,通过脉冲激光沉积(PLD)技术制作了Er2O3/Al2O3/Si多层薄膜结构,原位条件下利用X射线光电子能谱(XPS)研究了Al2O3作为势垒层的Er2O3与Si界面的电子结构.XPS结果表明,Al2O3中Al的2p芯能级峰在低、高温退火前后没有变化;Er的4d芯能级峰来自于硅酸铒中的铒,并非全是本征氧化铒薄膜中的铒;衬底硅的芯能级峰在沉积Al2O 3时没有变化,说明Al2O3薄膜从沉积到退火不参与任何反应,与Si界面很稳定;在沉积Er2O3薄膜和退火过程中,有硅化物生成,表明Er2O3与Si的界面不太稳定,但随着Al2O3薄膜厚度的增加,其硅化物中硅的峰强减弱,含量减少,说明势垒层很好地起到了阻挡扩散的作用.     

PEALD制备的Al2O3薄膜在n-TOPCon太阳电池上的钝化性能

对采用等离子体增强原子层沉积(PEALD)法制备的Al2O3薄膜在n型单晶硅隧穿氧化层钝化接触(TOPCon)太阳电池正表面的钝化性能进行了研究.采用少数载流子寿命、X射线电子能谱(XPS)及J-V特性的测试分析,重点研究了 Al2O3沉积温度、薄膜厚度及薄膜形成后不同退火条件对钝化性能的影响,实现了低表面复合速率、良好钝化效果的产业化制备的Al2O3薄膜工艺.研究结果表明,在沉积温度为150℃、膜厚为5 nm、退火温度为450℃时,测试计算得出薄膜中O和Al的原子数之比为2.08,电池发射极正表面复合速率较低,达到了Al2O3钝化的最优效果,并且分析了 Al2O3薄膜的化学态和形成机理.利用其Al2O3薄膜工艺制备的n型单晶硅TOPCon太阳电池开路电压提升了 8 mV,电池的平均光电转换效率达到了 23.30％.     

原子层沉积LiPON薄膜的表面钝化研究

LiPON是一种重要的固态电解质,然而LiPON薄膜会与空气中的水和CO2发生反应产生Li2CO3,导致器件的电学性能变差.本工作利用X射线光电子能谱研究了通过原子层沉积(ALD)技术生长Al2O3薄膜来钝化LiPON薄膜,并且对比了多种方案:在ALD生长Al2O3薄膜之前对样品表面不做预处理,利用O3作为生长Al2O...     

沉积功率和退火工艺对PE-ALD氧化铝薄膜的影响

Al2O3薄膜常用于有机电子器件的稳定化封装.除了薄膜的水气渗透率特性,薄膜的表面粗糙度、润湿性和折射率等性能也会影响薄膜的最终封装效果.采用自制等离子增强原子层沉积(PE-ALD)系统在低温下成功制备了Al2O3薄膜,研究了沉积功率和退火参数对Al2O3薄膜微观形貌和性能的影响.结果表明,Al2O3薄膜的生长速率和折射率随沉积功率的增加分别呈现先增加后下降和不断增加的趋势,当沉积功率为1 800 W时,薄膜的线性生长速率达到0.27 nm/cycle,远高于传统热原子层沉积技术的沉积速率.退火处理不会改变Al2O3薄膜晶态,但改善了薄膜的表面粗糙度,降低了接触角和有机基团红外强度.得到了最佳的PE-ALD薄膜制备工艺条件,实现了对有机发光二极管器件的有效封装.     

退火处理对锑化铟MIS器件C-V特性的影响

采用原子层沉积技术制备Al2O3薄膜作为InSb材料介电层,制备了MIS器件,研究了金属化后不同退火温度对界面特性的影响.利用C-V测试表征了MIS(metal-insulator-semiconductor)器件的界面特性,结果表明Al2O3介电层引入了表面固定正电荷,200℃和300℃退火处理可有效减小慢界面态密度...     

氧氩流量比对高介电薄膜Ta_2O_5电学性能的影响

利用反应溅射的方法沉积Ta2O5高介电薄膜,研究了溅射过程中氧气与氩气的体积流量比Ψ(O2:Ar)对薄膜电学性能的影响。结果表明,制备的薄膜退火后为多晶态四方结构的β-Ta2O5。随着Ψ(O2:Ar)的增大,薄膜的沉积速率逐渐减小,积累电容逐渐增大,等效氧化层厚度逐渐减小,平带电容增大,氧化层中可动离子电荷密度逐渐减小。当Ψ(O2:Ar)=6:5时,所沉积Ta2O5薄膜的相对介电常数r最大,为38.32;当Ψ(O2:Ar)=2:5时,漏电流密度最小,仅为7.7×10–7A/cm2。     

氮化硅薄膜MIM电容器的制备与性能研究

在被釉氧化铝陶瓷基片上,采用真空电阻蒸发法和等离子体增强化学气相沉积法制备了Au/NiCr电极薄膜及氮化硅(SiNx)介质薄膜,并对薄膜进行光刻图形化,制成了Au/NiCr/SiNx/Au/NiCr结构的MIM电容器。研究了所制电容器的介电性能、介温性能和I-V特性等电学性能。结果表明:所得MIM电容器具有很低的介电损耗(1MHz时tanδ为0.00192)及很高的电压稳定性;在–55～+150℃的范围内其1MHz时的电容温度系数为258×10–6/℃;另外,其I-V特性曲线显示出较好的对称性,漏电流密度较低,可承受较高的电压。     

硅缓冲层提高选区外延生长硅基锗薄膜质量

研究了Si缓冲层对选区外延Si基Ge薄膜的晶体质量的影响。利用超高真空化学气相沉积系统,结合低温Ge缓冲层和选区外延技术,通过插入Si缓冲层,在Si/SiO_2图形衬底上选择性外延生长Ge薄膜。采用X射线衍射(XRD)、扫描电子显微镜(SEM)、原子力显微镜(AFM)表征了Ge薄膜的晶体质量和表面形貌。测试结果表明,选区外延Ge薄膜的晶体质量比无图形衬底外延得到薄膜的晶体质量要高;选区外延Ge薄膜前插入Si缓冲层得到Ge薄膜具有较低的XRD曲线半高宽以及表面粗糙度,位错密度低至5.9×10~5/cm^2,且薄膜经过高低温循环退火后,XRD曲线半高宽和位错密度进一步降低。通过插入Si缓冲层可提高选区外延Si基Ge薄膜的晶体质量,该技术有望应用于Si基光电集成。     

Low‐Temperature Growth of SiO2 Films by Plasma‐Enhanced Atomic Layer Deposition

Silicon dioxide (SiO₂) films prepared by plasma‐enhanced atomic‐layer deposition were successfully grown at temperatures of 100 to 250 °C, showing self‐limiting characteristics. The growth rate decreases with an increasing deposition temperature. The relative dielectric constants of SiO₂ films are ranged from 4.5 to 7.7 with the decrease of growth temperature. A SiO₂ film grown at 250 °C exhibits a much lower leakage current than that grown at 100°C due to its high film density and the fact that it contains deeper electron traps.     

Silicon nano-asperities: Morphological evolution and electrical properties of double-polysilicon interlayers

Polysilicon/silicon-dioxide/polysilicon structures (double polysilicon) are grown by deposition of amorphous silicon followed by thermal oxidation and a final polysilicon deposition process. Correlation between the appearance of silicon nano-structures and surface morphology formed during the amorphous silicon deposition stage and the electrical characteristics of the double poly capacitor have been investigated. It is shown that the process parameters have a pronounced effect on the morphological properties of the film surface. Nanometric size asperities form during the amorphous silicon deposition stage. The density and height distribution of these asperities were found to depend on deposition temperature. Thermal oxidation of the amorphous layer resulted in the growth of a top oxide layer and crystallization of the bottom silicon film. This process results in an overall increase of the surface roughness and a pronounced decrease in the height of the nano-asperities. By HF-etching the oxidized film, the surface of the polycrystalline silicon is exposed. Following this etching process, the surface roughness increases, whereas the density and height of the nano-asperities decrease. A correlation between the height of asperities on the bottom amorphous silicon film (as well as roughness of this film) and the breakdown voltage of the double poly was found.     

Highly robust ultrathin silicon nitride films grown atlow-temperature by microwave-excitation high-density plasma for gigascale integration

This paper focuses attention on electrical properties of ultra-thin silicon nitride films grown by radial line slot antenna high-density plasma system at a temperature of 400°C as an advanced gate dielectric film. The results show low density of interface trap and bulk charge, lower leakage current than jet vapor deposition silicon nitride and thermally grown silicon oxide with same equivalent oxide thickness. Furthermore, they represent high breakdown field intensity, almost no stress-induced leakage current, very little trap generation even in high-field stress, and excellent resistance to boron penetration and oxidation     

High-Density Through Silicon Vias for 3-D LSIs

High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have developed polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly-Si TSV technology for 3-D integration. In the poly-Si TSV formation, low-pressure chemical vapor deposition poly-Si heavily doped with phosphorus was conformally deposited into the narrow and deep trench formed in a Si substrate after the surface of Si trench was thermally oxidized. In the W/poly-Si TSV formation, tungsten was deposited into the Si trench by atomic layer deposition method after the poly-Si deposition, where poly-Si was used as a liner layer for W deposition. The 3-D microprocessor test chip, 3-D memory test chip, 3-D image sensor chip, and 3-D artificial retina chip were successfully fabricated by using poly-Si TSV.      

p-Si TFT栅绝缘层用SiN薄膜的研究

以NH3和SiH4为反应源气体,采用射频等离子体增强化学气相沉积(RF-PECVD)法在多晶硅(p-Si)衬底上沉积了一系列SiN薄膜,并利用椭圆偏振测厚仪、超高电阻-微电流计、C-V测试仪对所沉积的薄膜作了相关性能测试.系统分析了沉积温度和射频功率对SiN薄膜的相对介电常数、电学性能及界面特性的影响.分析表明,沉积温度和射频功率主要是通过影响SiN薄膜中的Si/N比影响薄膜的性能,在制备高质量的p-Si TFT栅绝缘层用SiN薄膜方面具有重要的参考价值.     

High-pressure oxidation for thin gate insulator process

High-pressure oxidation of silicon was performed at a pressure of 8.9 kg/cm²at a temperature range of 650 to 950°C. The oxidation temperature dependence of the film density, refractive index, chemical etching rate, and residual stress was measured. The film density of the oxide film was found to increase with decreasing oxidation temperature. The refractive index of the film also increased with decreasing oxidation temperature. The residual stress was found to be dependent on the oxidation temperature. The dielectric breakdown strength of the oxide film was measured by the voltage ramping method. The defect density of the oxide film calculated from the distribution of dielectric breakdown strength slightly decreased with decreasing oxidation temperature. The surface-state density of the oxide film was about 1.1 × 10¹¹cm^-2throughout the oxidation temperature range. The oxide grown on a doped polysilicon layer at a temperature of 750°C was five times as thick as the oxide simultaneously grown on the silicon substrate. The high-pressure and low-temperature oxidation was applied to the fabrication process of a device with a double polysilicon layer structure.     

Comparison of TiO2 and other dielectric coatings for buried‐contact solar cells: a review

This paper compares the optical, electronic, physical and chemical properties of dielectric thin films that are commonly used to enhance the performance of bulk silicon photovoltaic devices. The standard buried‐contact (BC) solar cell presents a particularly challenging set of criteria, requiring the dielectric film to act as: (i) an anti‐reflection (AR) coating; (ii) a film compatible with surface passivation; (iii) a mask for an electroless metal plating step; (iv) a diffusion barrier for achieving a selective emitter; (v) a film with excellent chemical resistance; (vi) a stable layer during high‐temperature processing. The dielectric coatings reviewed here include thermally grown silicon dioxide (SiO₂), silicon nitride deposited by plasma‐enhanced chemical vapour deposition (a‐ SiN_x :H) and low‐pressure chemical vapour deposition (Si₃N₄), silicon oxynitride (SiON), cerium dioxide (CeO₂), zinc sulphide (ZnS), and titanium dioxide (TiO₂). While TiO₂ dielectric coatings exhibit the best optical performance and a simple post‐deposition surface passivation sequence has been developed, they require an additional sacrificial diffusion barrier to survive the heavy groove diffusion step. A‐ SiN_x :H affords passivation through its high fixed positive charge density and large hydrogen concentration; however, it is difficult to retain these electronic benefits during lengthy high‐temperature processing. Therefore, for the BC solar cell, Si₃N₄ films would appear to be the best choice of dielectric films common in industrial use. Copyright © 2004 John Wiley & Sons, Ltd.     

High-Pressure Oxidation for Thin Gate InsuIator Process

High-pressure oxidation of silicon was performed at a pressure of 8.9 kg/cm/sup 2/ at a temperature range of 650 to 950/spl deg/C. The oxidation temperature dependence of the film density, refractive index, chemical etching rate, and residual stress was measured. The film density of the oxide film was found to increase with decreasing oxidation temperature. The refractive index of the film also increased with decreasing oxidation temperature. The residual stress was found to be dependent on the oxidation temperature. The dielectric breakdown strength of the oxide film was measured by the voltage ramping method. The defect density of the oxide film calculated from the distribution of dielectric breakdown strength slightly decreased with decreasing oxidation temperature. The surface-state density of the oxide film was about 1.1 X 10/sup 11/ cm/sup -2/ throughout the oxidation temperature range. The oxide grown on a doped polysilicon layer at a temperature of 750/spl deg/C was five times as thick as the oxide simultaneously grown on the silicon substrate. The high-pressure and low-temperature oxidation was applied to the fabrication process of a device with a double polysilicon layer structure.