国外动态

日将播放数字式立体电视节目日本三洋电机公司和日本电视广播网近日宣布，他们已研制成功一种数字式立体电视广播系统。这种系统的特点是，使用数字信号播出由立体摄像机摄制的影像，用立体电视机接收，用专用眼镜观看。日本电视广播网今夏将试播立体电视节目。这种立体广播将供左眼看和供右眼看的图像分别播出，电视接收到之后以一百二十分之一秒的间隔交错映出两种画面，当戴上专用眼镜观看时，人物就像飞出电视机一样，立体感很强。（肖雨摘）据《莫斯科共青团员报》报道，一种为俄罗斯和西欧国家设计的新型电视──蜂窝式电视，将于年底…     

一种机扫超视距侦测系统测向模型及其解算方法

针对机械扫描方式工作的超视距侦测系统,由于受到收发双发天线方向图和天线扫描的调制,存在测向模糊的问题,建立一种机械扫描超视距侦测系统测向模型,利用窗口截获理论分析其截获和测向特性,给出模型的解算方法,并提出一种变扫描周期进行解模糊的测向策略,最后通过仿真验证了方法的有效性。     

一体化侦测阵列天线技术研究

本文在一种宽带偶极子单元天线的基础上,对由单元天线组成的常规侦测阵列进行改进设计,通过组阵方式实现了一种新颖的一体化侦测阵列天线。文章运用HFSS 电磁仿真软件结合干涉仪测向原理分别对两种侦测阵列进行性能比较。结果表明,新颖的一体化阵列实现了既包括常规侦测阵列的功能,又利用其组阵后的波束形成及其控制灵活等特 点,较单元天线实现更高的天线增益,这对提高系统的灵敏度和多功能性有很大帮助,比较适合应用于宽带一体化侦测系统。     

反交错滤镜YADIF及PP li的技术实现分析

反交错滤镜是一种视频图像编码处理技术,用于解决从隔行扫描到逐行扫描的转换后图像出现的拖尾及锯齿等画面质量问题。本文分析了两种采用不同技术原理实现的反交错滤镜YADIF和PP li的具体实现方式,并提出了一种综合使用两种滤镜获得更好的反交错处理画面效果的方法。     

电视史话(连载九)

十七、影片与影片录象 1.影片自从最早的电视公开表演以来,影片一直是重要的节目来源。人们注意到,1936年BBC表演机械扫描电视广播时,就是独特地使用影片在摄影棚中拍摄节目的。人们也注意到,早     

感知无线电中的高效频谱侦测方案

感知无线电是一种能有效提高频谱利用率的先进技术,他能在主用户没有使用频谱的时候发现并使用"频谱空洞".近来有研究结果表明,在衰落和阴影效应影响下频谱侦测的结果会有大幅度下降.为了削弱衰落和阴影效应的影响联合侦测诞生了,传统的联合侦测方式在每个用户所受衰落不同的情况下不能有效的工作.文章提出一种加权联合侦测来提高联合侦测性能.由大量分析和仿真结果可以表明加权联合侦测能大幅度提高侦测性能.     

基于相似性度量的面向对象程序方法级克隆侦测

代码克隆侦测对于代码重构以及可复用资产抽取都有着重要的作用.现有的克隆侦测方法及工具以相似代码片段为单位,给进一步的克隆分析以及代码重构带来困难.针对这一问题,本文提出了一种基于相似性度量的面向对象程序方法级克隆侦测方法,即以方法为单位进行克隆代码侦测.该方法综合利用代码中的注释、签名以及语法相似性来度量方法代码之间的克隆程度.在此基础上合并子类中的相似方法并提取到父类中,从而实现进一步的代码重构.本文通过对JDK包中代码的实验分析验证了本文所提出方法的有效性.初步的实验结果表明,本文方法能够准确、有效地辅助开发者实现方法级的克隆代码侦测.     

IDT发表搭载新一代HQV视频技术的Vida处理器

IDT发表该公司好莱坞高质量视频标准（Hollywood Quality Video;HQV）视频处理产品线的最新芯片。 Vida处理器运用四场动态适应解交错（four-field motion adaptive de-interlacing）、多重节奏追踪、扩充的12位色彩处理,以及细节强化,提供更细腻且高质量的影像。其结果能够将标准分辨率的影像来源转变成高画质．而高画质影像则看起来更加细致。此外．该芯片也能提供高压缩视频的实时净化．减少低画质影像来源常见的方块影像和蚊影噪声等影像压缩瑕疵。     

一种新颖的晶体型波长分插解复用器结构设计

提出了一种新颖的晶体型波长分插解复用器（Interleaver) 结构，该结构全部采用双折射晶体来实现，具有PMD补偿、PDL低和温漂小等特点，同时具有很小的外观尺寸。加工及装配误差分析表明这种结构的Interleaver完全可以满足ITU－T 100 GHz波长间隔的解复用。     

新品初览

电视骇客卡TV@nywhere Master采用CONEXANT顶级全功能影音译码处理器,更加入了业界最新的Siiicon Tuner电视讯号芯片,提供全方位的电视观看享受与节目录制编辑功能。 微星电视骇客卡就像一台录像机,不仅可以支持其它影像来源、输入端子像电视讯号、摄影机及其它AV设备,还可以用MPEG1或MPEG2     

基于ERRTP的网络摄像机系统设计

提出一种新的具有抗分组丢失能力的网络摄像机设计方案,该方案以DM643芯片为核心处理器,采用ERRTP载荷结构保证H.264视频通信的传输质量,该结构支持对H.264视频码流的TN码不等保护,保证时延在实时视频通信允许的范围内.实验结果表明,本系统没有过多增加信道负担和运算复杂度,传输效率较之RTP基本不变,且在高丢包率下恢复视频质量的峰值信噪比较单一TN码保护提高了1～7 dB.满足分组丢失环境下实时视频通信的QoS要求.     

一种新的实时通用视频处理器的设计

实时通用视频处理器是图像处理系统的核心，协调实时通用视频处理器的Ａ／Ｄ，ＤＳＰ，Ｄ／Ａ三者的时序，使ＤＳＰ有更多的时间处理图像数据是设计的关键。在分析国内外文献中提出了逆程和正程工作方式下的视频处理器原理和结构后，又提出一种新的全程工作方式的视频处理器设计方案，并对三种工作方式的电路及工作原理进行了比较。     

A Very High Throughput Deblocking Filter for H.264/AVC

This paper presents a novel hardware architecture for the real-time high-throughput implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard. A parallel filtering order of six units is proposed according to the H.264/AVC standard. With a parallel filtering order (fully compliant with H.264/AVC) and a dedicated data arrangement in local memory banks, the proposed architecture can process filtering operations for one macroblock with less filtering cycles than previously proposed approaches. Whereas, filtering efficiency is improved due to a novel computation scheduling and a dedicated architecture composed of six filtering cores. It can be used either into the decoder or the encoder as a hardware accelerator for the processor or can be embedded into a full-hardware codec. This developed Intellectual Property block-based on the proposed architecture supports multiple and high definition processing flows in real time. While working at clock frequency of 150 MHz, synthesized under 65 nm low power and low voltage CMOS standard cell technology, it easily meets the throughput requirements for 4 k video at 30 fps of all the levels in H.264/AVC video coding standard and consumes 25.08 Kgates.     

DVFS-aware motion estimation design scheme based on bandwidth–rate–distortion optimization in application processor systems

In this paper, a novel dynamic voltage–frequency scaling-aware (DVFS-aware) bandwidth- efficient motion estimation (ME) scheme is presented for mobile application processor (AP) systems. Under volatile operating performance conditions due to the power management mechanism, we model the coding bandwidth (BW) and coding performance for the video processor as a convex function of the working frequency. In this paper, we present a bandwidth–rate–distortion (B–R–D) optimized framework that will guarantee the smallest possible rate–distortion cost among coding BW constraints applied in video coding design. By formulating the coding bandwidth-constrained ME problem as an optimization problem, known convex optimization theory can be applied to yield optimal resource-constrained compression. Using varied CIF (352×288)- and HP (1280×720)-sized video sequences with different motion activities over our proposed DVFS-aware video coding approach, the excellent results in terms of coding performance and coding bandwidth savings are obtained. With negligible quality loss, the proposed scheme under coding BW constraints achieves 45–65% coding BW usage reduction over HD-sized 30 frame/s video coding.     

实时H.263+视频编码器的DSP实现

在多媒体处理芯片TM-1300的开发平台上,快速实现了H.263 视频编码器。首先,根据H.263 编码算法要求,介绍TM-1300适合视频通信开发的特点及其开发环境;然后,将编码算法移植到TM-1300平台并进行大量的优化,其中,重点讨论了位移估值的优化算法。由实验结果可知,使用本文给出的优化算法,可以在TM-1300上快速实现H.263 编码器,满足视频实时编解码的要求,且已应用于实际视频通信产品中。     

A Novel Penalty Controllable Dynamic Voltage Scaling Scheme for Mobile Multimedia Applications

Multimedia decoding is one of the key parts of many popular mobile multimedia applications, such as video telephony, streaming, and video playback. Since the multimedia decoding consumes a significant amount of energy on processors, it is crucial to lower the power consumption and prolong the battery life. In this paper, the statistical analysis of more than 600 processor load trace files is first presented. From the analysis, we found that it is feasible to predict the processor load of multimedia applications accurately using a low order linear time series model if the load is sampled using the feature period, which is obtained with fast Fourier transformation. Based on the analysis, we propose a novel interval-based DVS scheme to achieve penalty controllable energy reduction. The DVS scheme does not need any task profile or involvement of application program, and it is compatible with the service model of general purpose mobile operating systems. In addition, the proposed DVS scheme can handle the nonstationary behavior using an efficient online change detector, and important parameters, such as coefficients of the linear time series model, are estimated on the fly. More importantly, the proposed scheme can keep the overscaling rate (OSR) around a certain predefined value. Since the OSR has a simple and stable relationship with the deadline miss rate (DMR), the penalty incurred by DVS is effectively controlled. Experimental results show that the proposed DVS scheme achieves a much smaller prediction error than previous approaches and achieves a significant processor energy reduction with adjustable and controlled penalty     

A Unified FPGA-Based System Architecture for 2-D Discrete Wavelet Transform

This paper presents a novel unified and programmable 2-D Discrete Wavelet Transform (DWT) system architecture, which was implemented using a Field Programmable Gate Array (FPGA)-based Nios II soft-core processor working in combination with custom hardware accelerators generated through high-level synthesis. The proposed system architecture, synthesized on an Altera DE3 Stratix III FPGA board, was developed through an iterative design space exploration methodology using Altera’s C2H compiler. Experimental results show that the proposed system architecture is capable of real-time video processing performance for grayscale image resolutions of up to 1920?×?1080 (1080p) when ran on the Altera DE3 board, and it outperforms the existing 2-D DWT architecture implementations known in literature by a considerable margin in terms of throughput. While the proposed 2-D DWT system architecture satisfies real-time performance constraints, it can also perform both forward and inverse DWT, support a number of popular DWT filters used for image and video compression and provide architecture programmability in terms of number of levels of decomposition as well as image width and height. Based from the design principles used to implement the proposed 2-D DWT system architecture, a system design guideline can be formulated for SOC designs which plan to incorporate dedicated 2-D DWT hardware acceleration.     

基于H.264编码算法的高速CCD视频压缩系统设计

为了满足航空大面阵CCD相机视频数据高速、实时传输和存储的要求,本文设计了一种基于H.264视频编码算法的压缩系统。整个压缩系统分为CCD前端、视频压缩、视频显示、视频压缩码流存储以及压缩分析单元,视频压缩单元采用高性能视频专用DSP处理器TMS320DM642,软件平台采用在CCS3.1上使用C语言实现H.264压缩算法。为了使压缩算法高效快速的运行,本文使用了DSP/BIOS资源来管理软硬件工作。 为了高速交互数据,采用了EDMA高速搬运数据策略,进而保证了数据实时传输的需要。实验结果表明,本文提出的压缩系统可以稳定正常的工作,具有良好压缩性能,在压缩比40:1~10:1范围内,平均信噪比高于35dB,满足了航空CCD相机应用的需求。     

DM642开发与应用

视频处理机是基于TI的DSPTM320DM642芯片设计,高速信息处理性能,计算能力达4Gips使视频处理达到理想效果,可以做实时的视频采集,实现复杂的音视频压缩算法,带有以太网口,可以通过网络传输数据。主要应用于网络视频监控和其它复杂图象处理的高速DsP应用。     

一种基于数字信号处理器的媒体处理器结构及设计

设计了一种针对图像、音频、视频等多媒体数据的处理新型结构的媒体处理器。该媒体处理器由一个通用数字信号处理器及多媒体协处理器构成,其指令集包含了通用的数字信号处理指令及扩展的多媒体处理指令。多媒体协处理器中包含了多个专用于多媒体处理的功能模块,可以加速多媒体处理的进行。该媒体处理器具有强大的多媒体处理能力,可实现对JPEG压缩图像、MP3音频流或MPEG2的MP@ML级别的压缩视频流的实时解码。