A new approach to simulating n-MOSFET gate current degradation byincluding hot-electron induced oxide damage

A new gate current model which considers the hot-electron induced oxide damage in n-MOSFET's was developed for the first time. The spatial distributions of oxide damage, including the interface state (N_it ) and oxide trapped charge (Q_ox) were characterized by using an improved gated-diode current measurement technique. A numerical model feasible for accurately simulating gate current degradation due to the stress generated N_it and Q_ox has thus been proposed. Furthermore, the individual contributions of N_it and Q_ox to the degradation of gate current can thus be calculated separately using these oxide damage. For devices stressed under maximum gate current biases, it was found that the interface state will degrade the gate current more seriously than that of the oxide trapped charge. In other words, the interface states will dominate the gate current degradation under I_G,max. Good agreement of the simulated gate current has been achieved by comparing with the measured data for pre-stressed and post-stressed devices. Finally, the proposed degradation model is not only useful for predicting the gate current after the hot-electron stress, but also provides a monitor that is superior to substrate current for submicron device reliability applications, in particular for EPROM and flash EEPROM devices     

A unified approach to profiling the lateral distributions of bothoxide charge and interface states in n-MOSFET's under various biasstress conditions

A new and accurate technique that allows the simultaneous determination of the spatial distributions of both interface states (N _it) and oxide charge (Q_ox) will be presented. The gated-diode current measurement in combination with the gate-induced drain leakage (GIDL) current were performed to monitor the generation of both N_it and Q_ox in n-MOSFET's. A special detrapping technique and simple calculations have been developed, from which the spatial distributions of both N_it and Q_ox under various bias stress conditions, such as the hot-electron stress (I_G,max), I_B,max, and hot-hole stresses, can be determined. The calculation of gated-diode current by incorporating the extracted profiles of N_it and Q_ox has been justified from numerical simulation. Results show very good agreement with the experimental results. The extracted interface damages for hot-electron and hot-hole stresses have very important applications for the study of hot-carrier reliability issues, in particular, on the design of flash EPROM, E²PROM cells since the above stress conditions, such as the I_G,max and hot-hole stress, are the major operating conditions for device programming and erasing, respectively     

Simplified 0.35-μm flash EEPROM process using high-temperatureoxide (HTO) deposited by LPCVD as interpoly dielectrics and peripheraltransistors gate oxide

A simplified flash EEPROM process was developed using high-temperature LPCVD oxide both as flash cells interpoly dielectrics and as peripheral transistors gate oxide (decoding logic). An O₂ anneal at 850°C lowers charge trapping and interface trap density induced by Fowler-Nordheim injection. However, electron trapping remains slightly higher than with dry thermal oxide. Similar memory charge loss and write-erase endurance are obtained as for ONO-insulated cells. HTO thus proves to have the required quality and reliability to be used in flash EEPROMs     

A new charge-pumping technique for profiling the interface-statesand oxide-trapped charges in MOSFETs

A new charge-pumping method has been developed to characterize the hot-carrier induced local damage. By holding the rising and falling slopes of the gate pulse constant and then varying the high-level (V_GH) and base-level (V_GL) voltages, the lateral distribution of interface-states (N_it(x)) and oxide-trapped charges (Q_ox(x)) can be profiled. The experimental results show that during extracting Q_ox(x) after hot-carrier stress, a contradictory result occurs between the extraction methods by varing the high-level (V_GH) and base-level (V_GL) voltages. As a result, some modifications are made to eliminate the perturbation induced by the generated interface-states after hot-carrier stress for extracting Q_ox(x)     

A new observation of band-to-band tunneling induced hot-carrierstress using charge-pumping technique [MOSFETs]

The lateral distributions of interface-states (N_it) and oxide-trapped charges (Q_ox) generated by band-to-band tunneling (BTBT) induced hot-carrier stress are analyzed by the new charge-pumping method. It is shown that the interface-states and oxide-trapped charges should originate from different types of carriers due to the separation of the locations of their peak values. The further evidence of the measured distribution of the interface-states in the band-gap shows that the carriers travelling toward the gate edge would be the dominant carrier for the generation of interface-states while the carriers travelling away from the gate edge will generate oxide-trapped charges through the help of the vertical electric field. These results should be very useful for the reliability analysis of flash memories     

Device characteristics of 0.35 μm P-channel DINOR flash memoryusing band-to-band tunneling-induced hot electron (BBHE)programming

The P-channel DINOR flash memory, which uses the band-to-band tunneling induced hot electron (BBHE) program method having the advantages of high scalability, high efficiency, and high oxide reliability, was fabricated by 0.35-μm-rule CMOS process and was investigated in detail. An ultra-high programming throughput of less than 8 ns/byte (=4 μs/512 byte) and a low current consumption of less than 250 μA were achieved by utilizing 512-byte parallel programming. Furthermore, we investigated its endurance characteristics up to 10⁶ program/erase cycles, and window narrowing and G_m degradation were found to be very small even after 10⁶ cycles. It is thought that the BBHE injection point contributes to the G _m stability and the oxide-damage-reduced operation contributes to the good window narrowing characteristics. The P-channel DINOR flash memory realizing high programming throughput with low power consumption is one of the strongest candidates for the next generation of high-performance, low-voltage flash memories     

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOStechnologies

In this paper, the performance and reliability characteristics of the 0.35 μm/0.25 μm High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 μm CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 μs) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125°C. Furthermore, the cell has been scaled to a 0.25 μm version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V     

P-Type Floating Gate for Retention and P/E Window Improvement of Flash Memory Devices

A flash memory with a lightly doped p-type floating gate is proposed, which improves charge retention and programming/erase (P/E) V_th window. Improvement in P/E window is enhanced for cells with smaller capacitance coupling ratio, which is important for future scaled flash memory cells. Both device simulation and experimental verification are presented.     

低电场应力下闪速存储器的退化特性

基于负栅源边擦除的闪速存储器存储单元,研究了形成应力诱生漏电流的三种导电机制,同时采用新的实验方法对引起瞬态和稳态电流的电压漂移量进行了测量.并利用电容耦合效应模型对闪速存储器存储单元的可靠性进行了研究,结果表明,在低电场应力下,其可靠性问题主要由载流子在氧化层里充放电引起.     

Impact of floating gate dry etching on erase characteristics in NOR flash memory

We report the effects of plasma process-induced damage during floating gate (FG) dry-etching process on the erase characteristics of NOR flash cells. As compared to flash cells processed in a stable plasma condition, it is found that flash cells processed in the nonoptimized ambient show significantly degraded erase characteristics under a negative gate Fowler-Nordheim (FN) bias, exhibiting a fast-erasing bit in the distribution of erased bits. However, little differences are found in their tunneling characteristics under a positive gate biasing. The gate bias polarity dependence of FN tunneling indicates that positive charges are created near the poly-Si/SiO/sub 2/ interface during the FG dry-etching, prior to the backend processes such as metal- or via-etch.     

New programming and erasing schemes for p-channel flash memory

In this work, a new programming scheme using a forward substrate bias during BBHE injection and a two-step erasing scheme has been suggested to improve the performances of p-channel flash memory. It has been found that applying a forward substrate bias increases the electron injection efficiency and improves the cell's endurance characteristics. The two-step erasing scheme, where a channel erase cycle is added after the source erase operation, is found to reduce the gate current degradation and also to improve the cell's endurance characteristics     

A new write/erase method to improve the read disturbcharacteristics based on the decay phenomena of stress leakage currentfor flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10⁶ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond     

Highly Reliable Multilevel and 2-bit/cell Operation of Wrapped Select Gate (WSG) SONOS Memory

In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multilevel and 2-bit/cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mus/5 ms) and low programming current (3.5 muA) for our WSG SONOS by a source-side injection. Besides the excellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (>150degC) and good endurance (>10⁴) are also presented. This novel WSG-SONOS memory with a multilevel and 2-bit/cell operation can be used in future high-density and high-performance memory application     

Device scaling effects on hot-carrier induced interface andoxide-trapped charge distributions in MOSFETs

The influence of channel length and oxide thickness on the hot-carrier induced interface (N_it) and oxide (N_ot) trap profiles is studied in n-channel LDD MOSFET's using a novel charge pumping (CP) technique. The technique directly provides separate N_it and N_ot profiles without using simulation, iteration or neutralization, and has better immunity from measurement noise by avoiding numerical differentiation of data. The N_it and N_ot profiles obtained under a variety of stress conditions show well-defined trends with the variation in device dimensions. The N_it generation has been found to be the dominant damage mode for devices having thinner oxides and shorter channel lengths. Both the peak and spread of the N_it profiles have been found to affect the transconductance degradation, observed over different channel lengths and oxide thicknesses. Results are presented which provide useful insight into the effect of device scaling on the hot-carrier degradation process     

Read-disturb and endurance of SSI-flash E2PROM devicesat high operating temperatures

The high-temperature (T) reliability behavior of merged-transistor source side injection (SSI) flash nonvolatile memory (NVM) devices is evaluated in terms of endurance and disturb effects related to stress induced leakage current (SILC) and correlated with the high-T behavior (generation, anneal) of oxide traps. As compared to room-T, program/erase (P/E) cycling at 150°C results in an improved endurance due to an enhanced charge emission. The impact of the operating temperature on SILC-related disturb effects, on the other hand, depends on two combined effects in memory cells where large local charge trap-up influences the threshold voltage, V_t: 1) the T-enhanced trap generation and 2) the T-enhanced emission of trapped charge which influences the disturb field. In the case of the HIMOS-cell-which is discussed here-long-term nonvolatility can still be guaranteed at 150°C. Finally, bake tests at higher temperatures (250-300°C) have been performed in order to evaluate the persistence of the generated damage. It is found that bulk oxide traps are not cured by the bake and, therefore, no long-term relief of SILC-related disturb effects is expected at 150°C     

An efficient method for characterizing time-evolutional interfacestate and its correlation with the device degradation in LDD n-MOSFETs

A new characterization method is proposed to study the relationship between the hot-carrier-induced interface state N_it (x) and the device drain current degradation of submicron LDD n-MOSFETs. In this method, by making use of the conventional charge pumping measurement in combination with the power-law dependence of interface damages on stress time, the spatial distribution N_it(x) and the effective damaged length L_dam can be easily extracted. The time evolution of the interface state generation and its correlation with the device degradation can then be well explained. It is worthwhile to note that this newly developed method requires no repetitive charge pumping measurements, and hence avoids he likely imposition of re-stress on tested devices. By combining the characterized L_dam and N_it quantitatively, the results show that the damage at L_dam and V_GS≈V _DS/2 is most highly localized among various stress biases, which can explain why the generated interface states will dominate the device drain current degradation at this bias after long-term operating conditions     

Effects of erase source bias on Flash EPROM device reliability

This paper is concerned with the effects of the source bias during the erase operation on the reliability of Flash EPROM devices. It will be shown that positive charge in the tunnel oxide, mostly generated by the erase operation, is a major cause of the unintentional charge loss/gain mechanisms that disturb the data content of the memory cell. The effects of the erase source bias are evaluated in the context of the positive oxide charge generation and the resulting enhancement of the gate current that causes the data loss. An optimal source bias during erase, around 2 V for our samples, is shown to cause the least positive oxide charge. A model based on the band-to-band tunneling-induced hole generation in Si and subsequent hole injection during the erase operation is presented and discussed     

Determination of trapped oxide charge in flash-type EEPROMs with heavily oxynitrided tunnel oxide films

Flash-type EEPROMs with rapid thermal oxide (RTO) and rapid thermal oxynitrided oxide (RTONO) films are fabricated. The oxide trap density in the program and erase (P/E) cycles is determined by the shifts in I-V curves for the source-gate and drain-gate edges, respectively. The RTONO flash cell shows a drastically reduced trap density of less than 3*10/sup 12//cm/sup 2/ after 10/sup 4/ P/E cycles. This value is one order smaller than that of the RTO flash cell. This smaller oxide trap density originates in the stable Si-N bond formation near the SiO/sub 2/-Si interface, and results in lower threshold voltage shifts.<>     

Direct lateral profiling of hot-carrier-induced oxide charge andinterface traps in thin gate MOSFET's

A simple charge pumping method has been developed to measure the localized hot-carrier damage in scaled thin-gate MOSFET's. Lateral distributions of both interface traps and oxide charge can be derived directly from experimental charge pumping results without numerical simulation. By the use of this method, we have studied the erase-induced hot-carrier damage in flash EPROM devices, including the lateral distributions of both oxide charge (trapped holes) and interface traps. We discovered the following: the damage is confined within the source diffusion region with a rather wide distribution; the erase-induced oxide charge density is orders of magnitude more than erase-induced interface traps; both the peak density and width of the damage depend strongly on the junction bias during the erase operation. These results should be very useful for the reliability modeling and future device design of flash EPROM's