金属诱导晶化法制备多晶硅薄膜研究进展

本文介绍了金属诱导晶化非晶态硅制备多晶硅薄膜的新方法，综述了制备金属/非晶态硅复合薄膜的各种方法与晶化结果，着重介绍了金属低温诱导的机理及其在器件应用方面的可行性。     

铝诱导晶化法低温制备多晶硅薄膜

为了满足在普通玻璃衬底上制备多晶硅薄膜晶体管有源矩阵液晶显示器,低温（＜６００℃）制备高质量多晶硅薄膜已成为研究热点．本文研究了一种低温制备多晶硅薄膜的新工艺：金属诱导非晶硅薄膜低温晶化法．在非晶硅薄膜上蒸镀金属铝薄膜,并光刻形成铝膜图形,而后于氮气保护中退火．利用光学显微镜和拉曼光谱等测试方法,研究了Ａｌ诱导下非晶硅薄膜的晶化过程,结果表明;在５６０℃退火６ｈ后;铝膜下的非晶硅已完全晶化,确定了所制备的是多晶硅薄膜．初步探讨了非晶硅薄膜金属诱导横向晶化机理．     

铝诱导晶化制备多晶硅薄膜研究进展

铝诱导晶化(AIC)技术制备多晶硅(Poly-Si)薄膜因处理温度低、退火时间短,且所制备的薄膜晶粒尺寸大而受到广泛关注.阐述了AIC法制备Poly-Si薄膜的交换机制,着重讨论了AIC过程中工艺条件对制备Poly-Si薄膜质量的影响,简单介绍了AIC制备的Poly-Si薄膜在太阳电池器件方面的研究现状,并指出提高AIC法制备的Poly-Si薄膜籽晶层及外延层质量以改善薄膜电池性能是今后的重点研究方向.     

金属诱导晶化法制备多晶硅薄膜研究进展

本文介绍了金属诱导晶化非晶态硅制备多晶硅薄膜的新方法 ,综述了制备金属 /非晶态硅复合薄膜的各种方法与晶化结果 ,着重介绍了金属低温诱导的机理及其在器件应用方面的可行性     

金属诱导晶化的实时电阻测量与监控

采用实时电阻测量方法实现了金属镍诱导晶化制备多晶硅薄膜的实时监控,实验中使用了两种样品,一种采用电场增强侧向晶化;另一种采用金属诱导侧向晶化.结果表明薄膜电阻值在高温下随晶化时间呈指数衰减,且具有很强的温度依赖关系.采用晶粒边界势垒模型解释了阻值衰减行为,分析计算了两种样品的阻值衰减规律.电场增强方式的时间常数比非电场增强方式小,表明加电场有促进晶化的作用.实时电阻测量方法可以用于金属诱导晶化动力学的研究,是一种简单实用的实时监控手段.     

铝诱导非晶硅薄膜低温晶化及结构研究

介绍了一种非晶硅薄膜低温晶化的新工艺－金属诱导非晶硅薄膜低温晶化。在非晶硅膜上蒸镀金属铝薄膜,而后于氮气保护中退火,实现了非晶硅薄膜的低温（＜600℃）晶化。利用X射线衍射、光学显微镜及透射电等测试方法,研究了不同退火工艺对非晶硅薄膜低温晶化的影响,确定了所制备的是多晶硅薄膜。     

铝诱导晶化真空蒸镀多晶硅薄膜的研究

采用真空蒸镀的方法在玻璃衬底上沉积1层非晶硅薄膜,再通过铝诱导晶化的方法制备出晶粒分布较均匀、晶粒尺寸0.5～5μm、晶化率达到89%的多晶硅薄膜。研究了衬底距离、衬底温度、退火温度对薄膜表面形貌、晶粒尺寸和分布及晶化率的影响。结果表明适中的衬底距离下得到的薄膜晶粒分布均匀,表面平整度好,薄膜厚度较大。薄膜的晶化率随着衬底温度和退火温度的提高而增大;随着退火温度的进一步提高,薄膜的晶化率达到最大值然后降低。     

多晶硅薄膜的铝诱导晶化法制备及其晶粒的择优取向特性

采用铝诱导非晶硅薄膜晶化技术制备了多晶硅薄膜,并研究了多晶硅的成核和生长特性。非晶硅薄膜采用等离子体增强化学气相沉积法制备,其表面沉积铝薄膜后经不同温度的氮氛围退火处理。结果表明,退火后的硅薄膜层与铝层发生置换,所生长的多晶硅颗粒的平均尺寸约为150nm。X射线衍射分析结果揭示,薄膜的晶向显著依赖于退火温度,较低温度下,铝诱导晶化速率较慢,薄膜的优化晶向与非晶硅薄膜中团簇的初始原子排列趋势紧密相关。而较高温度下,铝诱导晶化促使多晶硅(111)择优成核及随后的固相生长。     

金属镍诱导p型多晶硅薄膜的光电性能研究

利用电子束蒸镀方法及重掺杂p型硅为蒸发源在K8玻璃衬底上沉积非晶硅薄膜,采用镍诱导晶化法在氮气氛围下进行退火处理制备出p型多晶硅薄膜.研究了不同温度热处理条件对p型多晶硅薄膜的光电性能的影响,通过霍尔测量、拉曼光谱、原子力显微镜、紫外-可见光吸收光谱等测试手段对薄膜进行分析.结果表明,随着晶化温度的提高晶化程度先增强后...     

非晶硅薄膜晶化方法

多晶硅薄膜由于具有较高的载流子迁移率和良好的光电性能,广泛应用于集成电路及光电器件中,尤其在太阳电池领域引起了广泛关注。多晶材料晶界处会发生载流子的复合,降低载流子寿命。结晶度与晶粒尺寸是多晶硅薄膜取得良好性能的关键因素,直接制备的多晶硅薄膜一般晶粒尺寸较小、晶界较多,所以常采用非晶硅晶化法制备出晶粒尺寸较大的多晶硅薄膜。介绍了几种常见的非晶硅薄膜晶化方法,总结了各种晶化方法的机理和制备的薄膜的物理性质。     

Electrical stress effect on the leakage current of metal-induced laterally crystallized p-channel poly-Si TFTs

A p-type polycrystalline silicon thin-film transistor (TFT) was fabricated using the metal-induced lateral crystallization (MILC) technique at 550 degrees C. To reduce the leakage current in the MILC TFT, electrical stress (ES), newly developed in this work, was applied prior to the I(D)-V(G) measurements. It was found that ES is effective only when the TFT is under off-state. The stress gate voltage is related to the leakage current at high gate voltages and the electric field between the source and the drain to the leakage current at low gate voltages. The leakage current of the MILC TFT could be lowered to 10(-11) A for width/length ratios of 1/2 measured at the drain voltage of 3 V. A new plausible model has been suggested to explain the ES effect on the leakage current behavior in low-temperature polycrystalline silicon TFTs.     

On the study of p-channel thin-film transistors fabricated by SLS ELA crystallization techniques

The electrical characterization, in terms of drain current, of SLS ELA p-channel polysilicon TFTs is investigated. The study was based on the DLTS technique. It was found that drain current is governed by trapping/detrapping mechanisms associated to poly-Si/SiO₂ interface states. This fact is in accordance with the results of stretched exponential analysis applied on switch-ON drain current transients. DC hot carrier measurements under worse ageing condition regime were also conducted. Threshold voltage and transconductance variation revealed that hole injection towards the gate oxide is the prevailing mechanism, while poly-Si/SiO₂ interface degradation seems to be minor.     

Polycrystalline silicon thin films obtained by metal-induced crystallization

The formation of high-quality polycrystalline silicon (poly-Si) on different substrates has important applications in the development of thin-film transistors, solar cells, image sensors, etc. In this study, we present the results of an investigation of poly-Si films on glass, formed by aluminum-induced crystallization. The process is based on the isothermal annealing for 3 h at 500 °C of co-sputtered Al+Si or sputtered a-Si films on glass, with and without thermally evaporated Al. The poly-Si films were investigated by Raman spectroscopy, scanning electron microscopy, and X-ray photoelectron spectroscopy.     

Comparison of a-Si TFTs fabricated by Cat-CVD and PECVD methods

We investigate the characteristics of amorphous silicon thin film transistors (a-Si TFTs) fabricated by plasma-enhanced chemical vapor deposition (PECVD) and catalytic CVD (Cat-CVD), and their stability under bias and temperature (BT) accelerated stress. The Cat-CVD a-Si TFTs have off-leak current as small as 10^− 14 A, and a smaller threshold voltage shift under the BT stress. The superiority in off-leak current and stability is observed in the Cat-CVD a-Si TFTs fabricated at both 320 °C and 180 °C. The high performance and stability of the Cat-CVD a-Si TFTs will enable to use low-cost glass substrates and result in a cost reduction of TFT fabrication.     

氧化增强注氧隔离工艺制备绝缘体上的硅锗

提出一种氧化增强注氧隔离工艺,在退火前氧化得到SiO2层,再进行高温退火得到绝缘体上的硅锗材料.经X射线摇摆曲线和拉曼测试发现所制备的绝缘体上的SiGe材料锗含量没有发生损失,且应变弛豫完全.透射电镜和二次离子质谱分析结果显示样品多层结构清晰,埋氧层质量完好、平整度高、无不连续、无硅岛.研究表明,氧化增加工艺的引入是绝缘体上的硅锗材料锗质量提高的关键.     

The effects of nanometal-induced crystallization on the electrical characteristics of bottom-gate poly-Si thin-film transistors

The effects of active layer thickness and device dimensions on nanometal-induced crystallization (nano-MIC) were studied to determine the electrical characteristics of the polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with bottom-gate structures. The nano-MIC poly-Si film was obtained via deposition of a 0.4-nm-thick Ni film on the amorphous silicon layer and subsequent annealing at 550 degrees C for 0.5 to 8 h. The EDS revealed a approximately 0.1% Ni concentration in the poly-Si film. The cross-sectional TEM image shows the vertical-grain growth mechanism, where the bottom side of the grain exhibits a larger crytalline area than the top side. Therefore, the field effect mobility of the bottom-gate poly-Si TFTs increases with increased active-amorphous-silicon (a-Si) thickness. Furthermore, the mobility increases when the device dimensions are scaled down. A mechanism for explaining such phenomenon in relation to the nano-MIC bottom-gate poly-Si TFTs was also proposed.     

Ta上生长的硅薄膜退火的微晶化研究

对射频溅射功率80W条件下Ta缓冲层上生长的硅薄膜进行退火并用Raman散射和X射线衍射技术对样品的微观结构进行检测,系统研究了退火温度和退火时间对硅薄膜结晶性的影响.分析结果表明,在560℃退火2h或680℃退火1h之后,硅薄膜开始晶化,并且随着退火温度的增加或退火时间延长,薄膜逐渐由非晶向微晶转变.获得了可用于太阳能电池的微晶硅薄膜的最佳晶化参数.     

Germanium enhanced large-grain growth by pulse mode rapid thermal crystallization process

The large-grain crystallization for silicon film was implemented by doping germanium in silicon film and using a rapid thermal process with near-infrared illumination. Germanium atoms acted as nuclei for crystallization of the amorphous silicon film. Because the germanium embedded in silicon film could absorb infrared photonic energy and convert it into thermal energy. Due to the low thermal conductivity of germanium, the absorbed energy remained in the germanium-doped film for a long time and helped the grain growth. With the amount of germanium in silicon film increased, a large grain will be obtained readily. A grain size of 3.92 μm was achieved in germanium-doped film.     

The NTC thermistor fabricated by boundary-layer technology

A thermistor with a negative temperature coefficient of resistance (NTCR), based on the semiconducting (Ba_0.8Sr_0.2) (Ti_0.9Zr_0.1)O₃ ceramics, is fabricated by boundary-layer (BL) technology. By adding a suitable amount of V₂O₅ as additive, a semiconducting boundary layer is segregated at the grain boundaries after sintering in a reducing atmosphere. This layer dominates the temperature-dependent property and shows an NTCR effect with a thermistor constant of about 4200 K. Based on the microstructural and electrical properties, an n⁺-n-n⁺ energy band model is proposed for this boundary-layer thermistor.