SoC功能验证的特点和方法

简要分析了传统集成电路（ASIC）验证方法的特点以及将这些方法应用于系统级芯片（SoC）验证时所面临的问题。在此基础上，论述说明了模块级验证是提高SoC验证效率的基础；而基于随机测试激励的验证方法能够提升SoC的功能验证的覆盖率。另外，还介绍了用于SoC功能验证的关键方法，包括断言和RTL形式验证，Farm，随机化测试激励和功能覆盖等。     

A novel clock generation algorithm for system-on-chip based on least common multiple

Due to increase in the number of Intellectual Property (IP) cores, clock generation in current day System-on-Chips (SoCs) is facing a crisis. The conventional method of using a dedicated Phase Locked Loop (PLL) to generate the clock for each IP core is becoming inefficient in terms of power and cost. We propose an algorithm based on Least Common Multiple (LCM) to minimize the number of PLLs required to generate the clocks for the IP cores in a SoC. This is done by finding an Optimum Operating Frequency (OOF) for each IP core within 10% below the maximum operating frequency of the core. The OOF is chosen such that the LCM of the OOF of all the IP cores is minimized. Simulated annealing is used to find the LCM. This LCM is the crucial high frequency from which maximum number of clocks can be derived by clock dividers.     

深亚微米SoC芯片的可测试性设计

深亚微米工艺使SoC芯片集成越来越复杂的功能,测试开发的难度也不断提高。由各种电路结构以及设计风格组成的异构系统使测试复杂度大大提高,增加了测试时间以及测试成本。描述了一款通讯基带SoC芯片的DFT实现,这款混合信号基带芯片包含模拟和数字子系统,IP核以及片上嵌入式存储器,为了满足测试需求,通过片上测试控制单元,控制SoC各种测试模式,支持传统的扫描测试以及专门针对深亚微米工艺的,操作在不同时钟频率和时钟域的基于扫描的延迟测试模式,可配置的片上存储器的BIST操作以及其它一些特定测试模式。     

Scenario-based quasi-static task mapping and scheduling for temperature-efficient MPSoC design under process variation

Nowadays, employing the worst case analysis is the most common approach to provide unified static task mapping–scheduling plans on MPSoCs. Since the whole design space nor a subset of design space are not explored in the worst case methods, these approaches may fail to achieve efficient performance yield. In this paper, we present a temperature-aware quasi-static task mapping–scheduling framework under process variation for hard real-time and periodic systems on MPSoCs. By employing the stochastic optimization and scenario-based approaches, we explore a few representative scenarios in the whole design space of the chip using the probability density function of the problem random variables. Then, we obtain a compact set of near optimal mapping–scheduling of real-time tasks which targets performance-yield maximization and minimization of the expected values of peak temperature. Consequently, considering different chip parameter configurations, we construct the plan set as the solutions that attain the best variation-aware task mapping–scheduling that satisfy the deadline and minimize the temperature. This plan set can readily look up at run time by the system scheduler of the chip to find the proper plan of the tasks based on the run-time parameters. The experimental results demonstrate significant improvements in performance-yield and peak temperature for almost all of the test cases off homogenous and heterogeneous MPSoCs.