Optoelectronic component arrays for optical interconnection ofcircuits and subsystems

The design and performance of arrays of hybrid optoelectronic detector and modulator elements for use as optical input and output pads for chip- and board-level optical interconnects are discussed. The application of these interface arrays to specific VLSI circuits is discussed, illustrating the potential improvements in performance levels. This solder bond technique is capable of very accurate component positioning at points across the entire surface of the VLSI circuit, so that precise alignment to the optical pathways can be envisaged with optical signals taken from or delivered to any position on the chip. Measurements presented indicate that submicron positioning can be achieved. In particular, a fabrication-tolerant modulator design incorporating a chirped semiconductor mirror is reported     

Hierarchical interconnection structures for field programmable gatearrays

Field programmable gate arrays (FPGA's) suffer from lower density and lower performance than conventional gate arrays. Hierarchical interconnection structures for field programmable gate arrays are proposed. They help overcome these problems. Logic blocks in a field programmable gate array are grouped into clusters. Clusters are then recursively grouped together. To obtain the optimal hierarchical structure with high performance and high density, various hierarchical structures with the same routability are discussed. The field programmable gate arrays with new architecture can be efficiently configured with existing computer aided design algorithms. The k-way min-cut algorithm is applicable to the placement step in the implementation. Global routing paths in a field programmable gate array can be obtained easily. The placement and global routing steps can be performed simultaneously. Experiments on benchmark circuits show that density and performance are significantly improved     

Inductance and resistance computations for three-dimensionalmulticonductor interconnection structures

A computer-aided analysis system has been established to calculate the equivalent inductance and resistance matrices for three-dimensional multiconductor interconnection structures. Based on partial element equivalent circuit theory, the interconnection structures are first decomposed into many straight segments which are of circular or rectangular cross sections but can be in arbitrary orientation. The resistances and partial inductances between all these segments are calculated using analytical integration and quadrature formulae. They are assembled into the desired equivalent impedance matrix by general network theory. Illustrative examples include the analysis for nonuniformly coupled transmission lines and the calculation for skin-effect impedances of transmission lines and three-dimensional structures. The numerical results are in good agreement with the measurement data and results in the literature     

Free-space multistage optical interconnection networks using microlens arrays

Optical interconnections suitable for three-dimensional combining of lens arrays are presented. A multistage interconnection network with a self-routing function is described. The number of light paths this network is estimated to be capable of handling roughly ten or more times that of previously reported self-routing networks. Two separate lens arrays were fabricated to construct an 8×8 network of this design. The feasibility of the proposed interconnections was successfully demonstrated     

A mathematical programming method for constructing the shortest interconnection VLSI arrays

Mesh-connected processor array is an extensively investigated architecture in parallel processing. Massive studies have addressed the problem of using reconfiguration algorithms to solve the fault tolerance of faulty mesh-connected processor arrays. However, the subarrays generated by the previous studies still contain large interconnection length, which will lead to the increase of capacitance, power dissipation and dynamic communication cost. First, a mathematical model is established for the array reconfiguration. Then, the proposed method treats the interconnections between each PEs as a function with different integer variables, which can be solved by using effective integer programming techniques. Finally, an effective solver is called to find the optimal solution. Simulation results show that the proposed method can reduce the interconnection length of the array in the row and column directions simultaneously, thereby generating a subarray with the shortest interconnection length. On a 32 × 32 host array with fault density of 30%, the total interconnection length of the subarray can be reduced by 8.36% compared with state-of-the-art, and the average interconnection length can be reduced by 39.30%, which is more closer to the lower bound.     

A comparison of homogeneous hierarchical interconnection structures

Among the various proposal advanced to build massive parallel systems in which the number of computing units ranges in the thousands, hierarchical topologies share a number of interesting properties. The authors review these architectures and their applicability and reliability, with particular attention to connections complexity and the ability to exchange messages. The usual assumption of the multiple instruction multiple data (MIMD) computational paradigm is as follows: autonomous but cooperating tasks execute on different processing units in the system. The overall complexity of the systems is measured with the analysis of the diameter and of the increasing law that states the number of interconnections against the number of nodes in the system. The various architectures are compared in terms of links load and average internode distance     

Design of a self-reconfiguring interconnection network forfault-tolerant VLSI processor arrays

An interconnection network capable of spontaneously reconfiguring a VLSI processor array on detection of faulty processors is presented. Although the reconfiguration process is global, the network control circuitry is localized around each processor and is therefore completely modular. The structure of the control circuitry is fixed and thus independent of the array size or the number of spare processors. The network performance in yield enhancement is analyzed through Monte Carlo simulation. The network effectiveness in using surviving processors is close to that of an ideal network (one capable of tolerating as many faulty processors per row as there are spare processors per row). Strategies involved in testing the fault-tolerant array are also presented. Test circuitry is placed around each of the processors to enable testing of all the processors in parallel. The same circuitry is used to test the interconnection network efficiently. The additional silicon area requirements due to the network and the test circuitries are examined through the design of a prototype fault-tolerant array     

HIERACHICAL STRUCTURES FOR GENERATING PSEUDO-RANDOM SEQUENCES AND ARRAYS

This paper proposes new hierarchical structures for generating pseudorandom sequences and arrays. The principle of the structures is based on a new concept-multi-interleaving. It is the generalization of normal sequence decimation(sampling). The kernal of the structures is a lower speed linear feedback shift register together with several high speed time-division multiplexers arranged hierarchically. These new structures have much higher speed compared with that of other schemes proposed before.     

On-die diffractive alignment structures for packaging of microlens arrays with 2-D optoelectronic device arrays

A novel technique for aligning a microlens array to an electrically packaged optoelectronic device array is presented: reflective Fresnel zone plates (FZP's) are fabricated on the device die to provide registration spots during alignment. A proof-of-concept experiment in which an MSM array was aligned to a microlens array with an accuracy of better than 9 microns is described.     

New low-loss bend structures for high-density integrated opticalswitch arrays

A technique for lowering the loss around discrete bends in weakly guiding integrated optical circuits proposed, and modeling based on the beam-propagation method predicts a large improvement in the bend losses when it is applied. The idea of inserting an outrigger waveguide of high-refractive index appears to be novel, is relatively easily implemented practically, and shows considerable potential. The development of this idea is an excellent example of the use of numerical CAD (computer-aided design) tools in device design, since it is unlikely that it would have been discovered by experimentation alone. A CAD package for running the BPM (BEAMER) has been used to iterate towards low-loss bend geometries     

Area efficient computing structures for concurrent error detection in systolic arrays

A method of designing testable systolic architectures is proposed in this paper. Testing systolic arrays involves mapping of an algorithm into a specific VLSI systolic architecture, and then modifying the design to achieve concurrent testing. In our approach, redundant computations are introduced at the algorithmic level by deriving two versions of a given algorithm. The transformed dependency matrix (TDM) of the first version is a valid transformation matrix while the second version is obtained by rotating the first TDM by 180 degrees about any of the indices that represent the spatial component of the TDM. Concurrent error detection (CED) systolic array is constructed by merging the corresponding systolic array of the two versions of the algorithm. The merging method attempts to obtain the self testing systolic array at minimal cost in terms of area and speed. It is based on rescheduling input data, rearranging data flow, and increasing the utilization of the array cells. The resulting design can detect all single permanent and temporary faults and the majority of the multiple fault patterns with high probability. The design method is applied to an algorithm for matrix multiplication in order to demonstrate the generality and novelty of our approach to design testable VLSI systolic architectures.This work has been supported by a grant from the Natural Sciences and Engineering Research Council of Canada.     

Optimal interconnection circuits for VLSI

The propagation delay of interconnection lines is a major factor in determining the performance Of VLSI circuits because the RC time delay of these lines increases rapidly as chip size is increased and cross-sectional interconnection dimensions are reduced. In this paper, a model for interconnection time delay is developed that includes the effects of scaling transistor, interconnection, and chip dimensions. The delays of aluminum, WSi2, and polysilicon lines are compared, and propagation delays in future VLSI circuits are projected. Properly scaled multilevel conductors, repeaters, cascaded drivers, and cascaded driver/ repeater combinations are investigated as potential methods for reducing propagation delay. The model yields optimal cross-sectional interconnection dimensions and driver/repeater configurations that can lower propagation delays by more than an order of magnitude in MOSFET circuits.     

A full-wave analysis of interconnection planar lines applications to structures with finite ground plane

The high integration level associated to the increase of the operating frequency of microelectronic integrated circuits create complex electromagnetic coupling in the interconnection lines which lead to mismatch and frequency dispersion. In the present paper, we propose a full-wave analysis to characterise the electromagnetic behaviour of interconnection planar lines using mixed-potential integral equations technique. The theoretical and numerical treatments of Green’s functions for the specific structures are firstly presented. The calculated results for parallel and coplanar strips are compared to the published ones. The effect of the finite ground plane on the propagation constant and the characteristic impedance is then analysed for different permittivities. The obtained theoretical and experimental results for the reflection coefficient of straight resonators confirm finally the observed effect of the finite ground plane on the frequency dispersion and the scattering characteristics.     

Optimum design of feed structures for high G/T passive and activeantenna arrays

In this work, noise analysis of parallel feed structures is presented. Signal and noise behavior of the feed structures are signified by the newly introduced concepts of “coherent” and “incoherent” impedance match of power-combining structures. It is also shown that a feed structure can be redesigned for low-noise operation without affecting the radiation characteristics. Optimum design of parallel feed structures for low-noise operation is explained. Also an optimum use of active elements in such structures is investigated to have a low overall noise temperature of the antenna array with minimum number of active elements. In the analysis, a new method is introduced where a “noise-equivalent line length” (NELL) is defined. This definition, which unifies the contribution of noise from different array elements, is used in the design of a parallel feed structure and as an active circuit replacement criteria in passive arrays     

Selective electroless copper for VLSI interconnection

Cu is studied as a candidate for low-resistance VLSI interconnection. Simulation studies show that for effective channel length less than 0.5 μm, the RC time constant of interconnection is a major part of the total delay. By reducing the resistivity of the interconnect, the operating speed can be increased by more than 20% without any change in design rule. A selective electroless deposition process was used to solve the Cu patterning difficulty. Patterns of 2.2-μm pitch have been achieved with this process. The copper contamination issue is also studied; dielectric films such as silicon oxynitride and silicon nitride are shown to be effective in stopping Cu diffusion. By coating a thin Ni film on Cu, Cu corrosion can be reduced from 0.2 μ/h to less than 0.05 μm/h at 100°C in 4% KCL solution     

Vertically high-density interconnection for mobile application

There are several PWB technologies in the market that enables high density interconnection for product miniaturization, and this paper focuses on two HDI technologies, SSP and FVSS^®, and discuss the new PWB technologies and the reliability evaluation results for mobile applications. SSP is manufactured in simple lamination process using conventional FR4 materials, which enables future cost reduction and high reliability. FVSS contains filled buried via hole (BVH) and filled micro blind via (μvia) process. By combining the two process FVSS accomplishes high vertical design capability with Stacked μvia-on-μvia and stacked μvia-on-BVH designs.Key reliability requirements for final product quality is drop and temperature cycling reliability in board level in addition to evaluate PWB specific tests to compare performance of new materials used in PWB.     

Antenna interconnection strategies for personal communicationsystems

Microcellular and distributed antenna systems are two promising candidates for implementing personal communication systems. Antenna interconnection strategies for these systems are studied in order to determine cost-efficient as well as robust and flexible architectures in hexagonal layouts. To this end, some results from minimal networks theory are used, in particular, those dealing with the problem of Steiner trees. The significant reduction in conduit and cable lengths that the Steiner minimal tree (SMT) architecture provides over the star type, especially in large networks, is demonstrated. It is further shown that the SMT architecture also provides more flexibility and robustness compared to the star type. The suboptimal, but easy-to-construct, minimal spanning tree (MST) architecture is given as well, and it is compared to the SMT and star types     

An interconnection architecture for network-on-chip systems

Network on Chip (NoC) is a discipline research path that primarily addresses the global communication in System on Chip (SoC). It is inspired and uses the same routing and switching techniques needed in multi-computer networks. Current shared-bus based on-chip communication architectures generally have limited scalability due to the nature of the buses especially when complex on-chip communication SoC is needed. The main goal is to have a dedicated communication infrastructure in the system that can scale up while minimizing the area and power. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we introduce a new NoC architecture by adapting a recursive topology structure. An experimental study is performed to compare this structure with basic NoC topologies represented by 2D mesh and Spidergon. The analysis illustrates the main features of this topology and its unique benefits. The simulation results show that recursive network outperforms 2D mesh and Spidergon in main performance metrics.     

Characterization of nonconductive adhesives for flip-chip interconnection

For chip-level interconnection, nonconductive adhesive (NCA) is emerging as one of the promising substitutes for solder interconnection because of its inherent fine-pitch capability and environmental friendliness. The NCA interconnect relies on the mechanical connection between the contacts on the chip and corresponding contacts on the substrate enabled by the compressive stress created as the NCA epoxy cures. The degradation mechanism of NCA technology is, however, relatively less well understood compared to solder interconnects in terms of materials requirements for enhanced reliability performance. This study addresses the impact of material systems employed on the reliability of the packages. This involves characterization of NCA pastes in thermomechanical, hygroscopic swelling, and moisture diffusion properties. The reliability evaluation was carried out using electroless nickel/gold perimeter bumped test chips with daisy-chained connections. Analysis showed that interfacial delamination and open contact were the major failure modes in the NCA package. Pressure cooker test (PCT) performance was improved by using NCA with low-saturated moisture concentration, low coefficient of moisture expansion, and high adhesion. For better performance in the moisture sensitivity test (MST), the key properties required were high shear strength and low moisture diffusivity. Interestingly, filler content shows opposing behavior in the MST versus the PCT. Thus, optimum filler content must be found.     

Packet-switched on-chip interconnection network for system-on-chip applications

Increasing complexity of a system-on-chip design demands efficient on-chip interconnection architecture such as on-chip network to overcome limitations of bus architecture. In this brief, we propose a packet-switched on-chip interconnection network architecture, through which multiple processing units of different clock frequencies can communicate with each other without global synchronization. The architecture is analyzed in terms of area and energy consumption, and implementation issues on building blocks are addressed for cost-effective design. A test chip is implemented using 0.38-/spl mu/m CMOS technology, and measured its operation at 800 MHz to demonstrate its feasibility.