一种适用于高速串行数据通信的发送器设计

为满足点对点高速串行数据通信的需求,设计了一款适用于点对点高速串行数据通信的发送器芯片.该发送器包括产生高速时钟的内嵌锁相环倍频电路、集成8B/10B编码电路以及并串转换电路等模块.根据数模混合信号设计的特点,在电路设计上采用了CMOS、CML及BiCMOS等多种电路拓扑结构以提高芯片性能;在版图设计上采取了减小噪声耦合的措施.该发送器采用2P2M 0.6μm BiCMOS工艺实现,芯片面积2.4mm×2.5mm,陶瓷封装.测试结果表明:该发送器的逻辑功能正确,串行传输速率达400Mbpa,功耗350mW.     

一种适用于高速串行数据通信的发送器

介绍了一种采用深亚微米CMOS工艺实现的单片集成发送器的设计.该发送器适用于高速串行硬盘接口,主要由时钟发生器、并串转换电路和片内阻抗匹配的线驱动器三大模块组成.发送器采用0.18μm六层金属单层多晶N阱CMOS工艺实现,芯片面积1.3mm×0.78mm.测试结果表明时钟发生器可工作在1.5GHz的频率下,数据可以正常发送.发送器总体功耗为95mW,输出共模电平270mV,单端输出幅度270mV.     

一种适用于高速串行数据通信的发送器

介绍了一种采用深亚微米CMOS工艺实现的单片集成发送器的设计.该发送器适用于高速串行硬盘接口,主要由时钟发生器、并串转换电路和片内阻抗匹配的线驱动器三大模块组成.发送器采用0 .18μm六层金属单层多晶N阱CMOS工艺实现,芯片面积1.3mm×0 .78mm .测试结果表明时钟发生器可工作在1.5 GHz的频率下,数据可以正常发送.发送器总体功耗为95 m W,输出共模电平2 70 m V ,单端输出幅度2 70 m V.     

Bitmap Algorithms for Counting Active Flows on High-Speed Links

This paper presents a family of bitmap algorithms that address the problem of counting the number of distinct header patterns (flows) seen on a high-speed link. Such counting can be used to detect DoS attacks and port scans and to solve measurement problems. Counting is especially hard when processing must be done within a packet arrival time (8 ns at OC-768 speeds) and, hence, may perform only a small number of accesses to limited, fast memory. A naive solution that maintains a hash table requires several megabytes because the number of flows can be above a million. By contrast, our new probabilistic algorithms use little memory and are fast. The reduction in memory is particularly important for applications that run multiple concurrent counting instances. For example, we replaced the port-scan detection component of the popular intrusion detection system Snort with one of our new algorithms. This reduced memory usage on a ten minute trace from 50 to 5.6 MB while maintaining a 99.77% probability of alarming on a scan within 6 s of when the large-memory algorithm would. The best known prior algorithm (probabilistic counting) takes four times more memory on port scan detection and eight times more on a measurement application. This is possible because our algorithms can be customized to take advantage of special features such as a large number of instances that have very small counts or prior knowledge of the likely range of the count.     

Eye-Pattern Design for High-Speed Differential Links Using Extended Passive Equalization

The performance of current high-speed consumer electronic systems is often compromised by degradation caused by distortion in eye patterns. This paper proposes a systematic method that uses the voltage transfer function for arbitrary source and load terminations to improve the eye patterns of high-speed differential links with passive components that minimize distortion. This approach is cost-effective since it only utilizes commercially available surface-mount components. The methodology has been validated by measurements in this paper.     

一种高速双通道串行总线接口

本文描述了一种用于实时多机系统的高速双通道串行总线接口,能在两条总线上同时通讯.通讯与CPU工作并行,具有效率高,实时性强,电路简单之优点.     

Control System With High-Speed and Real-Time Communication Links

Recent technological advances have enabled distributed control systems to be implemented via networks. This allows feedback control loops to be closed over communication channels. This paper develops a control system with high-speed and real-time communication links. Two-degrees-of-freedom control is utilized in this servo control system, and sigma-delta modulation is employed to compress data and to transmit the signal over the transmission channels between the controller and the controlled plant. Simulation results show that the controller can compensate the possible existing noise in the transmission channels. In addition, the developed system is implemented in field-programmable gate arrays. We developed a real-time closed-loop control system that has a communication channel whose control-sampling period is 600 ns and can reduce the sampling period of the controller module to hundreds of nanoseconds.     

基于高速EAM集成光源的微波光纤传输链路

基于AlGaInAs多量子阱高速电吸收调制器(EAM)集成光源,构建了微波光纤传输链路,并研究了掺铒光纤放大器(EDFA)对其链路特性的影响,实现了40GHz频段97.4dB.Hz2/3的无失真动态范围。     

A Multichannel Scheduler for High-Speed Wireless Backhaul Links with Packet Concatenation

Capacity has been an important issue for many wireless backhaul networks. Both the multihop nature and the large per packet channel access overhead can lead to its low channel efficiency. The problem may get even worse when there are many applications transmitting packets with small data payloads, e.g., Voice over Internet Protocol (VoIP). Previously, the use of multiple parallel channels and employing packet concatenation were treated as separate solutions to these problems. However, there is no available work on the integrated design and performance analysis of a complete scheduler architecture combining these two schemes. In this paper, we propose a scheduler that concatenates small packets into large frames and sends them through multiple parallel channels with an intelligent channel selection algorithm between neighboring nodes. Besides the expected capacity improvements, we also derive delay bounds for this scheduler. Based on the delay bound formula, call admission control (CAC) of a broad range of scheduling algorithms can be obtained. We demonstrate the significant capacity and resequencing delay improvements of this novel design with a voice-data traffic mixing example, via both numerical and simulation results. It is shown that the proposed packet concatenation and channel selection algorithms greatly outperform the round-robin scheduler in a multihop scenario.     

A New CMOS Current-Mode Multiplexer for l0 Gbps Serial Links

This paper presents an in-depth study of the pros and cons of voltage-mode multiplexers for Gbps serial links and exploits the advantages of multiplexing in current domain. In addition, it proposes a new fully differential CMOS current-mode multiplexer where a high multiplexing speed is achieved by multiplexing at a low-impedance node. Multiplexing speed is further improved by inductive shunt peaking with active inductors. The differential configuration of the multiplexer minimizes the effect of common-mode disturbances, particularly those coupled from the power and ground rails. The flow of the output currents in the opposite directions minimizes the effect of electro-magnetic interference from channels, making the multiplexer particularly attractive for high-speed data transmission over long interconnects and printed-circuit-board (PCB) traces. The proposed multiplexer draws a constant current from the supply voltage, thereby minimizing both switching noise and noise injected to the substrate. A fully differential CMOS current-mode 8-to-l multiplexer has been implemented in TSMC’s 1.8 V 0.18 μm CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3v device models. Simulation results demonstrate that the multiplexer offers sufficiently large eye-opening when multiplexed at 10 Gbps.Jean Jiang received the B.Eng. degree in Electrical Engineering from Wuhan University of Technology, Wuhan, China in 1995. From 1999 to 2001, she worked for Ericsson Global IT Services where she was a technical staff to maintain computer networks. Since 2002, she has been a research assistant with the System-on-Chip research lab of Ryerson University. She is currently a M.A.Sc candidate under the supervision of Dr. Fei Yuan in the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Canada. Her research interests are in analog CMOS circuit design for high-speed data communications. She was awarded the Ontario Graduate Scholarship (OGS) in 2003–2005 for academic excellence.Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the MASc. degree in chemical engineering and PhD. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively.During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Canada. During 1989–1994, he worked for Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer. Since July 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book “Computer Methods for Analysis of Mixed-Mode Switching Circuits” (Kluwer Academic Publishers, 2004, with Ajoy Opal). Dr. Yuan received an “Excellence of Teaching” award from Changzhou Institute of Technology in 1988, a post-graduate scholarship from Natural Science and Engineering Research Council (NSERC) of Canada during 1997–1998. He is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada.     

Modeling and Analysis of High-Speed I/O Links

Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this regime, it is critical to accurately model and comprehend channel/circuit nonidealities in order to co-optimize the link architecture, circuits, and interconnect. Empirical and worst-case analysis methods used at lower rates are inadequate to account for several deterministic and random noise sources present in I/O links today. In this paper, we review models and methods for statistical signaling analysis of high-speed links, and also propose a new way to integrate behavioral modeling approaches with analytical methods. A computationally efficient segment-based analysis method is shown to accurately capture the effect of transmit jitter and its interaction with the channel. In addition, a new jitter interpretation approach is proposed to enable the analysis of arbitrary I/O clocking topologies. We also present some examples to illustrate the practical utility of these analysis methods in the realm of high-speed I/O design.      

Specialized Methods and Tools for Accelerated Characterization of High-Speed Serial Transceivers

Journal of Communications Technology and Electronics - Specialized methods and tools (high-level models) that can significantly speed up the calculations of high-speed serial channel transceivers...     

一种新型的用于高速串行接口的发送器

本文提出了一种新型的适用于USB2．0高速模式下(480Mb／s的数据传送率)的发送器电路。发送器主要由前置驱动电路和主驱动电路组成。前置驱动电路和主驱动电路分别由8级延迟单元和8级驱动单元组成。通过控制延迟单元的延迟时间和改变电路级数，可控制输出数据信号特性。电路设计基于TSMC的CMOS 0．25μm混合信号模型。电路仿真表明输出信号速率达到480Mb／s，并且高低电平幅值和上升下降时间符合USB2．0协议要求。     

New CMOS Class AB Transmitter for 10 Gb/s Serial Links

This paper presents a new fully differential CMOS class AB transmitter for 10 Gb/s serial links. The transmitter consists of a fully differential multiplexer, a rail-to-rail configured pre-amplification stage, and a push-pull output stage. The multiplexer achieves a high multiplexing speed by using modified pseudo-NMOS logic where pull-up networks are replaced with self-biased active inductors. The rail-to-rail configured pre-amplification stage with active inductors amplifies the signals from the multiplexer. The fully differential output current is generated by a class AB output stage operated in a push-pull mode. High data rates of the transmitter are obtained by ensuring that the transistors in both the pre-amplification and output stages are always in saturation and the voltage swing of all critical nodes is small. The fully differential configuration of the transmitter effectively suppresses common-mode disturbances, particularly those coupled from the power and ground rails, the electro-magnetic interference exerted from channels to neighboring devices is also minimized. The transmitter minimizes switching noise by drawing a constant current from the supply voltage. The transmitter has been implemented in TSMC 0.18 μm 1.8 V 6-metal CMOS technology and analyzed using Spectre from Cadence Design Systems with BSIM3.3 device models. Simulation results demonstrate that the transmitter provides a 5 mA peak-to-peak differential output current with 100 ps eye-width and >5 mA eye-height at 10 Gb/s. The transmitter consumes 18 mW with a total transistor area of 100 μm² approximately. Jean Jiang received the B.Eng. degree in Electrical Engineering from Wuhan University of Technology, Wuhan, China in 1995, and the M.A.Sc. degree in Electrical and Computer Engineering from Ryerson University, Toronto, Ontario, Canada in 2004. From 1999 to 2001, she worked for Ericsson Global IT Services where she was a technical staff to maintain computer networks. From 2002 to 2004, she was a research assistant and a M.A.Sc. student with the Microsystem Research Laboratory in the Department of Electrical and Computer Engineering at Ryerson University. She is now with Intel Corp., CA. as an IC design engineer. Her research interests are in analog CMOS circuit design for high-speed data communications. Jean Jiang was awarded the Ontario Graduate Scholarship in 2003–2005 for academic excellence. Fei Yuan received the B.Eng. degree in electrical engineering from Shandong University, Jinan, China in 1985, the M.A.Sc. degree in chemical engineering and Ph.D. degree in electrical engineering from University of Waterloo, Waterloo, Ontario, Canada in 1995 and 1999, respectively. During 1985–1989, he was a Lecturer in the Department of Electrical Engineering, Changzhou Institute of Technology, Jiangsu, China. In 1989 he was a Visiting Professor at Humber College of Applied Arts and Technology, Toronto, Ontario, Canada, and Lambton College of Applied Arts and Technology, Sarnia, Ontario, Canada. He was with Paton Controls Limited, Sarnia, Ontario, Canada as a Controls Engineer during 1989–1994. Since 1999 he has been with the Department of Electrical and Computer Engineering, Ryerson University, Toronto, Ontario, Canada, where he is currently an Associate Professor and the Associate Chair for Undergraduate Studies and Faculty Affairs. He is the co-author of the book Computer Methods for Analysis of Mixed-Mode Switching Circuits (Springer-Verlag, 2004, with Ajoy Opal). Dr. Yuan received the Ryerson Research Chair award from Ryerson University in Jan. 2005, the Research Excellence Award from the Faculty of Engineering and Applied Science of Ryerson University in 2004, the post-graduate scholarship from Natural Science and Engineering Research Council of Canada during 1997–1998, and the Teaching Excellence Award from Changzhou Institute of Technology in 1988. Dr. Yuan is a senior member of IEEE and a registered professional engineer in the province of Ontario, Canada.     

Wiener Filter Based Channel Estimation for High-Speed Communication Environments

Wiener filter is the best channel interpolation method in terms of minimizing mean square error at the time dimension. However, Wiener filter with low order will lose its efficiency in high-speed communication environments, while Wiener filter with high order suffers from the problem of high computational complexity. In this paper, we analyze the relationships among Wiener filter with different orders and their corresponding application scenarios. Furthermore, based on the analysis, a pilot symbol design criterion for high-speed communication environments and a simplified Wiener filter based channel estimation technique are proposed, respectively.     

16位高速DSP增强型同步串行口的设计

分析了一种16位高速DSP中增强型同步串口的帧格式及其接口和功能;详细讨论了同步串口的系统级和行为级的设计过程。利用Verilog,设计出同步串口的电路;并通过计算机仿真和实验,证明了设计的正确性。     

雨衰卫星链路质量的一种优化估计算法

本文提出一种雨衰信道Eb/N0的优化估计算法。利用维持比译码器提供纠错个数的功能可以估计BER，结合一个有效的雨衰预测模型，本算法预测出最优估计时间，以此估计出雨衰信道的Eb/N0值和雨衰值。     

CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems

Three dimensional (3D) integrated systems become a reality nowadays, as Thru-Silicon-Via (TSV) technologies mature. 3D integration promises significant performance and energy efficiency improvements by reducing the signal travel distances and integrating more capabilities on a single chip. High integration costs, thermal management, and poor reliability and yield are major challenges of TSV based 3D chips. High structural and parametric fault rates due to manufacturing defects makes it difficult to achieve high interconnect yield using only spare-based repair solutions. In this paper we address the TSV yield issue by implementing the inter-die links of 3D chips as Configurable fault-tolerant Serial Links (CSLs). When there are not enough available functional TSVs, faults are tolerated by performing data serialization. CSLs help reduce chip costs by improving the TSV yield with very few or no spares at all. For 3D Networks-on-Chip (3D NoCs) we show that the CSL yield improvement comes with moderate area overheads (~12–26%) and small performance penalties (less than 5% average latency overhead).     

一种新型的用于高速串行接口电路中的接收器

本文提出了一种新型的符合计算机与外围设备间通用串行接口USB(Universal Serial Bus)2．0高速模式(480Mb／s数据传输率)的高精度接收器电路，并分析了其设计思路和设计方案。这种高精度接收器由三级电路组成：电压转换级、数据采样级和数据保持级。电路设计基于TSMC的CMOS 0．25μm混合信号模型。仿真结果表明，这种接收器在500Mb／s的信号传输速率下，将输入数据的上升和下降时间从700ps降至140ps，提高了高速串行通信中采样数据的准确度，以保证可靠、正确接收数据。     

A Programmable Pre-emphasis Technique with Combined RLC Source Degeneration for High-Speed Serial Link Transmitters

This paper presents a clock-less pro-grammable pre-emphasis technique realized by a driver with combined resistive-inductive-capacitive source degen-eration for...