固化残余应力对倒装焊底充胶可靠性的影响

通过对考虑固化过程影响的倒装焊底充胶的热－机械有限元模拟，分析了底充胶在固化过程中因体积收缩，材料的刚度增加及受周围材料的约束所产生的固化残余应力对随后热循环加载下底充胶应力分布与幅值的影响，得出了固化过程及其固化残余应力不但进一步劣化了热循环加载下底充胶中的应力值，而且还影响了随后底充胶的热－机械疲劳可靠性的结论。     

倒装焊器件尺寸参数对低k层及焊点的影响

当前。集成电路制造中低k介质与铜互连集成工艺的引入已经成为一种趋势,因此分析封装器件中低矗结构的可靠性是很有必要的。利用有限元软件分析了倒装焊器件的尺寸参数对低k层及焊点的影响。结果表明：减薄芯片,减小PI层厚度,增加焊点高度,增加焊盘高度,减小基板厚度能够缓解低k层上的最大等效应力;而减薄芯片,增加PI层厚度,增加焊点高度,减小焊盘高度,减小基板厚度能够降低焊点的等效塑性应变。     

固化残余应力对倒装焊器件热-机械可靠性的影响

采用底充胶的与固化过程相关的粘弹性力学模型,通过有限元仿真的方法,模拟了底充胶的整个固化过程,计算出了热循环加载下硅片、底充胶/硅片界面、底充胶内部的应力分布及其幅值大小。结果表明:底充胶的固化过程及由此产生的固化残余应力不但使得硅片中的最大垂直开裂应力位置偏离中心线达1.6 mm之多,而且还劣化了热循环加载下底充胶中应力幅值约6.25%。最后得出了固化残余应力对倒装焊器件热–机械可靠性的影响是不可忽略的结论。     

固化残余应力对倒装焊器件热–机械可靠性的影响

采用底充胶的与固化过程相关的粘弹性力学模型,通过有限元仿真的方法,模拟了底充胶的整个固化过程,计算出了热循环加载下硅片、底充胶/硅片界面、底充胶内部的应力分布及其幅值大小.结果表明:底充胶的固化过程及由此产生的固化残余应力不但使得硅片中的最大垂直开裂应力位置偏离中心线达1.6 mm之多,而且还劣化了热循环加载下底充胶中应力幅值约6.25%.最后得出了固化残余应力对倒装焊器件热–机械可靠性的影响是不可忽略的结论.     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法 ,确定了倒装焊 Sn Pb焊点的热循环寿命 .采用粘塑性和粘弹性材料模式描述了 Sn Pb焊料和底充胶的力学行为 ,用有限元方法模拟了 Sn Pb焊点在热循环条件下的应力应变过程 .基于计算的塑性应变范围和实验的热循环寿命 ,确定了倒装焊 Sn Pb焊点热循环失效 Coffin- Manson经验方程的材料参数 .研究表明 ,有底充胶倒装焊 Sn Pb焊点的塑性应变范围比无底充胶时明显减小 ,热循环寿命可提高约 2 0倍 ,充胶后的焊点高度对可靠性的影响变得不明显     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

湿热环境下倒装焊无铅焊点的可靠性

对板上倒装芯片底充胶进行吸湿实验,并结合有限元分析软件研究了底充胶在湿敏感元件实验标准MSL—1条件下吸湿和热循环阶段的解吸附过程,测定了湿热环境对Sn3.8Ag0.7Cu焊料焊点可靠性的影响,并用蠕变变形预测了无铅焊点的疲劳寿命。结果表明:在湿热环境下,底充胶材料内部残留的湿气提高了焊点的应力水平。当分别采用累积蠕变应变和累积蠕变应变能量密度寿命预测模型时,无铅焊点的寿命只有1740和1866次循环周期。     

与CMOS—SEED灵巧象素相关的倒装焊工艺

介绍了新型ＣＭＯＳ－ＳＥＥＤ灵巧象素结构原理及相关的倒装焊技术。采用厚光致抗蚀剂作掩模,通过磁控溅射和真空蒸发相结合,解决了与ＣＭＯＳ－ＳＥＥＤ有关的Ｉｎ凸点阵列成型等关键工艺,并用Ｍ８－Ａ型可视对准式倒装焊系统完成了ＣＭＯＳ电路芯片和ＳＥＥＤ阵列芯片的倒装焊。     

超声扫描技术在倒装焊器件中的应用北大核心CSCD

倒装焊器件底充胶的填充质量对于芯片可靠性的影响较大。超声扫描技术可以有效检测芯片与基板之间凸点周围的底充胶的填充质量。选用30 MHz和110 MHz频率的超声换能探头检测底充胶层,两种频率探头检测结果清晰度均能满足底充胶缺陷检测要求。结果显示,30 MHz探头聚焦范围宽于110 MHz探头,操作更为简便。对于包含热沉的器件,热沉的存在会干扰超声扫描显微镜对底充胶层的检测,未去除热沉可能导致研究者误判底充胶层填充情况,去除热沉后可获得底充胶层的清晰成像。倒装焊器件底充胶层厚度比较薄,检测时SAM的栅门宽度选取不易过宽,否则会影响图像清晰度,其具体值可视被测器件不同而调整。     

一种用于MEMS器件的Au-In倒装焊技术

介绍了Au-In键合在MEMS芯片封装中的应用.根据现有的工艺设备和实验条件对制备铟凸点阵列进行工艺设计,对铟凸点制备技术进行了研究,最终在硅圆片上制备了6 μm高的铟凸点阵列.在150～300℃下成功的进行了Au-In倒装键合实验.在300℃,0.3 MPa压力下键合的剪切强度达到了5 MPa.     

倒装芯片放置工艺的设计分析

对倒装芯片不流动底部填充胶进行压迫流动填充,底部填料会对倒装芯片产生流体静态压力,阻碍芯片向下放置。根据牛顿流体挤压流动的静态近似分析估算出底部填料对芯片的作用力,分别计算在两种不同工艺条件下放置压力达到最大时,两种不同规格芯片与基板的间隔距离,比较与芯片凸点高度,然后计算使芯片凸点与基板键合区实现接触所需放置压力的最小保持时间,从正反两个方面讨论关键参数等对倒装芯片工艺设计影响。     

百万像素级红外焦平面器件倒装互连工艺研究

介绍了倒装互连技术的工艺原理,阐述了红外焦平面器件倒装互连的工艺特点。通过系列实验和分析,最终优化并确定了百万像素级红外焦平面器件倒装互连的工艺参数,获得了良好的互连效果。     

Effects of underfill material properties on the reliability ofsolder bumped flip chip on board with imperfect underfill encapsulants

Three different types of underfill imperfections were considered; i.e., (1) interfacial delamination between the underfill encapsulant and the solder mask on the PCB (crack initiated at the tip of underfill fillet), (2) interfacial delamination between the chip and the underfill encapsulant (crack initiated at the chip corner), and (3) the same as (2) but without the underfill fillet. Five different combinations of coefficient of thermal expansion (CTE) and Young's modulus with the aforementioned delaminations were investigated. A fracture mechanics approach was employed for computational analysis. The strain energy release rate at the crack tip and the maximum accumulated equivalent plastic strain in the solder bumps of all cases were evaluated as indices of reliability. Besides, mechanical shear tests were performed to characterize the shear strength at the underfill-solder mask interface and the underfill-chip passivation interface. The main objective of the present study is to achieve a better understanding in the thermo-mechanical behavior of flip chip on board (FCOB) assemblies with imperfect underfill encapsulants     

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.     

Advanced HiCTE flip chip packaging of 90-nm Cu/Low-K chips: Underfill,novel terminal pad structures,and processing optimization

Packaging of 90-nm Cu/Low-K chips presents a serious challenge, which requires an advanced ceramic flip chip solution. Finer Cu interconnects are expected to interact differently with the current underfill-to-die passivation stack-up structures used for Al or previous Cu technology nodes especially in system level applications. Furthermore, the more porous and brittle-proned advanced Low-K (K<3) dielectrics present additional process incompatibility problems such as stress-induced crackings and delaminations. These reliability issues in various stress-relieving passivation structures and materials (i.e., Benzocyclobutene (BCB) and single versus double SiOxNy passivations) have not been extensively studied. This study analyzes the effect of the eight metal layer 90-nm Cu/Low-K flip chip devices through designed experiments using two relatively different underfill materials, standard terminal pad and novel passivation structures, and JEDEC Level-3 reliability stressings: temperature cycling (TC), highly accelerated stress testing (HAST), and high-temperature storage (HTS). Black Diamond Low-K and HiCTE ceramic substrates are employed for the large package form factor. The active Si uses eutectic stencil-pasted SnPb bump and BGA balls with Ti/Ni-V/Al-Cu reflectory thin film-deposited under bump metallurgy (UBM). It is found that the double passivation pad structures are less susceptible to reliability damage for various types of underfills, although a single passivation with BCB coating combined with an optimal underfill can also yield a similar favorable result. The metallurgical effect of delamination cracking, HiCTE flip chip and stress-relieving passivation structures, and the underfill interface failure mode mechanism are examined by functional testing, chemical deprocessings, scanning acoustic microscope (SAM), and scanning electron microscope (SEM)/energy-dispersive x-ray (EDX). The presented results are significant for the development of flip chip packaging technologies for future advanced Cu/Low-K generations.     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

Anisotropic behavior of the capillary action in flip chip underfill

An underfill encapsulant can be used to improve the long-term reliability of flip chip interconnecting system by filling the gap between the chip and substrate around the solder bumps. The underfill encapsulant was filled by a capillary flow. This study was devoted to investigate the anisotropic effects of the capillary action induced by the solder bumps. A modified Hele-Shaw flow model, considering the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. A capillary force model, depending on the direction of filling flow, for full array solder bumps was proposed. The capillary force was formulated based on quadrilateral arrangement of solder bumps. It was found that the capillary action is not the same for different directions. In the 45° direction, enhancement of the capillary flow was noticed for a bump pitch within a critical value. The edge preferential flow during the underfill experiment could be attributed to the anisotropic behavior of the capillary action.     

Studies of electroless nickel under bump metallurgy—Solder interfacial reactions and their effects on flip chip solder joint reliability

The electroless-deposited Ni-P under bump metallurgy (UBM) layer was fabricated on Al pads for Sn containing solder bumps. The amount of P in the electroless Ni film was optimized by controlling complexing agents and the pH of plating solution. The interfacial reaction at the electroless Ni UBM/solder interface was investigated in this study. The intermetallic compound (IMC) formed at the interface during solder reflowing was mainly Ni₃Sn₄, and a P-rich Ni layer was also formed as a by-product of Ni-Sn reaction between the Ni-Sn IMC and the electroless Ni layer. One to four microns of Ni₃Sn₄ IMC and a 1800–5000 Å of P-rich Ni layer were formed in less than 10 min of solder reflowing depending on solder materials and reflow temperatures. It was found that the P-rich Ni layer contains Ni, P, and a small amount of Sn (～7 at.%). Further cross-sectional transmission electron microscopy (TEM) analysis confirmed that the composition of the P-rich Ni layer was 75 at.% Ni, 20at.%P, and 5at.%Sn by energy-dispersive x-ray spectroscopy (EDS) and the phase transformation occurred in the P-rich Ni layer by observing grain size. Kirkendall voids were also found in the Ni₃Sn₄ IMC, just above the P-rich Ni layer after extensive solder reflow. The Kirkendall voids are considered a primary cause of the brittle fracture; restriction of the growth of of the P-rich Ni layer by optimizing proper processing conditions is recommended. The growth kinetics of Ni-Sn IMC and P-rich Ni layer follows three steps: a rapid initial growth during the first 1 min of solder reflow, followed by a reduced growth step, and finally a diffusion-controlled growth. During the diffusion-controlled growth, there was a linear dependence between the layer thickness and time^1/2. Flip chip bump shear testing was performed to measure the effects of the IMC and the P-rich Ni layers on bump adhesion property. Most failures occurred in the solder and at the Ni₃Sn₄ IMC. The brittle characteristics of the Ni-Sn IMC and the Kirkendall voids at the electroless Ni UBM-Sn containing solder system cause brittle bump failure, which results in a decreased bump adhesion strength.     

倒装芯片互连结构中电流聚集研究

由于电流聚集,在倒装芯片封装技术中,电迁移已经成为一个关键的可靠性问题。分析了电迁移力和电迁移中值失效时间,采用二维模型研究了电流密度和焦耳热在倒装芯片互连结构中的分布以及影响电流密度和焦耳热分布的因素。结果表明铝线(Al)和凸点下金属层(UBM)的厚度对电流密度和焦耳热分布有很大的影响。     

氧化层对于倒装焊接质量的影响和分析

利用氧化铟易于溶于酸性溶液的性质,提出了在倒装焊接之前使用酸性溶液对铟柱进行酸洗.在未进行酸洗和进行酸洗的条件下,对比了样品在焊接之后的拉力以及在经过热循环后的盲元率,结果显示酸洗能够降低表面氧化层的影响,有效地改善倒装焊接的质量.