一种基于贪婪算法的CORDIC改进算法

针对传统串行坐标旋转数字计算方法(CORDIC)耗时且占用较多资源的缺点,提出了一种旋转模式下CORDIC算法的新型改进算法,该改进算法可用来代替直接数字频率合成器(DDS)查找表进行正余弦的计算。通过采用贪婪算法实现对CORDIC旋转方向与旋转角度的优化,从而可以达到串行转并行和减少迭代次数、节约资源的目的。该算法可以应用于三角函数的复杂函数的硬件实现中。仿真结果表明,在迭代次数相同的情况下,改进算法较传统算法可以获得更高的精度。最后,在Xilinx FPGA的Spartan-3E芯片上实现了改进的CORDIC结构。与传统CORDIC算法相比,在运算精度为10-5时,可以节省Slices、LUTs(Look Up Tables)资源分别为28%和25%。     

免缩放因子双步旋转CORDIC算法

集成电路设计中经常使用CORDIC算法实现高效的向量旋转操作.当前对该算法的研究热点集中在减少该算法的迭代次数、扩展其收敛范围以及降低缩放因子补偿操作的代价等问题上.本文提出免缩放因子的双步旋转CORDIC算法使用双步旋转策略,减少了免缩放因子CORDIC算法的迭代次数,将收敛区间扩展到了整个圆周区间.实验结果表明,该算法保持高计算精度的同时减少了迭代次数和面积消耗.     

高速高精度固定角度旋转CORDIC算法的设计与实现

固定角度旋转的CORDIC(Coordinate Rotation Digital Computer)算法已经广泛的应用于高速数字信号处理、图像处理、机器人学等领域.针对固定角度旋转CORDIC算法在相位旋转过程中,存在数据吞吐率较高、占用硬件资源较多且资源消耗量大等缺点,提出了利用混合CORDIC算法,将角度旋转分为单向角度旋转和一次角度估计旋转两部分.本文根据欠阻尼理论,将固定角度旋转采用单向旋转CORDIC算法实现,减少了流水线的级数和迭代符号位的判决,然后通过对角度估计旋转的二进制表示,修正常数因子,再根据角度映射关系进行相关处理,完成高速高精度坐标旋转.最后在硬件平台上进行了仿真实验.实验结果表明,在误差范围一定的前提下,混合算法进一步的减少了迭代次数,并且资源消耗较低,提高了数据吞吐率.     

基于CORDIC旋转器的基-3 FFT算法高效设计

设计出一种可以用于FPGA高效实现的基-3 FFT算法,采用改进的三端前馈延迟转换器结构,优化了延迟和运算过程。针对蝶形运算中复数乘法器占据大量内存的问题,引入了CORDIC旋转器实现输入与旋转因子相乘的运算,可以降低乘法运算的复杂度,该CORDIC旋转器采用改进的高基CORDIC算法,解决了传统的CORDIC算法迭代次数多、延迟大的问题,从而达到高吞吐率要求。该基-3 FFT算法以寻址变序、流水处理的方式,可以满足最高运行频率为404 MHz的FFT处理要求。与基于传统复数乘法器的基-3 FFT算法相比,基于CORDIC旋转器的基-3 FFT算法使功耗平均减少了22%,使总延迟平均减少了29%。     

基于改进Scaling-Free CORDIC算法的DDS

直接数字频率合成器(Direct Digital Synthesizer,DDS)在现代数字通信系统中有非常重要的应用。基于CORDIC算法的DDS在高速、高精度信号源领域已得到广泛应用,但传统的CORDIC算法存在迭代次数多、硬件消耗资源大、缩放因子补偿误差等问题。文章提出固定角度的传统迭代预旋转和分段双步SF(Scaling-Free)CORDIC算法旋转方式,有效减少了算法的迭代次数,并且采用区间映射将收敛区间扩展到[0,2π]。结果表明,该算法在保持高计算精度的同时减少了迭代次数和面积消耗。基于此算法的DDS产生的正交信号具有精度高、噪声低、线性度好等优点。     

基于改进CORDIC算法的DDFS设计

设计了一种基于改进CORDIC算法的直接数字式频率合成器(DDFS)。在CORDIC算法的基础上,采用角度重编码来进行迭代方向预测,避免了传统算法中迭代方向需要由剩余角度与输入角度反复比较的不足;运用少数比特迭代法,对迭代过程进行优化,减少了迭代次数,降低了传统CORDIC算法的运算量。     

改进型CORDIC算法的研究与实现

CORDIC的运算速度问题是研究的热点。为了解决CORDIC运算速度慢的问题,采用跳过零点思想,跳过输入相位值中为0的位,有效的减少了迭代次数。利用ISE仿真技术多次仿真综合。验证出改进型的CORDIC算法,在保证算法的运算精度基础上,明显地改善了CORDIC的运算速度,尤其针对于一些特殊的旋转角度,利用极少的旋转就达到结果。最终利用FPGA实现改进后CORDIC算法。     

CORDIC算法的一种补码实现结构设计

根据CORDIC算法原理,分析了该算法角度旋转范围缺陷,提出360°覆盖的角度旋转算法结构;推导出利用补码实现CORDIC算法的迭代运算单元结构,并根据该补码运算原理设计了CORDIC补码迭代运算单元和方向向量发生器的实现结构.     

多模式CORDIC算法结构改进与实现

本文对计算反正余弦函数的CORDIC算法的迭代结构进行了改进,并在此基础上完成多模式CORDIC算法的实现.通过重新设定初始旋转向量避免了前两级迭代,通过修改向量旋转方向的判决条件对原算法的误差进行了校正,在增加了很少资源的情况下将正余弦运算和反正余弦运算统一到同样的迭代结构中并予以实现.实现结果表明改进后的算法反正余弦运算结果有更高的运算精度,在两种运算函数都需要的应用中能够有效减少的硬件资源占用.     

基于FPGA的CORDIC算法实现

针对传统CORDIC算法延时大,消耗资源多的缺点,在平行CORDIC算法的基础上提出了一种优化的平行算法,利用二进制转两极算法和微旋转角度编码对低部和高部的旋转方向进行预测,并在高部旋转中利用正反旋转抵消的策略来进一步减少旋转次数,提高运算速度。采用FPGA对提出的算法进行了硬件设计和验证,结果表明,计算迭代次数少,资源消耗少,精度较传统算法来说都有了明显改善。     

Para-CORDIC: parallel CORDIC rotation algorithm

In this paper, the parallel COrdinate Rotation DIgital Computer (CORDIC) rotation algorithm in circular and hyperbolic coordinate is proposed. The most critical path of the conventional CORDIC rotation lies in the determination of rotation directions, which depends on the sign of the remaining angle after each iteration. Using the binary-to-bipolar recoding (BBR) and microrotation angle recoding techniques, the rotation directions can be predicted directly from the binary value of the initial input angle. The original sequential CORDIC rotations can be divided into two phases where the rotations in each phase can be executed in parallel. Our proposed architectures have a more regular and simpler prediction scheme compared to previous approaches. The critical path delay is reduced since the concurrently predicted rotations can be combined using multioperand carry-save addition structures.     

基于改进混合式CORDIC算法的 直接数字频率合成器设计

 提出一种新的面积优化的直接数字频率合成器设计方案.采用改进混合式CORDIC算法,通过削减旋转相位判断电路和乘法单元,改进和调整相位旋转误差,并利用简单的移位和加/减电路完成复杂的幅度修正,降低了电路复杂度,缩减了电路规模.结构上采用流水线式多级循环迭代技术,实现移位和加/减电路的高度复用.实验结果表明本方法输出频谱杂散小于-70dB,并在运算速度和资源利用率上具有一定的优势.该设计已成功用于宽带网络SoC芯片的频率调制模块.     

Ultra Low Phase Noise DSP Oscillator [DSP Tips & Tricks]

This article describes a novel complex oscillator, which is based on an interesting variation of the traditional CORDIC DDS and produces sine and cosine output samples of any specified angle. Our oscillator provides drastically improved phase noise performance (relative to a traditional CORDIC DDS) without the need for additional CORDIC iteration processing. In addition, our oscillator supports real-time output sample-by-sample digital frequency control. In describing our enhanced complex oscillator, we first present the arithmetic processing needed to generate sine and cosine samples. Next we show how that processing is implemented using the CORDIC algorithm. Then we detail the trick used to reduce oscillator phase noise errors. Finally we show how to guarantee a stable oscillator output amplitude and present an example of our oscillator's ultra low phase noise performance.     

Mixed-radix,virtually scaling-free CORDIC algorithm based rotator for DSP applications

In this work, we proposed a novel Coordinate Rotation DIgital Computer (CORDIC) rotator algorithm that converges faster by performing radix-2,4 and 16 CORDIC iterations while maintaining the scale factor implicitly constant. A mixed-radix is used to achieve convergence faster to reduce the computational latency of the CORDIC algorithm. The main concern of the higher radix CORDIC algorithm is the compensation of a variable scale factor. To solve this problem, the Taylor series approximation of sine and cosine is proposed for a higher radix CORDIC algorithm to achieve the scaling-free rotation of the two-dimensional vector. The scaling-free rotation of the proposed CORDIC algorithm removes the read-only memory (ROM) needed to store scale factor of higher radix CORDIC algorithm. Further, the proposed CORDIC algorithm is designed in rotation mode and optimized by removing the Z datapath for the digital signal processing (DSP) applications for which the angle of rotation is known in advance. Finally, the multipath delay commutator (MDC) fast Fourier transform (FFT) algorithm is implemented with the proposed CORDIC algorithm based rotator on FPGA. The proposed design is compared with existing designs. In a comparison between the radix-16 CORDIC rotator based FFT implementation and our proposed implementation, it has been found out that implementation proposed in this article has used 17% fewer resources.     

改进型高速高精度CORDIC算法及其在DDFS中的应用

提出了一种新的选择迭代式高速高精度CORDIC（COrdinate Rotation Digital Computer）算法.基于表驱动法缩小目标旋转角度,通过改进的基本角度选择方法旁路不必要的迭代;并以移位和减法实现幅度校正,减小硬件资源消耗.设定角度误差小于10^-5rad时,迭代次数减小至7次以下.在DDFS（Direct Digital Frequency Synthesizer）的应用中,利用区间压缩技术在Xilinx的FPGA中实现20位定点小数电路设计.仿真及实测结果表明,该算法幅度误差小于2×10^-5,输出延时不大于43.5ns,同时硬件资源消耗不增加.     

Radix-4 Vectoring CORDIC Algorithm and Architectures

In this work we extend the radix-4 CORDIC algorithm to the vectoring mode (the radix-4 CORDIC algorithm was proposed recently by the authors for the rotation mode). The extension to the vectoring mode is not straightforward, since the digit selection function is more complex in the vectoring case than in the rotation case; as in the rotation mode, the scale factor is not constant. Although the radix-4 CORDIC algorithm in vectoring mode has a similar recurrence as the radix-4 division algorithm, there are specific issues concerning the vectoring algorithm that demand dedicated study. We present the digit selection for nonredundant and redundant arithmetic (following two different approaches: arithmetic comparisons and table look-up), the computation and compensation of the scale factor, and the implementation of the algorithm (with both types of digit selection) in a word-serial architecture. When compared with conventional radix-2 (redundant and non-redundant) architectures, the radix-4 algorithms present a significant speed up for angle calculation. For the computation of the magnitude the speed up is very slight, due to the nonconstant scale factor in the radix-4 algorithm.     

一种新的快速并行结构的优化CORDIC算法

对传统的CORDIC算法进行改进,采用角度二进制低位转换成两极的模式和基本角度线性编码方式,更易于确定旋转方向,加快迭代速度。迭代过程中低位采用最高非零位最大逼近角的算法,高位采用基于4∶2压缩器的高速进位加法器的结构,在精度提高时其速度优势更加明显。实现结构采用流水线方式,不需要ROM存储空间,节省逻辑资源,满足高速高精度领域的运算要求。     

一种低复杂度的降低MIMO—OFDM峰平比的CARI方法

天线旋转取反算法(CARI)是降低MIMO-OFDM系统峰平功率比(PAPR)的一种性能较优的算法,不足之处是其迭代次数很大。CARI的次最优算法逐次次最优天线旋转取反(SS-CARI)算法虽然可以减小迭代次数,但性能损失又比较大。针对这一问题,提出了一种用滑动窗搜索旋转取反组合的次最优CARI方法,利用滑动窗搜索局部最优的旋转取反组合,既可以避免整体的遍历搜索大大减小CARI算法的计算复杂度,又可以改善SS-CARI的PAPR减小性能。仿真结果表明,该方法能够在系统复杂度与PAPR降低性能上取得很好的折衷。