一种用于数字集成系统的新型CMOS三态缓冲器的设计

三态逻辑电路已被广泛应用于VLSI数字集成系统中.现在也有很多种实现三态逻辑的方法,但它们要么输出驱动能力不足够强要么占有较大的器件面积.在研究传统三态缓冲器的基础上设计了一种新型的三态缓冲器,据我们所知,这是使用晶体管数目最少的一种三态缓冲器结构.通过SPICE仿真实验表明,所设计的三态缓冲器与传统三态缓冲器相比具有更优的面积-延时积特性和更低的静态功耗.     

A 12-GHz Fully Integrated Cascode CMOS LC VCO With Q-Enhancement Circuit

A fully integrated complementary metal oxide semiconductor (CMOS) cascode LC voltage controlled oscillator (VCO) with Q-enhancement technique has been designed for high frequency and low phase noise. The symmetrical cascode architecture is implemented with negative conductance circuit for improving phase noise performance in 0.18 mum CMOS technology. The measured phase noise is -110.8 dBc/Hz at the offset frequency of 1 MHz. The tuning range of 630 MHz is achieved with the control voltage from 0.6 to 1.4 V. The VCO draws 4.5 mA in a differential core circuit from 1.8 V supply.     

一种全集成型CMOS LDO线性稳压器设计

设计了一种基于0.25μm CMOS工艺的低功耗片内全集成型LDO线性稳压电路。电路采用由电阻电容反馈网络在LDO输出端引入零点,补偿误差放大器输出极点的方法,避免了为补偿LDO输出极点,而需要大电容或复杂补偿电路的要求。该方法电路结构简单,芯片占用面积小,无需片外电容。Spectre仿真结果表明：工作电压为2.5 V,电路在较宽的频率范围内,电源抑制比约为78 dB,负载电流由1 mA到满载100 mA变化时,相位裕度大于40°,LDO和带隙电压源的总静态电流为390μA。     

一种新型的基于半模基片集成波导技术的Butler矩阵

提出并实现了一种新型的基于半模基片集成波导技术的Buffer矩阵,实际制作的样品工作在X波段(10GHz),实测插入损耗为2dB,样品尺寸为24cmx6.5cm.采用了标准的双面PCB工艺,该结构与传统的微带电路相比具有插入损耗低、功率容量大等特点,与基片集成波导相比具有面积小的优点,是一种适合于在微波毫米波频段多波束天线使用的波束形成网络.文中给出了具体设计过程和测试结果.     

16.6- and 28-GHz Fully Integrated CMOS RF Switches With Improved Body Floating

This paper presents two fully integrated CMOS transmit/receive (T/R) switches with improved body-floating operations. The first design exploits an improved transistor layout with asymmetric drain-source region, which reduces the drain-source feed-through for body-floated RF switches. In the second design, a switched body-floating technique is proposed, which reconfigures the body-floating condition of a switch transistor in the ON and OFF states. Both designs are fabricated in a standard 0.13-mum triple-well CMOS process. With regard to 2-dB insertion loss, the switch with asymmetric drain-source achieves 28-GHz bandwidth, which is among the highest reported frequencies for CMOS T/R switches. The bandwidth of the switched body-floating design is 16.6 GHz. There is approximately 5 dB better isolation obtained in the switched body-floating design. With the resistive double-well body-floating technique, 26.5- and 25.5-dBm input 1-dB compression point (P_1dB) are obtained, respectively. Both designs consume only 150 mum times 100 mum die area. The demonstrated T/R switches are suitable for high-frequency and wideband transceivers.     

一种5.7 GHz CMOS 全集成低噪声放大器的设计

提出并设计了一种可以完全单片集成的5.7 GHz低噪声放大器(LNA)。该电路结构利用MOSFET自身的栅寄生电阻,通过简单的LC网络变换实现输入匹配;并采用跨阻结构,实现输出匹配。该电路采用TSMC 0.35μm CMOS工艺,用ADS模拟软件进行分析与优化。结果表明,设计的低噪声放大器,其增益为11.34 dB,噪声系数为2.2 dB,功耗12 mW,输入反射系数-33dB,线性度-4 dBm。     

1.2 GHz CMOS全集成锁相环的设计

在分析影响锁相环性能的各种因素的基础上,采用相应的优化方法设计了一款全集成的1．2GHz LC锁相环。详细介绍了该锁相环中各模块电路（包括LC型压控振荡器,预分频器,分频器,鉴频／鉴相器,含有带隙基准电流源的电荷泵以及片上无源滤波器等）的设计,并且给出了仿真结果。该锁相环采用SMIC0．18μm RF CMOS工艺设计实现,其中无源滤波器也集成在片上,实现了完全片上集成。     

2.45 GHz全集成CMOS功率放大器设计

在一个RF收发机系统中,功率放大器的集成问题一直是难点之一.首先简要介绍开关模式功率放大器及其提高效率的理论基础,然后采用0.18 μm CMOS工艺给出了工作在2.45 GHz的全集成单片功率放大器的设计,并采用ADS仿真软件验证了设计的正确性.     

一种全集成CMOS数字电视调谐器射频前端

设计了一种全集成CMOS数字电视调谐器(DTV tuner)射频前端电路.该电路采用二次变频低中频结构,集成了低噪声放大器、上变频混频器、下变频混频器等模块.芯片采用0.18μm CMOS工艺实现,测试结果表明,在50～860MHz频率范围内,射频前端能够实现很好的输入阻抗匹配,并且总的增益变化范围达到20dB.其中,在最大增益模式下,电压增益为+33dB,单边带噪声系数(SSB NF)为9.6dB,输入参考三阶交调点(ⅡP3)为-11Bm;在最小增益模式下,电压增益为+14dB,单边带噪声系数为28dB,输入参考三阶交调点为+8dBm.射频前端电路面积为1.04mm×0.98mm,工作电压为1.8V,消耗电流为30mA.     

一种全集成CMOS数字电视调谐器射频前端

设计了一种全集成CMOS数字电视调谐器(DTV tuner)射频前端电路.该电路采用二次变频低中频结构,集成了低噪声放大器、上变频混频器、下变频混频器等模块.芯片采用0.18μm CMOS工艺实现,测试结果表明,在50～860MHz频率范围内,射频前端能够实现很好的输入阻抗匹配,并且总的增益变化范围达到20dB.其中,在最大增益模式下,电压增益为 33dB,单边带噪声系数(SSB NF)为9.6dB,输入参考三阶交调点(ⅡP3)为-11Bm;在最小增益模式下,电压增益为 14dB,单边带噪声系数为28dB,输入参考三阶交调点为 8dBm.射频前端电路面积为1.04mm×0.98mm,工作电压为1.8V,消耗电流为30mA.     

A 2.4-GHz 24-dBm SOI CMOS Power Amplifier With Fully Integrated Reconfigurable Output Matching Network

In this paper, the potential of load adaptation for enhanced backoff efficiency in RF power amplifiers (PAs) has been investigated through a 0.13-mum silicon-on-insulator (SOI) CMOS fabrication technology. The RF power performance of the adopted SOI CMOS process has been preliminarily characterized by on-wafer load-pull measurements on a custom unit power transistor. A 2.4-GHz 24-dBm 2-V SOI CMOS PA with fully integrated reconfigurable output matching network has then been designed and experimentally characterized. A significant efficiency improvement of up to 34% has been achieved through load adaptation, peak efficiency being as high as 65%. Linear operation has also been demonstrated under two-tone excitation, as a 16-dBm output power has been attained while complying with a - 40-dBc third-order intermodulation distortion specification.     

全集成2.4 GHz CMOS对称式收发开关的设计

文章设计了一种应用于无线通信的2．4GHz全集成对称式串并型射频收发开关，详细分析了影响这种射频收发开关性能的各种因素，并采用了相应的优化方案。经仿真，在2．5V电压下获得了插入损耗1．0dB、隔离度30．5dB和1dB压缩点为16．1dBm的较好结果。该开关采用TSMC0．25μm工艺设计实现，版图面积(包括pad)为0．6mm^2。     

Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications

CMOS transmit-receive (T/R) switches have been integrated in a 0.18-/spl mu/m standard CMOS technology for wireless applications at 2.4 and 5.2 GHz. This switch design achieves low loss and high linearity by increasing the substrate impedance of a MOSFET at the frequency of operation using a properly tuned LC tank. The switch design is asymmetric to accommodate the different linearity and isolation requirements in the transmit and receive modes. In the transmit mode, the switch exhibits 1.5-dB insertion loss, 28-dBm power, 1-dB compression point (P/sub 1dB/), and 30-dB isolation, at 2.4 and 5.2 GHz. In the receive mode, the switch achieves 1.6-dB insertion loss, 11.5-dBm P/sub 1dB/, and 15-dB isolation, at 2.4 and 5.2 GHz. The linearity obtained in the transmit mode is the highest reported to date in a standard CMOS process. The switch passes the 4-kV Human Body Model electrostatic discharge test. These results show that the switch design is suitable for narrow-band applications requiring a moderate-high transmitter power level (<1 W).     

一个应用于探测生理信号SoC中的CMOS全集成高线性度低噪声上变频器设计

本文设计一款用于探测生理信号SoC芯片中的5GHz双边带上变频器.该混频器基于传统的吉尔伯特单元,采用交流耦合current-bleeding结构以及三阶非线性失真抵消技术抑制非线性.通过将跨导级晶体管偏置在不同的工作区域(transconductance-boost结构),使得带内变频损失小于5dB而IIP3介于22.3dBm到39.8dBm,而且双边带噪声指数小于8.2dB.应用全差分结构和感性源极钝化,再次抑制了二阶以及三阶失真.全部上变频器在1.2V供电条件下总功耗为8.4mW.     

全集成CMOS SCA接收机单片化探讨

本文对调频副载波(SCA)广播接收机的单片化设计进行了探讨,提出了一种新的适合CMOS工艺的全集成SCA接收机结构。接收机采用Weaver-零中频结构实现下变频和二次解调功能,节省了片外镜像抑制滤波器,大大提高了接收机的集成度,降低了接收机的成本和功耗,显示了广阔的潜在应用前景。     

一种粒子探测器的CMOS读出电路设计

提出了新型的应用于粒子探测器CMOS读出电路中的电荷灵敏放大器和CR-(RC)n半高斯整形器的结构.电荷灵敏放大器采用多晶硅电阻做反馈来减小噪声,仿真发现与传统结构相比,在探测器电容高达150pF时,输入等效噪声电荷数由5036个电子减小到2381个,代价是输出摆幅减小了0.5V.在整形器中,MOS管电阻与多晶硅电阻串联,通过调节MOS管的栅压来改变阻值,以补偿工艺的偏差,在不明显降低线性度的情况下保证了时间常数能够比较精确控制.     

用于无线局域网的CMOS射频前端发送器

介绍了一种用于802.11b无线局域网的高线性度射频前端发送器的设计与实现。该发送器采用直接转换结构,从而最大程度地减小了所需的片外和片上元件。电路采用0.18μmCMOS工艺实现。发送器包括两个低通滤波器、一个单边带混频器、一个功率预放大器和一个产生正交本振信号的除2分频器。发送器能够以3 dB一级提供12 dB的增益控制,输出1 dB压缩点为7.7 dBm,正常输出功率为2 dBm。整个发送器工作时消耗电流40 mA,工作电压1.8 V,芯片面积(不包括焊盘)为1.8 mm×1.5 mm。     

一种粒子探测器的CMOS读出电路设计

提出了新型的应用于粒子探测器CMOS读出电路中的电荷灵敏放大器和CR-(RC)n半高斯整形器的结构.电荷灵敏放大器采用多晶硅电阻做反馈来减小噪声,仿真发现与传统结构相比,在探测器电容高达150pF时,输入等效噪声电荷数由5036个电子减小到2381个,代价是输出摆幅减小了0.5V.在整形器中,MOS管电阻与多晶硅电阻串联,通过调节MOS管的栅压来改变阻值,以补偿工艺的偏差,在不明显降低线性度的情况下保证了时间常数能够比较精确控制.     

A Fully Embedded 60-GHz Novel BPF for LTCC System-in-Package Applications

In this paper, a novel LTCC stripline (SL) 60-GHz band-pass filter (BPF) composed of transitions to coplanar waveguide (CPW) pads for monolithic microwave integrated circuit integration is presented. For low-loss interconnection with active devices, a CPW-to-SL vertical via transition integrating air cavities and a CPW-to-CPW planar transition using internal ground planes are proposed and implemented. The fabricated transition shows an insertion loss of 1.6 dB and a reflection loss below -20 dB at the passband of the filter. The implemented SL BPF using dual-mode patch resonators shows a center frequency of 60.4 GHz, 3.5 % bandwidth, and reflection losses below -15 dB at the passband. Excluding the insertion loss of the transitions, the filter insertion loss reveals 4.0 dB     

Ultra-Compact High-Linearity High-Power Fully Integrated DC–20-GHz 0.18-μm CMOS T/R Switch

A fully integrated ultra-broadband transmit/receive (T/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an extremely wide bandwidth. Negative bias to the bulk or positive bias to the drain of the MOSFET devices with floating bulk is used to reduce effects of the parasitic diodes, leading to enhanced linearity and power handling for the switch. Within dc-10, 10-18, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0, and 2.5 dB and isolation between 32-60, 25-32, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. The new CMOS T/R switch has a die area of only 230 mumtimes250 mum. The achieved ultra-broadband performance and high power-handling capability, approaching those achieved in GaAs-based T/R switches, along with the full-integration ability confirm the usefulness of switches in CMOS technology, and demonstrate their great potential for many broadband CMOS radar and communication applications