Cu contact on NiSi/Si with thin Ru/TaN barrier

Thin Ru(5 nm)/TaN(15 nm) bi-layer was sputtered on the NiSi/Si substrate as a diffusion barrier in the copper contact structure. The barrier properties were investigated through X-ray diffraction (XRD), X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), energy dispersive X-ray (EDX) and electrical measurement. The whole Cu/Ru/TaN/NiSi/Si structure has a good thermal stability until after annealing at 450 °C. The Schottky barrier measurement shows that the leakage current increases after 450 °C annealing and after 500 °C annealing the barrier fails. Failure mechanism of the barrier stack is discussed.     

Comparison of PVD, PECVD & PEALD Ru(-C) films as Cu diffusion barriers by means of bias temperature stress measurements

The diffusion barrier properties of PVD Ru and PECVD / PEALD Ru-C films, deposited by RuEtcp₂ precursor and N₂/H₂ plasma, were compared on the basis of bias temperature stress measurements. An MIS test structure was used to distinguish between thermal diffusion induced by annealing and a Cu field drift due to applied electric fields. BTS-CV, TZDB and TDDB measurements revealed that the barrier performance is significantly better for PEALD and PECVD Ru-C films. This improvement is associated with carbon impurities in the Ru films with a concentration in the order of several percent according to ToF-SIMS and ERDA. The TDDB mean time to failure at 250 °C, +5 MV/cm was 7 s for PVD Ru samples, ≈500 s for PECVD Ru-C, ≈800 s for PEALD Ru-C and >3600 s for PVD TaN. Triangular voltage sweep measurements at 300 °C, 0.1 V/s confirmed the presence of Cu ions inside the SiO₂ for degraded dots, in contrast to the Al reference sample and to PVD TaN, which performed best among all the Cu barriers under test. XRD data suggests that PEALD and PECVD Ru-C films are only weakly crystalline.     

Cu contact on NiSi substrate with a Ta/TaN barrier stack

The thermal and electrical stabilities of Cu contact on NiSi substrate with and without a Ta/TaN barrier stack in between were investigated. Four-point probe (FPP), X-ray diffraction (XRD), scanning electron microscopy (SEM), depth-profiling X-ray photoelectron spectroscopy (XPS), and Schottky barrier height (SBH) measurement were carried out to characterize the diffusion barrier properties. The SBH measurement provides a very sensitive method to characterize the diffusion barrier properties for the copper contact on NiSi/Si. The results show that the Ta/TaN stack can be both thermally and electrically stable after annealing at 450 °C for 30 min and it will have a potential application as a diffusion barrier for Cu contact on NiSi.     

ALD-grown seed layers for electrochemical copper deposition integrated with different diffusion barrier systems

The deposition of Cu seed layers for electrochemical Cu deposition (ECD) via atomic layer deposition (ALD) of copper oxide and subsequent thermal reduction at temperatures between 110 and 120 °C was studied on different diffusion barrier systems. While optimization of the process is required on TaN with respect to reduction and plating, promising results were obtained on blanket PVD Ru. The plating results on layers of ALD Cu with underlying Ru even outperformed the ones achieved on PVD Cu seed layers with respect to morphology and resistivity. Applying the processes to via and line patterns gave similar results, suggesting that a combination of ALD Cu with PVD or ALD-grown Ru could significantly improve the ECD Cu growth.     

The effect of Si addition and Ta diffusion barrier on growth and thermal stability of NiSi nanolayer

Formation and thermal stability of nanothickness NiSi layer in Ni(Pt 4 at.%)/Si(1 0 0) and Ni_0.6Si_0.4(Pt 4 at.%)/Si(1 0 0) structures have been investigated using magnetron co-sputtering deposition method. Moreover, to study the effect of Si substrate in formation of NiSi and its thermal stability, we have used Ta diffusion barrier between the Ni_0.6Si_0.4 layer and the Si substrate. Post annealing treatment of the samples was performed in an N₂ environment in a temperature range from 200 to 900 °C for 2 min. The samples were analyzed by four point probe sheet resistance (R_s) measurement, X-ray diffraction (XRD) and atomic force microscopy (AFM) techniques. It was found that the annealing process resulted in an agglomeration of the nanothickness Ni(Pt) layer, and consequently, phase formation of discontinuous NiSi grains at the temperatures greater than 700 °C. Instead, for the Ni_0.6Si_0.4(Pt)/Si structure, 100 °C excess temperature in both NiSi formation and agglomeration indicated that it can be considered as a more thermally stable structure as compared with the Ni(Pt 4 at.%)/Si(1 0 0) structure. XRD, AFM and R_s analyses confirmed formation of a continuous NiSi film with R_s value of 5 Ω/□ in a temperature range of 700−800 °C. Use of Ta diffusion barrier showed that the role of diffusion of Ni atoms into the Si substrate is essential in complete silicidation of a NiSi layer.     

A DRAM compatible Cu contact using self-aligned Ta-silicide and Ta-barrier

As an alternative to W contacts currently used in MOSFETs for DRAM, Cu contacts using self-aligned Ta-silicide and Ta-based barrier were studied experimentally. The silicidation of PVD Ta layers was studied first on 300 mm blanket Si wafers. The developed method was applied to patterned wafers in the contacts, that land on poly gate and active areas of NMOS, with a sequence including the PVD of Ta, a silicidation annealing, a Ta-based Cu diffusion barrier and a Cu seed for plating the Cu plug. X-ray diffraction (XRD), X-ray reflection (XRR) and sheet resistance tests of the blanket wafers show that a Ta layer of about 10 nm reacts with Si substrate and forms TaSi₂ at 650 °C in a reducing ambient. Cross-sectional SEM observation reveals that the selected processing flow fills the 90 nm contacts. Top-view SEM observation on the samples after 420 °C sintering demonstrates that the Cu diffusion barrier is effective. I_on-I_off curves of the devices show a performance for NMOS comparable to the reference samples which use Ni(Pt)Si and the same barrier and Cu contacts, indicating that the stack of the barrier/TaSi₂/p-type Si has a contact resistance comparable to the barrier/Ni(Pt)Si/p-type Si.     

Self-aligned n-channel GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using HfO2 and silicon interface passivation layer: Post-metal annealing optimization

In this work, using Si interface passivation layer (IPL), we demonstrate n-MOSFET on p-type GaAs by varying physical-vapor-deposition (PVD) Si IPL thickness, S/D ion implantation condition, and different substrate doping concentration and post-metal annealing (PMA) condition. Using the optimized process, TaN/HfO₂/GaAs n-MOSFETs made on p-GaAs substrates exhibit good electrical characteristics, equivalent oxide thickness (EOT) (∼3.7 nm), frequency dispersion (∼8%) and high maximum mobility (420 cm²/V s) with high temperature PMA (950 °C, 1 min) and good inversion.     

Reliability of multistacked tantalum-based structure as the barrier film in ultralarge-scale integrated metallization

Diffusion barrier properties of Ta films with and without plasma treatments have been investigated in the study. The nitrogen-incorporated Ta films were prepared by NH₃ plasma treatment or reactive sputtering. Barrier properties were evaluated by sheet resistance, X-ray diffraction, transmission electron microscopy, X-ray photoelectron spectroscopy and reverse-biased junction leakage current. An amorphous-like TaN_x layer was formed on Ta barrier film after plasma treatments. The thickness of the amorphous TaN_x layer is about 3 nm and NH₃ plasma-treated Ta films (TaN_x/Ta) possess lower resistivity and smaller grain sizes. The Cu/TaN_x/Ta(10 nm)/Si remained stable after annealing at 750 °C for 1 h. NH₃ plasma-treated Ta films (TaN_x/Ta) possess better thermal stability than Ta and TaN films. It is attributed to the formation of a new amorphous layer on the surface of Ta film after the plasma treatments. For thermal stability of Cu/Ta(-N)/n⁺-p diodes, Cu/Ta/n⁺-p and Cu/TaN/n⁺-p junction diodes resulted in large reverse-bias junction leakage current after annealing at 500 and 525 °C, respectively. On the other hand, TaN_x/Ta diffusion barriers will improve the integrity of Cu/Ta(-N)/n⁺-p junction diodes to 650 °C.     

Barrier and seed repair performance of thin RuTa films for Cu interconnects

Thin (<4 nm) Physical Vapor Deposited (PVD) Ru-10 at.% Ta films were evaluated as diffusion barriers and seed enhancement layers for Cu metallization in sub 25 nm trenches. The ratio of Ru/Ta on blanket wafers could be influenced by changing the process conditions. However, a difference in Ru/Ta ratio did not influence the thermal stability of the layers during High Temperature X-ray Diffraction (HT-XRD) measurements as all RuTa films exhibited good thermal properties since no Cu-silicide formation was observed for temperatures below 500 °C. The RuTa films also passed an 85 °C/85% relative humidity (RH) test of one week of storage in order to test the H₂O barrier integrity of the films. Furthermore no difference was found when testing the O₂ barrier integrity during 300 s anneals at various temperatures between 250 °C and 500 °C. Good Cu fill of 20 nm trenches (AR 4:1) patterned in oxide was achieved when combining the RuTa films with PVD Cu seed layers with thicknesses ranging from 7 to 20 nm and Cu plating. When compared to a Ta(N)/Ta barrier, relatively high electrical yields (60-80%) were obtained for structures with CDs <30 nm when combining RuTa films with PVD Cu seed layers as thin as 7 nm (on field), hence evidencing the seed enhancement ability of these layers.     

Barrier layer thickness analysis for reliable copper plug process in CMOS technology

Copper (Cu) replacing conventional tungsten (W) based 1st contact plug has become necessary for high performance CMOS. For a reliable and well optimized Cu plug, process selection and integration of plug diffusion barrier is an important task. In this work, we investigate barriers for Cu plug technology for CMOS process. Single layer TaN and bi-layer Ta + TaN barrier materials were studied for their effectiveness in preventing Cu diffusion into device active regions for backend thermal stress conditions. The degradation of device characteristics was used as monitor of robustness of barrier reliability. Diffusion of Cu in multilayer plug structure is modeled to explain observed stress behavior. From the model studies, the critical barrier layer thickness needed to prevent Cu diffusion is determined. We show than that a ∼7 nm sidewall barrier is effective in preventing Cu diffusion into Si at up to 350 °C/60 min only, while a minimum thickness of ∼10 nm is needed for blocking copper diffusion at 420 °C/30 min. Using multilayer Cu diffusion model, an optimized process window for reliable, low contact resistance Cu plug technology for CMOS process can be obtained.     

Annealing temperature effect on electrical and structural properties of Cu/Au Schottky contacts to n-type GaN

Schottky contacts were fabricated on n-type GaN using a Cu/Au metallization scheme, and the electrical and structural properties have been investigated as a function of annealing temperature by current-voltage (I-V), capacitance-voltage (C-V), Auger electron spectroscopy (AES) and X-ray diffraction (XRD) measurements. The extracted Schottky barrier height of the as-deposited contact was found to be 0.69 eV (I-V) and 0.77 eV (C-V), respectively. However, the Schottky barrier height of the Cu/Au contact slightly increases to 0.77 eV (I-V) and 1.18 eV (C-V) when the contact was annealed at 300 °C for 1 min. It is shown that the Schottky barrier height decreases to 0.73 eV (I-V) and 0.99 eV (C-V), 0.56 eV (I-V) and 0.87 eV (C-V) after annealing at 400 °C and 500 °C for 1 min in N₂ atmosphere. Norde method was also used to extract the barrier height of Cu/Au contacts and the values are 0.69 eV for the as-deposited, 0.76 eV at 300 °C, 0.71 eV at 400 °C and 0.56 eV at 500 °C which are in good agreement with those obtained by the I-V method. Based on Auger electron spectroscopy and X-ray diffraction results, the formation of nitride phases at the Cu/Au/n-GaN interface could be the reason for the degradation of Schottky barrier height upon annealing at 500 °C.     

Thermal and Electrical Properties of PVD Ru(P) Film as Cu Diffusion Barrier

Thermal and electrical properties of physical vapor deposition (PVD) Ru(P) film deposited on porous ultra low-k (p-ULK) material as Cu diffusion barrier were studied. The phosphorous concentration can be tuned by adjusting Ar to PH₃ ratio of the sputtering gases. The leakage current depends on phosphorous concentration. Higher phosphorous content in Ru film has lower leakage current. No obvious phosphorous content dependence was observed when the amorphous Ru(P) film crystallized. The X-ray diffraction (XRD) graphs and energy dispersive spectrometer’s (EDS) atomic depth profiles show that the Ru(P) film deposited on p-ULK can effectively block Cu diffusion when the sample is subjected to 800 °C 5 min annealing. The phosphorous doped Ru film improves diffusion barrier properties and leakage current performance. The improved Ru(P) barrier capable of direct Cu plating could be a potential candidate for advanced metallization.     

Enhancement of adhesion strength of Cu layer with low dielectric constant SiC:H liners in Cu interconnects

One of the primary candidates for the liner/etch stop layer in damascene process is silicon nitride (Si₃N₄). However, silicon nitride has a high dielectric constant of 7.0. To reduce the effective dielectric constant in Copper (Cu) damascene structure, dielectric SiC:H (prepared by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane source) as the Cu diffusion barrier was studied. The dielectric constant of SiC:H used is 4.2. A systematic study was made on the properties of liner material and electro-chemically plated (ECP) Cu to enhance the adhesion strength in Cu/low-dielectric constant (k) multilevel interconnects. Though the effects of as Si₃N₄ the liner have been much studied in the past, less is known about the relation between adhesion strength of ECP Cu layer and physical vapor deposited (PVD) Cu seeds, with seed thickness below 1000 Å. The annealing of Cu seed layer was carried out at 200 °C in N₂ ambient for 30 min was carried out to study the impact on adhesion strength and the microstructure evolution on the adhesion between ECP Cu and its barrier layer. In the study, our claim that SiC:H barrier/etch stop layer is essential for replacing conventional Si₃N₄ layer in enhancing adhesion strength and interfacial bonding between Cu/dielectric interconnects.     

Hf-O-N and HfO2 barrier layers for Hf-Ti-O gate dielectric thin films

Hf-O-N and HfO₂ thin films were evaluated as barrier layers for Hf-Ti-O metal oxide semiconductor capacitor structures. The films were processed by sequential pulsed laser deposition at 300 °C and ultra-violet ozone oxidation process at 500 °C. The as-deposited Hf-Ti-O films were polycrystalline in nature after oxidation at 500 °C and a fully crystallized (o)-HfTiO₄ phase was formed upon high temperature annealing at 900 °C. The Hf-Ti-O films deposited on Hf-O-N barrier layer exhibited a higher dielectric constant than the films deposited on the HfO₂ barrier layer. Leakage current densities lower than 5 × 10 A/cm² were achieved with both barrier layers at a sub 20 Å equivalent oxide thickness.     

Screening self-assembled monolayers as Cu diffusion barriers

Self-assembled monolayers (SAMs) are investigated as potential Cu diffusion barriers for application in back-end-of-line (BEOL) interconnections. A screening of SAMs derived from molecules with different head group (SiCl₃, Si(OCH₃)₃, Si(OCH₃)Cl₂) bonding to the dielectric substrate, chain lengths (n = 3-21) and terminal group (CH₃, Br, CN, NH₂, C₅H₄N and SH) bonding to the Cu overlayer are compared in terms of inhibition of interfacial Cu diffusion and promotion of Cu-SiO₂ adhesion. SAM barrier properties against Cu silicide formation are examined upon annealing from 200 to 400 °C by visual inspection, sheet resistance measurements (Rs) and X-ray Diffraction Spectroscopy (XRD). Cu/SAM/SiO₂ adhesion is evaluated by tape test and four-point probe measurements. Results indicate that NH₂-SAM derived from 3-aminopropyltrimethoxysilane is the most promising for Cu diffusion barrier application. Silicide formation is inhibited to at least 400 °C, essential stability for BEOL integration. However, the 2.9 Gc (J/m²) adhesion of the layer compared with 3.1 Gc (J/m²) on SiO₂ does need improvement.     

Enhancing the reliability of n-p junction diodes using plasma treated tantalum barrier film

The properties of Ta barrier films treated with various plasma nitridations have been investigated by Cu/barrier/Si. An amorphous layer is formed on Ta barrier film after plasma treatments. The thickness of the amorphous layer is about 3 nm. Plasma treated Ta films possess better barrier performance than sputtered Ta and TaN films. It is attributed to the formation of a new amorphous layer on Ta surface after the plasma treatment. Cu/Ta(N,H)/Ta (10 nm)/Si remained stable after annealing at 750 °C. Ta(N,H)/Ta possesses the best thermal stability and excellent electrical properties. Cu/Ta/n⁺-p and Cu/Ta(N,O)/Ta/n⁺-p diodes resulted in large reverse-bias junction leakage current after annealing at 500 °C and 600 °C, respectively. On the other hand, Ta(N,H)/Ta and Ta(N)/Ta diffusion barriers improve the thermal stability of junction diodes to 650 °C. Ta(N,H)/Ta barrier film possesses lowest resistivity among Ta, Ta(N,O)/Ta, and Ta(N)/Ta films. Hydrogen plays an important role in enhancement of barrier properties. It is believed that hydrogen not only induces amorphization on Ta, but also eliminates the oxygen in the film. It is believed that the enhancement of ability against the copper diffusion is due to the combined effects of the hydrogen reaction and nitridation.     

Thermal stability of Ni silicide films on heavily doped n and p Si substrates

Electrical and structural properties of Ni silicide films formed at various temperatures ranged from 200 °C to 950 °C on both heavily doped n⁺ and p⁺ Si substrates were studied. It was found that surface morphology as well as the sheet resistance properties of the Ni silicide films formed on n⁺ and p⁺ Si substrates at the temperatures higher than 600 °C were very different. Agglomerations of Ni silicide films on n⁺ Si substrates begin to occur at around 600 °C while there is no agglomeration observed in Ni silicide films on p⁺ Si substrates up to a forming temperature of 700 °C. It was also found that the phase transition temperature from NiSi phase to NiSi₂ phase depend on substrate types; 900 °C for NiSi film on n⁺ Si substrate and 750 °C for NiSi film on p⁺ Si substrate, respectively. Our results show that the agglomeration is, especially, important factor in the process temperature dependency of the sheet resistance of Ni silicides formed on n⁺ Si substrates.     

Properties of ALD HfTaxOy high-k layers deposited on chemical silicon oxide

HfTa_xO_y high-k dielectric layers with different compositions were deposited using ALD on 1 nm SiO₂ generated by ozone based cleaning of 200 mm Si(1 0 0) surface. Physical characterization of blanket layers and C-V mapping demonstrates that the ALD layers have excellent uniformity and controllable compositions. The layers with a composition of HfTaO_5.5 remain amorphous after annealing at 900 °C. The C-V measurements of MOS capacitors show no hysteresis, negligible frequency dispersion and interfacial state density smaller than 3 × 10¹¹ (cm⁻² eV⁻¹). k-value of the amorphous layers varies in the range from 20 to 25, depending on layer composition. The flat band voltage does not shift with the increase of EOT, implying that the effect of fixed charge densities in the layers is negligible. The I-V measurements show a leakage reduction comparable to that of the ALD HfO₂ layers.     

OLED compatible water-based nanolaminate encapsulation systems using ozone based starting layer

Highly efficient nanolaminate diffusion barriers made of TiO₂/Al₂O₃ multilayers using low temperature atomic layer deposition optimized for organic light emitting diodes are presented. Water vapour transmission rates (WVTR) show values of the order of 10⁻³ g/m²/d at 38 °C, 90% RH on planarized PEN webs (pPEN) when ozone is used as the oxidizing precursor for Al₂O₃ deposition. OLED encapsulated with such diffusion barriers display few dark spots observed over 2000 h after deposition and for aging under ambient conditions. Diffusion barriers deposited using water as the oxidizing precursor for Al₂O₃ result in at least 10 times lower WVTR on pPEN webs (10⁻⁴ g/m²/d). However, these water based diffusion barriers are incompatible with OLEDs such that the latter show extensive black spot formation (areas of no visible luminescence) immediately after deposition. Finally through the growth of these initial black spots, more than 40% loss in initial luminescence occurs after merely 900 h of operation. In this report, we introduce a new methodology for OLED encapsulation using a two step process where 10 nm thick ozone Al₂O₃ based nanolaminate diffusion barrier is followed by a 90 nm thick water Al₂O₃ based diffusion barrier (keeping TiO₂ precursors always the same). With this novel diffusion barrier stack, no visible black spot growth is observed over 2000 continuous operation hours under ambient conditions. Simultaneously, high OLED luminescence representing 90% of the initial luminescence value, which is measured at t = 0 is maintained after 2000 h of operation. Low WVTR values in the 10⁻⁴ g/m²/d range on pPEN webs are consistently measured in these essentially water based barrier layers with only 10 nm thick starting ozone Al₂O₃ based nanolaminate diffusion barriers. The results reported here have implications on developing methodologies for ultra high performance, OLED compatible diffusion barriers by ALD.     

NiSi contact metallization using electroless Ni deposition on Pd-activated self-assembled monolayer (SAM) on p-type Si(1 0 0)

In this paper we describe a method to form NiSi contacts using electroless plating of Nickel or Ni alloy on Pd activated self-assembled monolayer (SAM) on p-type Si(1 0 0). Such method allows uniform deposition of very thin, <30 nm, Ni or Ni alloy films. Clean, oxide free, Si substrate was covered with aminopropyltriethoxysilane (APTES) self-assembled monolayer. The surface was activated with Pd-citrate solution followed by electroless plating. The samples were annealed for 1 h in vacuum (∼10⁻⁶ Torr) forming the silicide layer. The annealing temperatures were 400 °C for NiP alloy and 500 °C for NiPW alloy. X-ray diffraction (XRD) measurement confirmed the presence of NiSi phase after annealing. The silicides material properties were characterized using secondary electron microscopy (SEM) analysis, X-ray diffraction (XRD) and X-ray photon spectroscopy (XPS) profiling. The results are reported and summarized.