Cover Picture: Formation of Metal Nano‐ and Micropatterns on Self‐Assembled Monolayers by Pulsed Laser Deposition Through Nanostencils and Electroless Deposition (Adv. Funct. Mater. 10/2006)

The cover illustrates two‐step fabrication of metal micro‐ and nanostructures on self‐assembled monolayers (SAMs) by pulsed laser deposition and electroless deposition. Metal–SAM–metal junctions are a key component of molecular electronic devices. Pt was deposited in a micropattern by pulsed laser deposition through a stencil. XPS maps show how the Pt pattern is developed into a Cu pattern using electroless deposition as reported by Ravoo, Brugger, Reinhoudt, Blank, and co‐workers on p. 1337. The Cu pattern can also be observed by optical microscopy (background). Patterns of noble‐metal structures on top of self‐assembled monolayers (SAMs) on Au and SiO₂ substrates have been prepared following two approaches. The first approach consists of pulsed laser deposition (PLD) of Pt, Pd, Au, or Cu through nano‐ and microstencils. In the second approach, noble‐metal cluster patterns deposited through nano‐ and microstencils are used as catalysts for selective electroless deposition (ELD) of Cu. Cu structures are grown on SAMs on both Au and SiO₂ substrates and are subsequently analyzed using X‐ray photoelectron spectroscopy element mapping, atomic force microscopy, and optical microscopy. The combination of PLD through stencils on SAMs followed by ELD is a new method for the creation of (sub)‐micrometer‐sized metal structures on top of SAMs. This method minimizes the gas‐phase deposition step, which is often responsible for damage to, or electrical shorts through, the SAM.     

Formation of Metal Nano‐ and Micropatterns on Self‐Assembled Monolayers by Pulsed Laser Deposition Through Nanostencils and Electroless Deposition

Patterns of noble‐metal structures on top of self‐assembled monolayers (SAMs) on Au and SiO₂ substrates have been prepared following two approaches. The first approach consists of pulsed laser deposition (PLD) of Pt, Pd, Au, or Cu through nano‐ and microstencils. In the second approach, noble‐metal cluster patterns deposited through nano‐ and microstencils are used as catalysts for selective electroless deposition (ELD) of Cu. Cu structures are grown on SAMs on both Au and SiO₂ substrates and are subsequently analyzed using X‐ray photoelectron spectroscopy element mapping, atomic force microscopy, and optical microscopy. The combination of PLD through stencils on SAMs followed by ELD is a new method for the creation of (sub)‐micrometer‐sized metal structures on top of SAMs. This method minimizes the gas‐phase deposition step, which is often responsible for damage to, or electrical shorts through, the SAM.     

Conformal electroless deposition of Cu seed layer on a 60-nm trench pattern modified with a self-assembled monolayer

We have developed a novel activation technique for the conformal electroless deposition (ELD) of Cu on a SiO₂ substrate modified with an organic self-assembled monolayer. The SiO₂ substrate was modified with amine groups using 3-aminopropyltriethoxysilane and Au nanoparticles (AuNPs) to form a uniform, continuous catalyst for ELD. The Au catalytic layer formed on the amine-SiO₂ substrate was stabilized by electrostatic interactions between the positively charged protonated-amine self-assembled monolayer (SAM) and negatively charged AuNPs. Cu films were then electrolessly deposited on Au-catalyzed SiO₂ substrates. The Cu seed layer formed by this method showed a highly conformal and continuous structure. Cu electrodeposition on the 60-nm trench was demonstrated using an acid cupric sulfate electrolyte containing chloride, polyethylene glycol 4000 and bis(3-sulfopropyl)disulfide. The resulting electroplated Cu showed excellent filling capability and no voids or other defects were observed in a 60-nm trench pattern.     

Tunable Crystal Nanostructures of Pentacene Thin Films on Gate Dielectrics Possessing Surface‐Order Control

To enhance the electrical performance of pentacene‐based field‐effect transistors (FETs) by tuning the surface‐induced ordering of pentacene crystals, we controlled the physical interactions at the semiconductor/gate dielectric (SiO₂) interface by inserting a hydrophobic self‐assembled monolayer (SAM, CH₃‐terminal) of organoalkyl‐silanes with an alkyl chain length of C8, C12, C16, or C18, as a complementary interlayer. We found that, depending on the physical structure of the dielectric surfaces, which was found to depend on the alkyl chain length of the SAM (ordered for C18 and disordered for C8), the pentacene nano‐layers in contact with the SAM could adopt two competing crystalline phases—a “thin‐film phase” and “bulk phase” – which affected the π‐conjugated nanostructures in the ultrathin and subsequently thick films. The field‐effect mobilities of the FET devices varied by more than a factor of 3 depending on the alkyl chain length of the SAM, reaching values as high as 0.6 cm² V^?1 s^?1 for the disordered SAM‐treated SiO₂ gate‐dielectric. This remarkable change in device performance can be explained by the production of well π‐conjugated and large crystal grains in the pentacene nanolayers formed on a disordered SAM surface. The enhanced electrical properties observed for systems with disordered SAMs can be attributed to the surfaces of these SAMs having fewer nucleation sites and a higher lateral diffusion rate of the first seeding pentacene molecules on the dielectric surfaces, due to the disordered and more mobile surface state of the short alkyl SAM.     

Integration of HfxTayN metal gate with SiO2 and HfOxNy gate dielectrics for MOS device applications

Interaction of Hf_xTa_yN metal gate with SiO₂ and HfO_xN_y gate dielectrics has been extensively studied. Metal-oxide-semiconductor (MOS) device formed with SiO₂ gate dielectric and Hf_xTa_yN metal gate shows satisfactory thermal stability. Time-of-flight secondary ion mass spectroscopy (TOF-SIMS) analysis results show that the diffusion depths of Hf and Ta are less significant in SiO₂ gate dielectric than that in HfO_xN_y. Compared to HfO_xN_y gate dielectric, SiO₂ shows better electrical properties, such as leakage current, hysteresis, interface trap density and stress-induced flat-band voltage shift. With an increase in post metallization annealing (PMA) temperature, the electrical characteristics of the MOS device with SiO₂ gate dielectric remain almost unchanged, indicating its superior thermal and electrical stability.     

Screening self-assembled monolayers as Cu diffusion barriers

Self-assembled monolayers (SAMs) are investigated as potential Cu diffusion barriers for application in back-end-of-line (BEOL) interconnections. A screening of SAMs derived from molecules with different head group (SiCl₃, Si(OCH₃)₃, Si(OCH₃)Cl₂) bonding to the dielectric substrate, chain lengths (n = 3-21) and terminal group (CH₃, Br, CN, NH₂, C₅H₄N and SH) bonding to the Cu overlayer are compared in terms of inhibition of interfacial Cu diffusion and promotion of Cu-SiO₂ adhesion. SAM barrier properties against Cu silicide formation are examined upon annealing from 200 to 400 °C by visual inspection, sheet resistance measurements (Rs) and X-ray Diffraction Spectroscopy (XRD). Cu/SAM/SiO₂ adhesion is evaluated by tape test and four-point probe measurements. Results indicate that NH₂-SAM derived from 3-aminopropyltrimethoxysilane is the most promising for Cu diffusion barrier application. Silicide formation is inhibited to at least 400 °C, essential stability for BEOL integration. However, the 2.9 Gc (J/m²) adhesion of the layer compared with 3.1 Gc (J/m²) on SiO₂ does need improvement.     

Towards metal electrode interface scavenging of rare-earth scandates: A Sc2O3 and Gd2O3 study

Amorphous Gd₂O₃ and Sc₂O₃ thin films were deposited on Si by high-pressure sputtering (HPS). In order to reduce the uncontrolled interfacial SiO_x growth, firstly a metallic film of Gd or Sc was sputtered in pure Ar plasma. Subsequently, they were in situ plasma oxidized in an Ar/O₂ atmosphere. For post-processing interfacial SiO_x thickness reduction, three different top metal electrodes were studied: platinum, aluminum and titanium. For both dielectrics, it was found that Pt did not react with the films, while Al reacted with them forming an aluminate-like interface and, finally, Ti was effective in scavenging the SiO₂ interface thickness without severely compromising gate dielectric leakage.     

Ultrathin HfO2 gate dielectrics on partially strain compensated SiGeC/Si heterostructure

Ultrathin HfO₂ gate dielectrics have been deposited on strain-compensated Si_0.69Ge_0.3C_0.01 layers by rf magnetron sputtering. X-ray diffraction spectra show the films to be polycrystalline having both monoclinic and tetragonal phases. The formation of an interfacial layer has been observed by high-resolution transmission electron microscopy. Secondary ion mass spectroscopy and Auger electron spectroscopy analyses show the formation of an amorphous Hf-silicate interfacial layer between the deposited oxide and SiGeC films. The average concentration of Ge at the interfacial layer is found to be 2–3 at%. The leakage current density of HfO₂ gate dielectrics is found to be several orders of magnitude lower than that reported for thermal SiO₂ with the same equivalent thickness.     

Performance improvement of flash memory using AlN as charge-trapping Layer

Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si₃N₄) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high-k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO₂ as a blocking oxide in p-Si/SiO₂/AlN/SiO₂/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.     

Improvement in dielectric properties of low temperature PECVD silicon dioxide by reaction with hydrazine

The dielectric properties of plasma-enhanced chemical vapor deposition (PECVD) SiO₂ deposited at 150°C were improved by reaction with anhydrous hydrazine vapor at 150–350°C. The permittivity and loss decreased ~32% and ~86%, respectively, after reaction with hydrazine at 150°C. The decrease in permittivity and loss correlated with a decrease in the dipole concentration (silanol + water). During exposure to humid conditions, water uptake in the SiO₂ films degraded the dielectric properties. A nitrogen anneal at 350°C did not improve the dielectric properties of the PECVD SiO₂. Although water was removed from the films, silanol remained. When the PECVD SiO₂ deposited at 150° was reacted with hydrazine vapor at 150°C, both silanol and water were removed from the films. The dielectric properties and resistance to water absorption improved.     

Bottom‐Up Engineering of Subnanometer Copper Diffusion Barriers Using NH2‐Derived Self‐Assembled Monolayers

A 3‐aminopropyltrimethoxysilane‐derived self‐assembled monolayer (NH₂SAM) is investigated as a barrier against copper diffusion for application in back‐end‐of‐line (BEOL) technology. The essential characteristics studied include thermal stability to BEOL processing, inhibition of copper diffusion, and adhesion to both the underlying SiO₂ dielectric substrate and the Cu over‐layer. Time‐of‐flight secondary ion mass spectrometry and X‐ray spectroscopy (XPS) analysis reveal that the copper over‐layer closes at 1–2‐nm thickness, comparable with the 1.3‐nm closure of state‐of‐the‐art Ta/TaN Cu diffusion barriers. That the NH₂SAM remains intact upon Cu deposition and subsequent annealing is unambiguously revealed by energy‐filtered transmission electron microscopy supported by XPS. The SAM forms a well‐defined carbon‐rich interface with the Cu over‐layer and electron energy loss spectroscopy shows no evidence of Cu penetration into the SAM. Interestingly, the adhesion of the Cu/NH₂SAM/SiO₂ system increases with annealing temperature up to 7.2 J m^?2 at 400 °C, comparable to Ta/TaN (7.5 J m^?2 at room temperature). The corresponding fracture analysis shows that when failure does occur it is located at the Cu/SAM interface. Overall, these results demonstrate that NH₂SAM is a suitable candidate for subnanometer‐scale diffusion barrier application in a selective coating for copper advanced interconnects.     

N and P metal oxide semiconductor field effect transistor characteristics of hafnium-doped SiO2 gate dielectrics

This work presents the interfacial properties of hafnium-doped SiO₂ films via N and P metal oxide semiconductor (MOS) materials, MOS-capacitor, and N and P metal oxide semiconductor field effect transistor (MOSFET) characterization. The results indicate that HfSi_xO_y films (a) have excellent transistor characteristics; (b) remain amorphous through high-temperature processing; (c) are compatible with N+ and P+ polysilicon electrodes; (d) have lower gate leakage than SiO₂ of the same equivalent oxide thickness (EOT); and (e) have a dielectric constant of ∼8. Therefore, the hafnium-doped SiO₂ films are at-tractive as a dielectric material and offer a technologically relevant gate-stack node for insertion, prior to deployment of high-K dielectrics.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

The impact of self-assembled monolayer thickness in hybrid gate dielectrics for organic thin-film transistors

We have investigated the electrical characteristics of hybrid dielectrics with a thickness of 6 nm or less that are composed of a plasma-grown aluminum oxide (AlO_x) layer and a self-assembled monolayer (SAM) of an aliphatic phosphonic acid. The impact of the quality of the AlO_x layer on the insulating properties of the double-layer dielectrics was assessed by comparing two different oxidation procedures, and the influence of the thickness of the organic SAM was evaluated by employing molecules with five different chain lengths. In order to decouple the relative contributions of the oxide and the SAM to the performance of the double-layer dielectrics we have also performed cyclic voltammetry measurements on indium tin oxide (ITO)/SAM devices without AlO_x layer. Finally, we have evaluated how the quality of the AlO_x layer and the thickness of the SAM affect the performance of low-voltage organic thin-film transistors (TFTs) that employ the thin AlO_x/SAM dielectrics as the gate dielectric. The results confirm the important role of the SAM in determining the breakdown voltage, in limiting the current density, and in compensating the somewhat lower quality of AlO_x layers produced under mild plasma conditions.     

Mobility Enhancement in Solution‐Processed Transparent Conductive Oxide TFTs due to Electron Donation from Traps in High‐k Gate Dielectrics

High‐mobility ZnO thin films are deposited onto solution‐processed ZrO₂ dielectrics in order to investigate the large differences between experimental field‐effect mobility values obtained when transparent conductive oxide (TCO) materials are deposited onto high‐k dielectrics as opposed to thermally grown SiO₂. Through detailed electrical characterization, the mobility enhancement in ZnO is correlated to the presence of electron traps in ZrO₂ serving to provide an additional source of electrons to the ZnO. Furthermore, as a consequence of the general tendency for solution‐processed high‐k dielectrics to exhibit similar behavior, the broad applicability is suggested to other TCO/high‐k material combinations in agreement with experimental observations.     

Characterization of Self-Formed Ti-Rich Interface Layers in Cu(Ti)/Low-k Samples

In our previous studies, thin Ti-rich diffusion barrier layers were found to be formed at the interface between Cu(Ti) films and SiO₂/Si substrates after annealing at elevated temperatures. This technique was called self-formation of the diffusion barrier, and is attractive for fabrication of ultralarge-scale integrated (ULSI) interconnects. In the present study, we investigated the applicability of this technique to Cu(Ti) alloy films which were deposited on low dielectric constant (low-k) materials (SiO _x C _y ), SiCO, and SiCN dielectric layers, which are potential dielectric layers for future ULSI Si devices. The microstructures were analyzed by transmission electron microscopy (TEM) and secondary-ion mass spectrometry (SIMS), and correlated with the electrical properties of the Cu(Ti) films. It was concluded that the Ti-rich interface layers were formed in all the Cu(Ti)/dielectric-layer samples. The primary factor to control the composition of the self-formed Ti-rich interface layers was the C concentration in the dielectric layers rather than the enthalpy of formation of the Ti compounds (TiC, TiSi, and TiN). Crystalline TiC was formed on the dielectric layers with a C concentration higher than 17 at.%.     

Electromigration and integration aspects for the copper-SiLK system

In this study, the thermal characteristics and electromigration (EM) resistance of two dielectrics, SiLK™ and SiO₂, are investigated to evaluate the feasibility of low dielectric-constant SiLK for intermetal dielectric applications. Liftoff patterning was employed to fabricate the Cu interconnect for the EM test, and the Taguchi method was used in the experimental design to identify the key parameters for a successful liftoff. It was shown that the thermal impedance of the metal lines passivated with SiLK is 14% higher than that of metal lines passivated with SiO₂. On the basis of the thermal impedance and temperature rise of the interconnect, it was concluded that the major heat transfer path is via the underlayer dielectric to the Si substrate. The activation energy of EM for Cu passivated with SiLK is smaller, and the EM lifetime is shorter than that of Cu passivated with SiO₂. Possible mechanisms are discussed.     

Morphology evolution in TiN/Al-0.5Cu/Ti interconnection during chamber long stay and post-deposition annealing correlated to defect formation in metallization processing

TiN/Al-0.5Cu/Ti film stacks deposited on SiO₂ substrate were studied by X-ray diffraction and electron microscopy to clarify the effects of the chamber long stay and post-deposition annealing on the morphology evolution. Experimental results indicated that the chamber idleness at 270 °C resulted in significant Al₂Cu precipitation and hillock growth for the Al-Cu films, which enhanced the occurrence rate of the microcorrosion-induced bridging defects and caused yield degradation on production line while post-deposition annealing at 400 °C for 30 min was proven to effectively regain good yield for the chamber-idled wafers. The yield recovery could be attributed to the fast Al₂Cu dissolution and hillock mitigation at the annealing temperature. The electrical sheet resistance of the Al-Cu films would somewhat increase due to the formation of the Al₃Ti phase during annealing, but the Al₂Cu precipitates and surface hillocks formed during chamber idleness would scarcely change the electrical property of the films. This study suggests that the evolutions of second phase and surface hillocks can be controlled by the processing duration and post-deposition treatment rather than the deposition temperature or Cu addition amount of Al-Cu alloy.     

Bias-temperature stress of Al on porous low-k dielectrics

Aluminum has been perceived as a stable electrode for the reliability test of dielectric films. In this letter, using energy dispersive X-ray spectroscopy method, Al ions were detected in the dielectric after Al/SiCOH/SiO₂/Si capacitor was subjected to bias-temperature stress (BTS). We investigated the impact of the drifted Al to the stability of the dielectrics by studying the leakage current of the capacitor. We showed that the increase of leakage current after BTS falls into the Poole-Frenkel conduction regime, indicating the Al ions act as electronic traps inside SiCOH. Our results question the compatibility between Al and low-k dielectrics.