32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k = 2.3

A 32 nm node BEOL integration scheme is presented with 100 nm metal pitch at local and intermediate levels and 50 nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32 nm RC performance specifications, extreme low-k (ELK) porous SiOCH k = 2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k = 2.3 is investigated using a multi-level metallization test vehicle in a 45 nm mature generation.     

Titanium-aluminum oxynitride (TAON) as high-k gate dielectric for sub-32 nm CMOS technology

High-k insulators for the next generation (sub-32 nm CMOS (complementary metal-oxide-semiconductor) technology), such as titanium-aluminum oxynitride (TAON) and titanium-aluminum oxide (TAO), have been obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation and oxidation on Si substrates, respectively. Physical thickness values between 5.7 and 6.3 nm were determined by ellipsometry. These films were used as gate insulators in MOS capacitors fabricated with Al electrodes, and they were used to obtain capacitance-voltage (C-V) measurements. A relative dielectric constant of 3.9 was adopted to extract the equivalent oxide thickness (EOT) of films from C-V curves under strong accumulation condition, resulting in values between 1.5 and 1.1 nm, and effective charge densities of about 10¹¹ cm⁻². Because of these results, nMOSFETs with Al gate electrode and TAON gate dielectric were fabricated and characterized by current-voltage (I-V) curves. From these nMOSFETs electrical characteristics, a sub-threshold slope of 80 mV/dec and an EOT of 0.87 nm were obtained. These results indicate that the obtained TAON film is a suitable gate insulator for the next generation (MOS) devices.     

Surface properties restoration and passivation of high porosity ultra low-k dielectric (k ∼ 2.3) after direct-CMP

Surface hydrophilisation and effective k-value degradation have been reported in literature after direct-CMP of high porosity SiOC films (without a protective capping layer). In the sequel, attempts to restore ultra low-k (ULK) material initial properties after a standard CMP and post-CMP cleaning process are reported. Annealing treatment has shown to be valuable to remove residual organics and water absorbed at the ultra low-k material surface after direct-CMP. However, as the hydrophilicity of the polished surface remains unchanged, it does not prevent moisture uptake, leading to an increase in k-value with time. Therefore, in order to restore hydrophobic properties and to stabilize the surface in time, three silylating agents - containing chlorosilane reactive groups (-SiMe_nCl_3−n) as well as hydrophobic methyl functions (-CH₃) in their structure - have been employed in liquid, gas or dense CO₂ phases on the CMP-induced damaged ULK layers. While each of these organic treatments is efficient to restore hydrophobicity on post-CMP ULK surfaces, only one of them proved to be able to keep the k-value low (comparable to the ULK pristine k-value) and stable in time, without inducing significant change in porosity of the ULK material.     

Crystalline orientation dependence of electrical properties of Mn Germanide/Ge(1 1 1) and (0 0 1) Schottky contacts

We have investigated the crystalline orientation dependence of the electrical properties of Mn germanide/Ge(1 1 1) and (0 0 1) Schottky contacts. We prepared epitaxial and polycrystalline Mn₅Ge₃ layers on Ge(1 1 1) and (0 0 1) substrates, respectively. The Schottky barrier height (SBH) estimated from the current density-voltage characteristics for epitaxial Mn₅Ge₃/Ge(1 1 1) is as low as 0.30 eV, while the SBH of polycrystalline Mn₅Ge₃/Ge(0 0 1) is higher than 0.56 eV. On the other hand, the SBH estimated from capacitance-voltage characteristics are higher than 0.6 eV for both samples. The difference of these SBHs can be explained by the local carrier conduction through the small area with the low SBH regions in the epitaxial Mn₅Ge₃/Ge(1 1 1) contact. This result suggests the possibility that the lowering SBH takes place due to Fermi level depinning in epitaxial germanide/Ge(1 1 1) contacts.     

Design and analysis of a 32 nm PVT tolerant CMOS SRAM cell for low leakage and high stability

A novel nine transistor (9T) CMOS SRAM cell design at 32 nm feature size is presented to improve the stability, power dissipation, and delay of the conventional SRAM cell along with detailed comparisons with other designs. An optimal transistor sizing is established for the proposed 9T SRAM cell by considering stability, energy consumption, and write-ability. As a complementary hardware solution at array-level, a novel write bitline balancing technique is proposed to reduce the leakage current. By optimizing its size and employing the proposed write circuit technique, 33% power dissipation saving is achieved in memory array operation compared with the conventional 6T SRAM based design. A new metric that comprehensively captures all of these figures of merit (and denoted to as SPR) is also proposed; under this metric, the proposed 9T SRAM cell is shown to be superior to all other cell configurations found in the technical literatures. The impact of the process variations on the cell design is investigated in detail. HSPICE simulation shows that the 9T SRAM cell demonstrates an excellent tolerance to process variations comparing with the conventional SRAM cells.     

Frequency and temperature dependent dielectric properties of Al/Si3N4/p-Si(1 0 0) MIS structure

The dielectric properties of Al/Si₃N₄/p-Si(1 0 0) MIS structure were studied from the C-V and G-V measurements in the frequency range of 1 kHz to 1 MHz and temperature range of 80-300 K. Experimental results shows that the ε′ and ε″ are found to decrease with increasing frequency while the value of ε′ and ε″ increase with increasing temperature, especially, above 160 K. As typical values, the dielectric constant ε′ and dielectric loss ε″ have the values of 7.49, 1.03 at 1 kHz, and only 0.9, 0.02 at 1 MHz, respectively. The ac electrical conductivity (σ_ac) increases with both increasing frequency and temperature. The activation energy of 24 meV was calculated from Arrhenius plot at 1 MHz. The results indicate that the interfacial polarization can be more easily occurred at low frequencies and high temperatures.     

Comparison of radio frequency physical vapor deposition target material used for LaOx cap layer deposition in 32 nm NMOSFETs

The MOSFET gate length reduction down to 32 nm requires the introduction of a metal gate and a high-K dielectric as gate stack, both stable at high temperature. Here we use a nanometric layer of Lanthanum to shift the device threshold voltage from 500 mV. Because this layer plays a key role in the device performance and strongly depends on its deposition process, we have compared two LaO_x deposition methods in terms of physical properties and influence on electrical NMOS device parameters. Chemical characterizations have shown a different oxidization state according to Lanthanum thickness deposited. It has been related to threshold voltage shift and gate leakage current variations on NMOS transistors. Furthermore mobility extractions have shown that Lanthanum is a cause of mobility degradation.     

In situ atomic layer deposition and synchrotron-radiation photoemission study of Al2O3 on pristine n-GaAs(0 0 1)-4 × 6 surface

This work presents the in situ reflection high-energy electron diffraction (RHEED), scanning tunneling microscopy (STM) and synchrotron-radiation photoemission studies for the morphological and interfacial chemical characterization of in situ atomic layer deposited (ALD) Al₂O₃ on pristine molecular beam epitaxy (MBE) grown Ga-rich n-GaAs (1 0 0)-4 × 6 surface. Both the RHEED pattern and STM image demonstrated that the first cycle of ALD-Al₂O₃ process reacted immediately with the GaAs surface. As revealed by in situ synchrotron-radiation photoemission studies, two types of surface As atoms that have excess in charge in the clean surface served as reaction sites with TMA. Two oxidized states were then induced in the As 3d core-level spectra with chemical shifts of +660 meV and +1.03 eV, respectively.     

Preparation and characterization of Fe-doped Ni0.9Co0.8Mn1.3−xFexO4 (0 ≤ x ≤ 0.7) negative temperature coefficient ceramic materials

Based on spinel-type semiconducting electroceramics, negative temperature coefficient (NTC) thermistor materials, Ni_0.9Co_0.8Mn_1.3−xFe_xO₄ (0 ≤ x ≤ 0.7), with different compositions were synthesized by a co-precipitation method. The optimal pH value and the influence of Fe³⁺ doping during the synthesis processing were discussed. As-prepared Ni_0.9Co_0.8Mn_1.3−xFe_xO₄ materials were characterized by DT/TGA, XRD, FTIR, SEM, electrical measurement and impendance analysis. It was found that, as the Fe doping content in the Ni_0.9Co_0.8Mn_1.3−xFe_xO₄ samples increased, both the grain size and the density decreased. The as-sintered Ni_0.9Co_0.8Mn_1.3−xFe_xO₄ samples presented a single-phase cubic spinel structure. The impendance diagram indicated that the grain boundary resistance was dominant in the overall impendance of Ni_0.9Co_0.8Mn_1.3−xFe_xO₄ NTC ceramic materials. The value of ρ₂₅, B_25/50, slope and activation energy for the samples Ni_0.9Co_0.8Mn_1.3−xFe_xO₄ sintered at 1200 °C were in the range of 453.1-2411 Ω cm, 3103-3355 K, 3.27325-3.43149 and 0.28207-0.29325 eV, respectively. This suggests that the electrical properties can be adjusted to desired values by controlling the Fe³⁺ ion doping content.     

Process optimization of polymetal (W/WN/Polysilicon) gate and its impact on dynamic random-access memory chip performance in 0.14-µm technology

This paper summarizes the problems and solutions in the process integration and device and circuit performances of fully working, 256-megabit, dynamic random-access memory (DRAM) chips employing poly-metal gate. In the circuit analysis, an anomalous decay of the electrical signal was observed as the signal proceeds through the delays. A circuit simulation suggested the presence of parasitic components in the gate tungsten/polysilicon interface. The experiments on the tungsten-electrode formation and metal-to-gate contact formation schemes confirmed the effects of the parasitic components when the scheme employing an in-situ formation of diffusion barrier is used. The search for a new cleaning chemical for the postgate etch process was also considered in the integration because it was found to significantly affect the data-retention characteristics. Finally, the temperature dependence of the data retention of the chips employing polymetal- and polycide-gates demonstrated the results to be quite comparable to each other.     

Characterization of CMOS sub-65 nm metallic contact by laser scattering: Thermal stability of Ni(Si1−xGex)

Very efficient in particles detection, light scattering also offers fast non-invasive full-mapping wafer surface state. This sensitivity was used in the case of germano-silicide process development. As a matter of fact, we report on haze measurement performances, compared to the usual methods used to investigate thermal stability of Ni(Si_1−xGe_x), such as sheet resistance (SR), X-ray diffraction (XRD) and scanning electron microscopy (SEM). We observed defectivity related to thermal agglomeration and Ge-segregation of Ni(Si_1−xGe_x) on strain Si_1−xGe_x (x ? 30%) by haze measurement (like SEM observations) earlier than SR measurement. Moreover, we noticed that a high Ge content affects at lower temperature the stability of Ni(Si_1−xGe_x) with a segregation phenomena.     

Epitaxy of BaTiO3 thin film on Si(0 0 1) using a SrTiO3 buffer layer for non-volatile memory application

In this study we report the epitaxial growth of BaTiO₃ films on Si(0 0 1) substrate buffered by 5 nm-thick SrTiO₃ layer using both MBE and PLD techniques. The BaTiO₃ films demonstrate single crystalline, (0 0 1)-oriented texture and atomically flat surface on SrTiO₃/Si template. The electrical characterizations of the BaTiO₃ films using MFIS structures show that samples grown by MBE with limited oxygen pressure during the growth exhibit typical dielectric behavior despite post deposition annealing process employed. A ferroelectric BaTiO₃ layer is obtained using PLD method, which permits much higher oxygen pressure. The C-V curve shows a memory window of 0.75 V which thus enable BaTiO₃ possibly being applied to the non-volatile memory application.     

Characterization of low-k SiOCH dielectric for 45 nm technology and link between the dominant leakage path and the breakdown localization

Electrical characterizations have been performed on porous low-k SiOCH dielectric used in the 45 nm technology. The present paper demonstrates that the conduction follows the Poole-Frenkel (PF) mechanism at medium and high fields. The apparent deviation from the PF mechanism at high field is explained by the trapping phenomenon due to the large amount of defects in the dielectric. This trapping deforms the band diagram and lowers the electron injection within the dielectric. A study of two key process steps is also performed and shows that the dominant conduction mechanism localization (bulk versus interface) is not necessarily at the origin of the breakdown mechanism.     

Relaxation study of AlGaAs cladding layers in InGaAs/GaAs (111)B lasers designed for 1.0-1.1 μm operation

InGaAs/GaAs-based lasers require thick AlGaAs cladding layers to provide optical confinement. Although the lattice mismatch between GaAs and AlGaAs is very low, relaxation may occur due to the thickness requirement for an AlGaAs waveguide of the order of microns. We have studied the relaxation of InGaAs/GaAs lasers with AlGaAs waveguides grown on GaAs (111)B substrates. We have observed by transmission electron microscopy (TEM) that certain AlGaAs layers show a high density of threading dislocations (TDs), whilst other AlGaAs layers remain essentially dislocation free. To explain the experimental results a model based on dislocation multiplication has been developed. TDs in the AlGaAs cladding layers are observed when the critical layer thickness (CLT) for dislocation multiplication has been overcome. Consequently, a design rule based on a modified CLT model for AlGaAs/GaAs (111)B is proposed.