Reliability of SiO2 and high-k gate insulators: A nanoscale study with conductive atomic force microscopy

In this work, a conductive atomic force microscope (C-AFM) is used to study the reliability (degradation and breakdown, BD) of SiO₂ and high-k dielectrics. The effect of a current limit on the post-BD SiO₂ electrical properties at the nanoscale is discussed. In particular, the impact of a current limit imposed during the stress on the post-BD oxide conductivity at the position where BD has been triggered, the area affected by the BD event and the structural damage induced in the broken down region will be investigated. A purposely developed C-AFM with enhanced electrical performance (ECAFM) is also presented, which has been used for the electrical characterization of HfO₂/SiO₂ gate stacks. The conduction of the fresh (without stress), electrically stressed and broken down stacks have been analyzed.     

Al-oxynitrides as a buffer layer for Pr2O3/SiC interfaces

We elaborate the possibility of combining high-k dielectrics with wide band gap semiconductors, i.e. Pr₂O₃ on SiC. The thermal stability of interfacial aluminum oxynitride (AlON) layers between Pr-oxide and SiC has been investigated by synchrotron radiation photoemission spectroscopy (SRPES). The interface of Pr₂O₃ with SiC is reactive. Such reaction is successfully prevented by utilizing a stable interlayer derived from AlON. No elemental carbon is observed in detectable amount after Pr-Oxide deposition on AlON covered 3C-SiC and subsequent vacuum annealing. After vacuum annealing at 500 °C AlON transformed to AlN and Pr-aluminate with a small amount of CN close to the SiC surface which were thermally stable even at 900 °C. AlON hence provides a good diffusion barrier between Pr-oxide dielectric and 3C-SiC.     

Improved performance by using TaON/SiO2 as dual tunnel layer in Charge-Trapping nonvolatile memory

Tunneling–barrier engineered stacks with different high-κ dielectrics are investigated by fabricating the stacked structures of Al/Al₂O₃/HfLaON/ (TaON/SiO₂)/Si and Al/Al₂O₃/HfLaON/ (HfON/SiO₂)/Si. As compared to the device with HfON/SiO₂ dual tunnel layer (DTL), the one with TaON/SiO₂ DTL shows larger memory window (3.85 V at ± 13 V/1 s), higher program/erase speeds (1.85 V/−2.00 V at ± 12 V/100 μs), better endurance (window narrowing rate of 5.7% after 10⁵ cycles). The main mechanisms involved lie in (1) the higher dielectric constant of TaON which induces high electric field in the SiO₂ layer, (2) the smaller conduction/valence-band offsets between TaON and the Si substrate, and (3) better interface quality with SiO₂. Furthermore, compared with SiO₂ single tunnel layer, better retention characteristics can be achieved for the TaON/SiO₂ DTL due to its larger thickness.     

Effect of plasma treatments on interface chemistry and adhesion strength between porous SiO2 low-k film and SiC/SiN layers

In this study, the interface chemistry and adhesion strengths between porous SiO₂ low-dielectric-constant film and SiN capping layer as well as SiC etch stop layer have been investigated under different plasma treatments. Elements of Si, O, and N constructed an interlayer region with mixing Si-N and Si-O bonds at the interface between the porous SiO₂ film and SiN capping layer. After plasma treatments especially O₂ plasma, the oxygen content at the interface increased, and the binding energy obviously shifted to a higher level. Under nanoindentation and nanoscratch tests, interface delamination occurred, and the interface adhesion strength was accordingly measured. After plasma treatments especially the O₂ plasma, more Si-O bonds of high binding energy existed at the interface, and thus the interface adhesion strength was effectively improved. The adhesion energy of SiO₂/SiN and SiC/SiO₂ interfaces was enhanced to 4.7 and 10.5 J/m² measured by nanoindentation test, and to 1.3 and 2.0 J/m² by nanoscratch test, respectively.     

Initial leakage current related to extrinsic breakdown in HfO2/Al2O3 nanolaminate ALD dielectrics

Multiple successive breakdown events are reported for HfO₂/Al₂O₃ nanolaminate dielectrics grown by atomic-layer deposition. The first breakdown distribution is not a Weibull distribution and shows a long TBD tail at high failure percentiles. Analysis of the correlation between time-to-breakdown and initial current leakage allows identifying this tail with extrinsic breakdown. Screening of the data to eliminate the extrinsic tail demonstrates that the successive breakdown events are completely uncorrelated and perfectly match the successive breakdown theory. The statistical correlation between initial current and extrinsic breakdown distribution is explained in terms of variations of the unintentional interfacial SiO_x layer at the silicon substrate/dielectric interface.     

Analyses of interface adhesion between porous SiO2 low-k film and SiC/SiN layers by nanoindentation and nanoscratch tests

In this study, the interface adhesion between porous SiO₂ low-dielectric-constant film and SiN capping layer as well as SiC etch stop layer has been investigated. The SiN capping layer was found mostly composed of Si to N bonds, and the porous SiO₂ film composed of Si to O bonds. Elements of Si, O, and N constructed an interlayer mixing region of about 20 nm at the interface between the porous SiO₂ film and SiN capping layer. Under nanoindentation and nanoscratch tests, interface delamination between the porous SiO₂ film and both SiN capping layer and SiC etch stop layer occurred around the indented regions, and the interface adhesion strengths were accordingly obtained. The interface adhesion energy between the porous SiO₂ film and SiN capping layer was measured as about 3.7 and 0.9 J/m² by nanoindentation and nanoscratch tests, respectively, and that between the porous SiO₂ film and SiC etch stop layer was about 8.3 and 1.2 J/m².     

Local current fluctuations before and after breakdown of thin SiO2 films observed with conductive atomic force microscope

Very thin SiO₂ films (3–6 nm) have been characterized with a conductive atomic force microscope (C-AFM). The set-up allows the electrical characterization of 30–50 nm² areas, which are of the order of single breakdown spots. Voltage ramps have been repeatedly applied to induce the degradation. On these spots, the phenomenology observed is quite similar to that during conventional electrical tests. In particular, on–off fluctuations before and after breakdown are reported on single breakdown spots. The results confirm the C-AFM as a suitable tool for the analysis of the gate oxide electrical properties and degradation dynamics at a nanometer scale.     

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 gate stack nMOSFETs

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO₂ thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < T_IL and the traps of HfO₂ in T_IL < z < T_HK. The traps near the Si/SiO₂ interface dominated the 1/f noise at higher frequencies, which is common in SiO₂ dielectrics. For the HfO₂/SiO₂ gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO₂ film than at the bottom of the interface.     

XPS studies of the ALD-growth of TaN diffusion barriers: Impact of the dielectric surface chemistry on the growth mechanism

The introduction of SiOCH low-k dielectrics in the copper interconnections of sub-45 nm node technologies is a challenge in terms of both material and process criteria. For instance, the deposition of a diffusion barrier between copper and dielectric is strongly dependent on the nature of the dielectric surface. In this study, we investigate the first steps of ALD TaN growth with respect to dielectric surface chemistry, using XPS measurements. Three different dielectrics have been tested: SiOCH, SiO₂ or SiOCH capped by a thin SiO₂ layer. We show that TaN can only grow over a monolayer-thick Ta₂O₅ formed at the early stages of deposition. A mechanism for the growth first steps is described, explaining the incubation delays observed for the appearing of Ta-O and Ta-N bonds. In addition, we show that a 3 nm-thick SiO₂ layer is able to hide the effect of SiOCH chemistry and obtain similar growth rates on SiOCH and SiO₂.     

Process integration and nanometer-scale electrical characterization of crystalline high-k gate dielectrics

Crystalline praseodymium oxide (Pr₂O₃) high-k gate dielectric has been successfully integrated into a polysilicon gate CMOS technology. Fully functional MOSFETs with an equivalent oxide thickness (EOT) of 1.8 nm and gate leakages below 10⁻⁶ A/cm² have been fabricated. However, at this early stage of development the transistors show Vt-instabilities and unusual high gate leakage for L > 10 μm. As a first attempt to explain the observed macroscopic device characteristics, topographical and electrical measurements at the nanometer scale have been performed directly on the Pr₂O₃ surface by Conductive Atomic Force Microscopy (C-AFM). This technique allows to discriminate between structural defect sites and charge trapping centers.     

Interfacial properties and reliability of SiO2 grown on 6H-SiC in dry O2 plus trichloroethylene

A new process of growing SiO₂ on n- and p-type 6H-SiC wafers in dry O₂ + trichloroethylene (TCE) was investigated. The interface quality and reliability of 6H-SiC metal-oxide-semiconductor (MOS) capacitors with gate dielectrics prepared by the process were examined. As compared to conventional dry O₂ oxidation, the O₂ + TCE oxidation resulted in lower interface-state, border-trap and oxide-charge densities, and enhanced reliability. This could be attributed to the passivation effect of Cl₂ or HCl on structural defects at/near the SiC/SiO₂ interface, and the gettering effect of Cl₂ or HCl on ion contamination. In addition, increased oxidation rate was observed in the O₂ + TCE ambient, and can be used to reduce the normally-high thermal budget for oxide growth. All these are very attractive for fabricating SiC MOS field-effect transistors (MOSFETs) with high inversion-channel mobility and high hot-carrier reliability.     

Sol–gel MgO thin films for insulation on SiC

Silicon carbide (SiC) is a wide bandgap semiconductor suitable for high-voltage, high-power, and high-temperature devices from DC to microwave frequencies. However, the marketing of advanced SiC power devices remains limited due to performance limitation of the SiO₂ dielectric among other issues. Indeed, SiO₂ has a dielectric constant 2.5 times lower than SiC, which means that at critical field for breakdown in SiC, the electric field in the adjoining SiO₂ becomes too high for reliable operation. This suppresses the main advantage of using SiC power devices if the ten times higher breakdown field for SiC in comparison to Si cannot be exploited. Therefore, alternative dielectrics having a dielectric constant higher or in the same order as SiC (ε_r≈10) should be used to reduce the electrical field in the insulator. Among alternative dielectrics to silicon dioxide (SiO₂), magnesium oxide (MgO) seems to be a good candidate regarding its bulk properties: large bandgap, high thermal conductivity and stability, and a suitable dielectric constant (ε_r≈10). In order to evaluate such a promising candidate, the sol–gel process appears to be a convenient route to elaborate this kind of coatings. By selecting an appropriate precursor solution and optimizing the curing conditions of the films, MgO films could be obtained under various crystallization states: non-oriented or preferred [1 1 1] orientation. MIM structures have been used to investigate the insulating properties of the sol–gel MgO films. The dielectric strength of the films was found to be microstructure–dependent, and reached 3 to 8 MV/cm at room temperature. Leakage currents were measured from 150 up to 250 °C, with values less than 10⁻⁵ A/cm² at 1 MV/cm.     

Selection of rare earth silicates for highly scaled gate dielectrics

An aggressive equivalent oxide thickness (EOT) scaling with high-k gate dielectrics has been demonstrated by ultra-thin La₂O₃ gate dielectric with a proper selection of rare earth (La-, Ce- and Pr-) silicates as an interfacial layer. Among silicates, Ce-silicate has shown the lowest interface-state density as low as 10¹¹ cmv⁻²/eV with a high dielectric constant over 20. n-Type field-effect transistor (FET) with a small EOT of 0.51 nm has been successfully fabricated with a La₂O₃ gate dielectric on a Ce-silicate interfacial layer after annealing at 500 °C. Negative shift in threshold voltage and reduced effective electron mobility has indicated the presence of fixed charges in the dielectric. Nonetheless, the high dielectric constant and nice interfacial property of Ce-silicate can be advantageous for the interfacial layer in highly scaled gate dielectrics.     

High resolution electrical characterisation of organic photovoltaic blends

In this work, electrostatic force microscopy (EFM) and conductive atomic force microscopy (C-AFM) are applied to perform high-resolution electrical characterisation of organic photovoltaic films. These films are composed of the C₆₀-derivative PCBM blended with hole conductive conjugated polymers PPV derivatives or P3HT. It is demonstrated that both EFM and C-AFM are able to electrically evidence phase separation in the blends, suggesting in addition higher density of carriers along interfaces. Correlation between the EFM contrast and the photovoltaic properties of the blends was observed. Local spectroscopy (I-V curves) completes the C-AFM investigations, analysing charge transport mechanisms in the P3HT:PCBM blend. Significant modifications of the local electrical properties of P3HT are shown to occur upon blending. Space charge limited current is evidenced in the blend and a hole mobility of 1.7 × 10⁻² cm² V⁻¹ s⁻¹ is determined for P3HT.     

Anomalous drain voltage dependence in bias temperature instability measurements on high-κ field effect transistors

We find that changes in threshold voltage induced by negative bias temperature stressing of p-channel field effect transistors with HfSiON gate dielectrics are modulated by the drain voltage, in measurements wherein the drain current is measured during stressing. This effect is not observed in SiO₂ gate devices. Short channel effects are excluded as explanations, leading us to conclude that positive charge in the dielectric stack is laterally mobile and is conducted out of the insulator via the drain. Further, a simple qualitative model of charging kinetics allows us to extract the density of interface states as a function of time, and shows that these defects build in time, reaching numbers on the order of 10¹¹ cm⁻² after hundreds of seconds.     

Systematic characterization of soft- and hard-breakdown spots using techniques with nanometer resolution

In this work, different Atomic Force Microscopy (AFM) related techniques have been used to completely characterize soft- and hard-breakdown spots of SiO₂ gate oxides. In particular, C-AFM (Conductive AFM), SCM (Scanning Capacitance Microscopy) and KPFM (Kelvin Probe Force Microscopy) were used to study the propagation, conduction and the electrical damage of previously broken down gate oxide areas. The results show that the combination of these techniques allows a complete and systematic study of the BD phenomenology at the nanoscale.     

OLED compatible water-based nanolaminate encapsulation systems using ozone based starting layer

Highly efficient nanolaminate diffusion barriers made of TiO₂/Al₂O₃ multilayers using low temperature atomic layer deposition optimized for organic light emitting diodes are presented. Water vapour transmission rates (WVTR) show values of the order of 10⁻³ g/m²/d at 38 °C, 90% RH on planarized PEN webs (pPEN) when ozone is used as the oxidizing precursor for Al₂O₃ deposition. OLED encapsulated with such diffusion barriers display few dark spots observed over 2000 h after deposition and for aging under ambient conditions. Diffusion barriers deposited using water as the oxidizing precursor for Al₂O₃ result in at least 10 times lower WVTR on pPEN webs (10⁻⁴ g/m²/d). However, these water based diffusion barriers are incompatible with OLEDs such that the latter show extensive black spot formation (areas of no visible luminescence) immediately after deposition. Finally through the growth of these initial black spots, more than 40% loss in initial luminescence occurs after merely 900 h of operation. In this report, we introduce a new methodology for OLED encapsulation using a two step process where 10 nm thick ozone Al₂O₃ based nanolaminate diffusion barrier is followed by a 90 nm thick water Al₂O₃ based diffusion barrier (keeping TiO₂ precursors always the same). With this novel diffusion barrier stack, no visible black spot growth is observed over 2000 continuous operation hours under ambient conditions. Simultaneously, high OLED luminescence representing 90% of the initial luminescence value, which is measured at t = 0 is maintained after 2000 h of operation. Low WVTR values in the 10⁻⁴ g/m²/d range on pPEN webs are consistently measured in these essentially water based barrier layers with only 10 nm thick starting ozone Al₂O₃ based nanolaminate diffusion barriers. The results reported here have implications on developing methodologies for ultra high performance, OLED compatible diffusion barriers by ALD.     

Atomic-layer-deposited silicon-nitride/SiO2 stack––a highly potential gate dielectrics for advanced CMOS technology

An extremely thin (2 monolayers) silicon nitride layer has been deposited on thermally grown SiO₂ by an atomic-layer-deposition (ALD) technique and used as gate dielectrics in metal–oxide–semiconductor (MOS) devices. The stack dielectrics having equivalent oxide thickness (T_eq=2.2 nm) efficiently reduce the boron diffusion from p⁺ poly-Si gate without the pile up of nitrogen atoms at the SiO₂/Si interface. The ALD silicon nitride is thermally stable and has very flat surface on SiO₂ especially in the thin (<0.5 nm) thickness region.An improvement has been obtained in the reliability of the ALD silicon-nitride/SiO₂ stack gate dielectrics compared with those of conventional SiO₂ dielectrics of identical thickness. An interesting feature of soft breakdown free phenomena has been observed only in the proposed stack gate dielectrics. Possible breakdown mechanisms are discussed and a model has been proposed based on the concept of localized physical damages which induce the formation of conductive filaments near both the poly-Si/SiO₂ and SiO₂/Si-substrate interfaces for the SiO₂ gate dielectrics and only near the SiO₂/Si-substrate interface for the stack gate dielectrics.Employing annealing in NH₃ at a moderate temperature of 550 °C after the ALD of silicon nitride on SiO₂, further reliability improvement has been achieved, which exhibits low bulk trap density and low trap generation rate in comparison with the stack dielectrics without NH₃ annealing.Because of the excellent thickness controllability and good electronic properties, the ALD silicon nitride on a thin gate oxide will fulfill the severe requirements for the ultrathin stack gate dielectrics for sub-0.1 μm complementary MOS (CMOS) transistors.     

Nanometer-scale leakage measurements in high vacuum on de-processed high-k capacitors

Conductive atomic force microscopy (C-AFM) allows probing local phenomena such as trap assisted tunneling and oxide breakdown, which hamper meeting the high-k device requirements. In this work we present the improvement of Conductive AFM measurements in high vacuum (1e^?5 torr) due to improved preservation of tip conductivity. Furthermore, we describe the gate removal process of real MOS devices, enabling standard macroscopic and microscopic measurements on the same gate dielectric. Using this procedure, we are able with C-AFM to locate the BD spots induced by standard macroscopic constant voltage stress. The C-AFM measured local current–voltage (I–V) characteristic of a single BD spot aligns well with the macroscopic post breakdown I–V trace.     

Electrical and physical characteristics of HfLaON-gated metal-oxide-semiconductor capacitors with various nitrogen concentration profiles

The comparative studies of electrical and physical characteristics of HfLaON-gated metal-oxide-semiconductor (MOS) capacitors with various nitrogen concentration profiles (NCPs) were investigated. Various NCPs in HfLaON gate dielectrics were adjusted by Hf₂La₂O₇ target sputtered in an ambient of modulated nitrogen flow. The related degradation mechanisms of various NCPs in HfLaON dielectrics have been investigated under various post-deposition annealing (PDA). The results indicate that by developing full nitrogen profile (FNP) incorporated into HfLaON dielectric enhances electrical characteristics, including oxide trap charge, interface trap density, and trap energy level. Detailed understand of current mechanisms of various NCPs incorporated into HfLaON dielectrics using current-voltage characteristics under various temperature measurements were investigated. Energy band diagram of MOS capacitor with Ta/HfLaON/SiO₂/P-Si(1 0 0) structure was demonstrated by the measurement of Schottky barrier height and the optical band gaps.