共查询到20条相似文献,搜索用时 15 毫秒
1.
Youhei Sugimoto Hideto Adachi Keisuke Yamamoto Dong Wang Hideharu Nakashima Hiroshi Nakashima 《Materials Science in Semiconductor Processing》2006,9(6):1031
High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO2/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfOx and SiO2. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfOx/SiO2/Si to HfSixOy/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO2. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO2. 相似文献
2.
In this paper, we report our recent study of the effect of RuO2 as an alternative top electrode for pMOS devices to overcome the serious problems of polysilicon (poly-Si) gate depletion, high gate resistance and dopant penetration in the trend of down to 50 nm devices and beyond. The conductive oxide RuO2, prepared by RF sputtering, was investigated as the gate electrode on the Laser MBE (LMBE) fabricated HfO2 for pMOS devices. Structural, dielectric and electric properties were investigated. RuO2/HfO2/n-Si capacitors showed negligible flatband voltage shift (<10 mV), very strong breakdown strength (>10 MV cm−1). Compared to the SiO2 dielectric with the same EOT value, RuO2/HfO2/n-Si capacitors exhibited at least 4 orders of leakage current density reduction. The work function value of the RuO2 top electrode was calculated to be about 5.0 eV by two methods, and the effective fixed oxide charge density was determined to be 3.3 × 1012 cm−2. All the results above indicate that RuO2 is a promising alternative gate electrode for LMBE grown HfO2 gate dielectrics. 相似文献
3.
T. Nabatame Y. Nunoshige H. Takaba S. Kimura H. Ota A. Toriumi 《Microelectronic Engineering》2008,85(7):1524-1528
Effective work function (?m,eff) values of Hfx Ru1−x alloy gate electrodes on SiO2 metal-oxide-semiconductor (MOS) capacitors were carefully examined to assess whether the ?m,eff was determined by the crystalline structure or the composition of the HfxRu1−x alloy. X-ray diffraction results indicated that the crystalline structures of HfxRu1−x alloy were divided into hexagonal-Ru, cubic-HfRu or hexagonal-Hf with the increase of Hf content. The ?m,eff values could be controlled continuously from 4.6 to 4.0 eV by changing the Hf content. The experimental ?m,eff value showed a good agreement with theoretical results considering the compositional ratio of pure Hf and Ru. These results suggest that the ?m,eff of HfxRu1−x alloy gates on SiO2 MOS capacitors is dominantly determined by the HfxRu1−x composition rather than the crystalline structure. 相似文献
4.
D. Kitayama T. KoyanagiK. Kakushima P. AhmetK. Tsutsui A. NishiyamaN. Sugii K. NatoriT. Hattori H. Iwai 《Microelectronic Engineering》2011,88(7):1330-1333
The effect of a thin Si layer insertion at W/La2O3 interface on the electrical characteristics of MOS capacitors and transistors is investigated. A suppression in the EOT increase can be obtained with Si insertion, indicating the inhibition of diffusion of oxygen atoms into La2O3 layer by forming an amorphous La-silicate layer at the W/La2O3 interface. In addition, positive shifts in Vfb and Vth caused by Si insertion implies the formation of amorphous La-silicate layer at the top of La2O3 dielectrics reduces the positive fixed charges induced by the metal electrode. Consequently, a large improvement in mobility has been confirmed for both at peak value and at high Eeff of 1 MV/cm with Si inserted nFETs. Although a degradation trend on EOT scaling has been observed, the insertion of thin Si layer is effective in pushing the scaling limit. 相似文献
5.
The characteristics of TDDB (time-dependent dielectric breakdown) and SILC (stress-induced leakage current) for an ultra-thin SiO2/HfO2 gate dielectric stack are studied. The EOT (equivalent-oxide-thickness) of the gate stack (Si/SiO2/HfOz/TiN/TiA1/TiN/W) is 0.91 am. The field acceleration factor extracted in TDDB experi- ments is 1.59 s.cm/MV, and the maximum voltage is 1.06 V when the devices operate at 125 ℃ for ten years. A detailed study on the defect generation mechanism induced by SILC is presented to deeply understand the break- down behavior. The trap energy levels can be calculated by the SILC peaks: one S1LC peak is most likely to be caused by the neutral oxygen vacancy in the HfO2 bulk layer at 0.51 eV below the Si conduction band minimum; another SILC peak is induced by the interface traps, which are aligned with the silicon conduction band edge. Fur- thermore, the great difference between the two SILC peaks demonstrates that the degeneration of the high-k layer dominates the breakdown behavior of the extremely thin gate dielectric. 相似文献
6.
Isodiana Crupi 《Microelectronic Engineering》2009,86(1):1-3
Charge trapping and trap generation in field-effect transistors with SiO2/HfO2/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case. 相似文献
7.
The effect of various electrodes (Al, W, TiN) deposited by evaporation (Al) and sputtering (W, TiN) on the electrical characteristics of thermal thin film (15-35 nm) Ta2O5 capacitors has been investigated. The absolute level of leakage currents, breakdown fields, mechanism of conductivity, dielectric constant values are discussed in the terms of possible reactions between Ta2O5 and electrode material as well as electrode deposition process-induced defects acting as electrically active centers. The dielectric constant values are in the range 12-26 in dependence on both Ta2O5 thickness and gate material. The results show that during deposition of TiN and Al a reaction that worsens the properties of Ta2O5 occurs while there is not an indication for detectable reduction of Ta2O5 when top electrode is W, and the leakage current is 5-7 orders of magnitude lower as compared to Al and TiN-electroded capacitors. The high level of leakage current for TiN and Al gate capacitors are related to the radiation defects generated in Ta2O5 during sputtering of TiN, and damaged interface at the electrode due to a reaction between Al and Ta2O5, respectively. It is demonstrated that the quality of the top electrode affects the electrical characteristics of the capacitors and the sputtered W is found to be the best. The sputtered W gate provides Ta2O5 capacitors with a good quality: the current density <7 × 10−10 A/cm2 at 1 V (0.7 MV/cm, 15 nm thick Ta2O5). W deposition is not accompanied by an introduction of a detectable damage leading to a change of the properties of the initial as-grown Ta2O5 as in the case of TiN electrode. Damage introduced during TiN sputtering is responsible for current deterioration (high leakage current) and poor breakdown characteristics. It is concluded that the sputtered W top electrode is a good candidate as a top electrode of storage capacitors in dynamic random access memories giving a stable contact with Ta2O5, but sputtering technique is less suitable (favorable) for deposition of TiN as a metal electrode due to the introduction of radiation defects causing both deterioration of leakage current and poor breakdown characteristics. 相似文献
8.
A. Bayerl M. LanzaM. Porti F. CampabadalM. Nafría X. AymerichG. Benstetter 《Microelectronic Engineering》2011,88(7):1334-1337
The electrical properties and reliability of MOS devices based on high-k dielectrics can be affected when the gate stack is subjected to an annealing process, which can lead to the polycrystallization of the high-k layer. In this work, a Conductive Atomic Force Microscope (C-AFM) has been used to study the nanoscale electrical conduction and reliability of amorphous and polycrystalline HfO2 based gate stacks. The link between the nanoscale properties and the reliability and gate conduction variability of fully processed MOS devices has also been investigated. 相似文献
9.
C.H. FuK.S. Chang-Liao Y.A. ChangY.Y. Hsu T.H. TzengT.K. Wang D.W. HehP.Y. Gu M.J. Tsai 《Microelectronic Engineering》2011,88(7):1309-1311
Annealing effects on electrical characteristics and reliability of MOS device with HfO2 or Ti/HfO2 high-k dielectric are studied in this work. For the sample with Ti/HfO2 higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10−2 A/cm2. As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded. 相似文献
10.
Yung-Hsien Wu Lun-Lun ChenWei-Chia Chen Chia-Chun LinMin-Lin Wu Jia-Rong Wu 《Microelectronic Engineering》2011,88(7):1361-1364
A Ge-stabilized tetragonal ZrO2 (t-ZrO2) film with permittivity (κ) of 36.2 was formed by depositing a ZrO2/Ge/ZrO2 laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO2. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO2 gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH3 plasma, good leakage current of 4.8 × 10−8 A/cm2 at Vg = Vfb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained. 相似文献
11.
Hafnium-based dielectrics are the most promising material for SiO2 replacement in future nodes of CMOS technology. While devices that utilize HfO2 gate dielectrics suffer from lower carrier mobility and degraded reliability, our group has recently reported improved device characteristics with a modified HfxZr1−xO2 [R.I. Hegde, D.H. Triyoso, P.J. Tobin, S. Kalpat, M.E. Ramon, H.-H. Tseng, J.K. Schaeffer, E. Luckowski, W.J. Taylor, C.C. Capasso, D.C. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L.B. La, E. Hebert, R. Cotton, X.-D. Wang, S. Zollner, R. Gregory, D. Werho, R.S. Rai, L. Fonseca, M. Stoker, C. Tracy, B.W. Chan, Y.H. Chiu, B.E. White, Jr., in: Technical Digest - International Electron Devices Meet, vol. 39, 2005, D.H. Triyoso, R.I. Hegde, J.K. Schaeffer, D. Roan, P.J. Tobin, S.B. Samavedam, B.E. White, Jr., R. Gregory, X.-D. Wang, Appl. Phys. Lett. 88 (2006) 222901]. These results have lead to evaluation of X-ray reflectivity (XRR) for monitoring high-k film thickness and control of Zr addition to HfO2 using measured film density. In addition, a combination of XRR and spectroscopic ellipsometry (SE) is shown to be a fast and non-intrusive method to monitor thickness of interfacial layer between high-k and the Si substrate. 相似文献
12.
Electrical properties of hafnium oxide (HfO2) gate dielectric with various metal nitride gate electrodes, i.e., tantalum nitride (TaN), molybdenum nitride (MoN), and tungsten nitride (WN), were studied over a range of HfO2 thicknesses, e.g., 2.5-10 nm, and post-metal annealing (PMA) temperatures, e.g., 600 °C to 800 °C. The work function of the nitride gate electrode was dependent on the material and the post-metal annealing (PMA) temperature. The scanning transmission electron microscopy technique is used to observe the effect of PMA on the interfacial gate dielectric thickness. After high-temperature annealing, the metal nitride gates were suitable for NMOS. At the same PMA temperature, the oxide-trapped charges increased and the interface state densities decreased with the increase of the HfO2 thickness for TaN and WN gate electrodes. However, for MoN gate electrode the interface state density is almost independent of film thickness. Therefore, dielectric properties of the HfO2 high-k film depend not only on the metal nitride gate electrode material but also the post-metal annealing condition as well as the film thickness. During constant voltage stress of the MOS capacitors, an increase in the time-dependent gate leakage current is also observed. 相似文献
13.
Ch. Wenger M. Lukosius R. Sorge H.-J. Müssig Ch. Lohe 《Microelectronic Engineering》2008,85(8):1762-1765
HfO2 films were grown by atomic vapour deposition (AVD) on SiO2/Si (1 0 0) substrates. The positive shift of the flat band voltage of the HfO2 based metal-oxide-silicon (MOS) devices indicates the presence of negative fixed charges with a density of 5 × 1012 cm−2. The interface trap charge density of HfO2/SiO2 stacks can be reduced to 3 × 1011 eV−1 cm−2 near mid gap, by forming gas annealing. The extracted work function of 4.7 eV preferred the use of TiN as metal gate for PMOS transistors. TiN/HfO2/SiO2 gate stacks were integrated into gate-last-formed MOSFET structures. The extracted maximum effective mobility of HfO2 based PMOS transistors is 56 cm2/Vs. 相似文献
14.
According to the recent prediction made by the Semiconductor Industry Association (SIA) in International Technology Roadmap for Semiconductors (ITRS), the silicon technology will continue its historical rate of advancement with the Moore’s law for at least a couple of decades. With this trend, the silicon gate oxide will be scaled down to its physical limit in order to maintain proper control of the nanosize MOS transistors. This work reviews several critical issues of MOS gate dielectrics in the nanometer range.Although it was suggested that the conventional oxide can be scaled down, in principle, to two atomic layers of about 7 Å, this is not practically feasible because of the non-scalabilities of interface, trap capture cross-section, leakage current, and the statistical parameters of fabrication processes. Introducing a high-κ material can help solving most of the problems by using physically thicker high-κ gate dielectric films but several other reliability problems of the MOS devices rises. Being used in the extreme fine structure, the requirements for the material properties of the new high-κ are very stringent. Unfortunately, most of the high-κ materials are ionic metal oxides. This fundamental physics results in several undesirable instability issues when interfacing with silicon and with the CMOS processes. Bulk type thin oxynitride/high-κ stack could be a good solution for the coming technology nodes. 相似文献
15.
H. Volders Z. Tökei B. Brijs L. Carbonell C. Drijbooms S. Garaud A. Moussa Y. Travaly G. Vereecke W.-M. Li A.M. Jonas 《Microelectronic Engineering》2007,84(11):2460-2465
A ternary WNxCy system was deposited in a thermal ALD (atomic layer deposition) reactor from ASM at 300 °C in a process sequence using tungsten hexafluoride (WF6), triethyl borane (TEB) and ammonia (NH3) as precursors. The WCx layers were deposited by a novel ALD process at a process temperature of 250 °C. The WNx layers were deposited at 375 °C using bis(tert-butylimido)-bis-(dimethylamido)tungsten (tBuN)2(Me2N)2W (imido-amido) and NH3 as precursors. WNx grows faster on plasma enhanced chemical vapor deposition (PECVD) oxide than WCx does on chemical oxide. WNxCy grows better on PECVD oxide than on thermal oxide, which is opposite of what is seen for WNx. In the case of the ternary WNxCy system, the scalability towards thinner layers and galvanic corrosion behavior are disadvantages for the incorporation of the layer into Cu interconnects. ALD WCx based barriers have a low resistivity, but galvanic corrosion in a model slurry solution of 15% peroxide (H2O2) is a potential problem. Higher resistivity values are determined for the binary WNx layers. WNx shows a constant composition and density throughout the layer. 相似文献
16.
Hafnium oxide (HfO2) films were deposited on Si substrates with a pre-grown oxide layer using hafnium chloride (HfCl4) source by surface sol-gel process, then ultrathin (HfO2)x(SiO2)1−x films were fabricated due to the reaction of SiO2 layer with HfO2 under the appropriate reaction-anneal treatment. The observation of high-resolution transmission electron microscopy indicates that the ultrathin films show amorphous nature. X-ray photoelectron spectroscopy analyses reveal that surface sol-gel derived ultrathin films are Hf-Si-O alloy instead of HfO2 and pre-grown SiO2 layer, and the composition was Hf0.52Si0.48O2 under 500 °C reaction-anneal. The lowest equivalent oxide thickness (EOT) value of 0.9 nm of film annealed at 500 °C has been obtained with small flatband voltage of −0.31 V. The experimental results indicate that a simple and feasible solution route to fabricate (HfO2)x(SiO2)1−x composite films has been developed by means of combination of surface sol-gel and reaction-anneal treatment. 相似文献
17.
H.D.B. Gottlob T. Echtermeyer T. Mollenhauer J.K. Efavi M. Schmidt T. Wahlbrink M.C. Lemme H. Kurz 《Materials Science in Semiconductor Processing》2006,9(6):904
Novel gate stacks with epitaxial gadolinium oxide (Gd2O3) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10–7 A cm–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd2O3 thickness of 3.1 nm yield current densities down to 0.5 A cm−2 at Vg=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd2O3 gate stacks for future material-based scaling of CMOS technology. 相似文献
18.
I. Mani?E. Atanassova N. Stojadinovi?D. Spassov A. Paskaleva 《Microelectronic Engineering》2011,88(3):305-313
The stress-induced leakage current in Hf-doped Ta2O5 layers (7; 10 nm) under constant voltage stress at gate injection was investigated in order to assess the mechanisms of conduction, the traps involved and the effect of Hf doping. The amount of Hf is found to affect the conduction mechanisms, the temperature dependence of the leakage current and the current response to the stress. A significant leakage current increase is observed only when the stress voltage and/or stress time exceed the corresponding threshold values, where the charge trapping at the pre-existing traps dominates below and defect generation above these threshold values. The energy levels of the traps responsible for the current transport are estimated. The stress effect on dominant conduction mechanisms appears quite weak, and the nature of the traps controlling the current transport before and after the stress seems to be nearly identical. The results indicate that the constant voltage stress affects the pre-existing traps in Hf-doped Ta2O5 and modifies their parameters, but there is no evidence for stress-induced generation of traps with completely new nature different from oxygen-vacancy related defects. 相似文献
19.
W. Yu B. Zhang Q.T. Zhao J.-M. HartmannD. Buca A. NichauR. Lupták J.M. LopesS. Lenk M. LuysbergK.K. Bourdelle X. WangS. Mantl 《Solid-state electronics》2011,62(1):185-188
Strained SiGe quantum well p-MOSFETs with LaLuO3 higher-k dielectric were fabricated and characterized. The strained Si/strained Si0.5Ge0.5/strained SOI heterostructure transistors showed good output and transfer characteristics with an Ion/Ioff ratio of 105. The extracted hole mobility shows an enhancement of about 2.5 times over Si universal hole mobility and no degradation compared to HfO2 or even SiO2 gate dielectric devices. 相似文献
20.
Electrical properties of mixed HfO2-Ta2O5 films (10;15 nm) deposited by rf sputtering on Si have been studied from the view point of their applications as high-k layers, by standard capacitance-voltage and temperature dependent current-voltage characteristics. The effect of HfO2 addition to the Ta2O5 is thickness dependent and the thicker layers exhibit advantages over the pure Ta2O5 (higher dielectric constant, enhanced charge storage density and improved interface quality). The process of HfO2 and Ta2O5 mixing introduces negative oxide charge, tends to creates shallow bulk traps and modifies the dominant conduction mechanisms in the stack capacitors as compared to the Ta2O5-based one (a contribution of tunneling processes through traps located below the conduction band of mixed layers to the leakage current in the HfO2-Ta2O5 stacks is observed). The traps involved in both Poole-Frenkel and tunneling processes are identified. 相似文献