X-ray metrology for high-k atomic layer deposited HfxZr1−xO2 films

Hafnium-based dielectrics are the most promising material for SiO₂ replacement in future nodes of CMOS technology. While devices that utilize HfO₂ gate dielectrics suffer from lower carrier mobility and degraded reliability, our group has recently reported improved device characteristics with a modified Hf_xZr_1−xO₂ [R.I. Hegde, D.H. Triyoso, P.J. Tobin, S. Kalpat, M.E. Ramon, H.-H. Tseng, J.K. Schaeffer, E. Luckowski, W.J. Taylor, C.C. Capasso, D.C. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L.B. La, E. Hebert, R. Cotton, X.-D. Wang, S. Zollner, R. Gregory, D. Werho, R.S. Rai, L. Fonseca, M. Stoker, C. Tracy, B.W. Chan, Y.H. Chiu, B.E. White, Jr., in: Technical Digest - International Electron Devices Meet, vol. 39, 2005, D.H. Triyoso, R.I. Hegde, J.K. Schaeffer, D. Roan, P.J. Tobin, S.B. Samavedam, B.E. White, Jr., R. Gregory, X.-D. Wang, Appl. Phys. Lett. 88 (2006) 222901]. These results have lead to evaluation of X-ray reflectivity (XRR) for monitoring high-k film thickness and control of Zr addition to HfO₂ using measured film density. In addition, a combination of XRR and spectroscopic ellipsometry (SE) is shown to be a fast and non-intrusive method to monitor thickness of interfacial layer between high-k and the Si substrate.     

Resistive switching effects of HfO2 high-k dielectric

Resistive switching behavior of HfO₂ high-k dielectric has been studied as a promising candidate for emerging non-volatile memory technology. The low resistance ON state and high resistance OFF state can be reversibly altered under a low SET/RESET voltage of ±3 V. The memory device shows stable retention behavior with the resistance ratio between both states maintained greater than 103. The bipolar nature of the voltage-induced hysteretic switching properties suggests changes in film conductivity related to the formation and removal of electronically conducting paths due to the presence of oxygen vacancies induced by the applied electric field. The effect of annealing on the switching behavior was related to changes in compositional and structural properties of the film. A transition from bipolar to unipolar switching behavior was observed upon O₂ annealing which could be related to different natures of defect introduced in the film which changes the film switching parameters. The HfO₂ resistive switching device offers a promising potential for high density and low power memory application with the ease of processing integration.     

A nanoanalytical investigation of elemental distributions in high-k dielectric gate stacks on silicon

Two high-k gate stacks with the structure Si/SiO₂/HfO₂/TiN/poly-Si are characterised using nanoanalytical electron microscopy. The effect of two key changes to the processing steps during the fabrication of the stacks is investigated. Electron energy-loss spectroscopy is used to show that the TiN layer has a very similar composition whether it is deposited by PVD or ALD. Spectrum imaging in the electron microscope was used to profile the distribution of elements across the layers in the stack. It was found that when the anneal after HfO₂ deposition is carried out in a NH₃ atmosphere instead of an O₂ atmosphere, there is diffusion of N into the SiO₂ and HfO₂ layers. There is also significant intermixing of the layers at the interfaces for both wafers.     

Role of N2 during chemical dry etching of silicon oxide layers using NF3/N2/Ar remote plasmas

In this work, the role of N₂ gas during the chemical dry etching of silicon oxide layers in NF₃/N₂/Ar remote plasmas was investigated by analyzing the species in the plasma, the reaction by-products in the exhaust, and the chemical properties of the etched surface. Increasing the N₂ gas flow rate resulted in an initial increase in the oxide etch rate up to a maximum value, followed by a subsequent decrease. The increased etch rate of the silicon oxide layers was not ascribed to the increased surface arrival rate of fluorine, but to the enhanced oxygen removal from the silicon oxide caused by the formation of NO₂ molecules. Presumably, the NO radicals formed from the added N₂ gas react chemically with the oxygen in the oxide, leading to the breaking of the Si-O bonds and the effective removal of oxygen, which in turn enhances the formation of SiF₄ resulting in an increased etch rate.     

Autodoping effects of Ge in vapor-grown GaAsl-xPx layers on the Ge substrates

Epitaxial growth of GaAs_1-xP_x layer on the Ge substrate has been investigated under the optimized growth conditions for reducing vapor etching of the substrate, using a Ga-PCl₃-AsH₃-H₂ system. The free carrier concentration, ?N_D⁺?N_A^??, and the electroluminescent properties of GaAs_1-xP_x layers with $\text{x ? 0·4}$ are studied, and are correlated with the Ge concentration involved. In the lightly doped region below 1×10¹⁷ atoms/cm³, bright electroluminescence is observed at room temperature from forward-biased p-n junctions fabricated by a zinc-diffusion technique. However, in the narrow region of 1×10¹⁷?4×10¹⁷ atoms/cm³, the enhanced amphoteric behavior of Ge leads to concentration quenching of visible-light emission. The ?N_D⁺?N_A^?? reaches its maximum at ～ 1×10¹⁷ atoms/cm³. Nearly complete self-compensation is observed above 4×10¹⁷ atoms/cm³ due to the increase of the concentration of deep-lying Ge acceptors.     

Carrier lifetimes in silicon epitaxial layers deposited on oxygen-implanted substrates

Carrier lifetimes in silicon epitaxial layers deposited on high-dose oxygen-implanted wafers have been obtained from measurements of diode storage times. A figure of 1.25 ?S was obtained for diodes in the implanted area, compared with 1.75 ?S for diodes outside the implanted area on the same wafer. This marginal degradation of lifetime indicates that the dielectrically isolated structure should be able to support bipolar and dynamic logic devices.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO₂ formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO₂-SiO₂ intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.     

Process integration of Pr-based high-k gate dielectrics

We present the process integration of the Pr-based high-k oxides Pr₂O₃, PrTi_xO_y and Pr_xSi_yO_z for CMOS devices. MOS structures were grown in form of p⁺ poly-Si/Pr-based dielectric/Si(100) by MBE. RIE with CF₄/O₂ plasma was used to selectively remove the poly-Si layer. It was found that the Pr-based oxides layers can be dissolved with high selectivity in diluted H₂SO₄ solutions. Details of the etch kinetics of Pr-based oxides and poly-Si were studied. Electrical characteristics of MOS stacks with integrated Pr_xSi_yO_z are presented.     

Materials characterization of WNxCy, WNx and WCx films for advanced barriers

A ternary WN_xC_y system was deposited in a thermal ALD (atomic layer deposition) reactor from ASM at 300 °C in a process sequence using tungsten hexafluoride (WF₆), triethyl borane (TEB) and ammonia (NH₃) as precursors. The WC_x layers were deposited by a novel ALD process at a process temperature of 250 °C. The WN_x layers were deposited at 375 °C using bis(tert-butylimido)-bis-(dimethylamido)tungsten (^tBuN)₂(Me₂N)₂W (imido-amido) and NH₃ as precursors. WN_x grows faster on plasma enhanced chemical vapor deposition (PECVD) oxide than WC_x does on chemical oxide. WN_xC_y grows better on PECVD oxide than on thermal oxide, which is opposite of what is seen for WN_x. In the case of the ternary WN_xC_y system, the scalability towards thinner layers and galvanic corrosion behavior are disadvantages for the incorporation of the layer into Cu interconnects. ALD WC_x based barriers have a low resistivity, but galvanic corrosion in a model slurry solution of 15% peroxide (H₂O₂) is a potential problem. Higher resistivity values are determined for the binary WN_x layers. WN_x shows a constant composition and density throughout the layer.     

Improved retention characteristic of charge-trapped flash device with sealing layer/Al2O3 or Al2O3/high-k stacked blocking layers

Although programming and erase speeds of charge trapping (CT) flash memory device are improved by using Al₂O₃ as blocking layer, its retention characteristic is still a main issue. CT flash memory device with Al₂O₃/high-k stacked blocking layer is proposed in this work to enhance data retention. Moreover, programming and erase speeds are slightly improved. In addition, sealing layer (SL), which is formed by an advanced clustered horizontal furnace between charge trapping layer and Al₂O₃ as one of the blocking layers is also studied. The retention characteristic is enhanced by SL approach due to lower gate leakage current with less defect. With the combination of SL and Al₂O₃/high-k stacked blocking layer approaches, retention property can be further improved.     

利用ICPCVD方法在GaN上沉积氧化硅薄膜的特性

使用感应耦合等离子体化学气相沉积(Inductively coupled plasma chemical vapor deposition,ICPCVD)方法在GaN上沉积SiOx薄膜,生长参数中采用不同RF功率,研究RF功率对薄膜物理性能和电学性能的影响.结果发现,随着RF功率增大,薄膜应力增大,表面粗糙度减小,薄膜致密度增大.选择最优的RF功率参数,制作了SiOx/nGaN金属-绝缘体-半导体(metal-insulator-semiconductor,MIS)器件,结果得到薄膜漏电流密度在外加偏压为90V时小于1×10-7A/cm2,SiOx/n-GaN界面态密度为2.4×1010eV-1cm-2.表明利用ICPCVD低温沉积的SiOx-GaN界面态密度低,薄膜绝缘性能良好.     

Performance of current mirror with high-k gate dielectrics

This work compares the performance of the basic current mirror topology by using two different materials for gate dielectrics, the conventional SiON and an Hf-based high-k dielectrics. The impact of gate leakage and of channel length modulation on the basic current mirror operation is described. It is shown that in the case of SiON gate dielectrics with an equivalent oxide thickness (EOT) of 1.4 nm, it is not possible to find a value for the channel length which allows a good trade-off to be obtained while minimizing the gate leakage and reducing the channel length modulation. On the other hand, the study demonstrates that in the case of HfSiON gate dielectrics with similar EOT, appropriate L values can be found obtaining very high output impedance current sources with reduced power consumption owing to low leakage and most of all with better parameter predictability.     

Comparison of La-based high-k dielectrics: HfLaSiON and HfLaON

For the first time, we present a comparative study on HfLaSiON and HfLaON gate dielectric with an equivalent oxide thickness (EOT) of 0.8 nm (T_inv = 1.2 nm). A detailed DC analysis of I_on vs. I_off shows HfLaON performs somewhat better than HfLaSiON. However, positive bias temperature instability (PBTI) lifetime of HfLaSiON is higher than HfLaON by about 2 orders of magnitude. On the other hand, hot carrier stress lifetime for HfLaSiON was similar to that of HfLaON. From the activation energy and U-trap, we found that the cause of different threshold voltage (V_T) shifts under PBT stress and detrapping was originated from stable electron traps induced by different charge trapping rates.     

Properties of the contact on ion cleaned n and p type silicon surfaces

Schottky contacts were produced by silver evaporation on Si(100) surfaces cleaned by ion sputtering and partial annealing. The samples work function were measured before and after metal deposition with the Kelvin method, in an experimental set-up which allowed a topografical study and direct comparison between n and p types. Clean surfaces with and without a residual layer of oxide was achieved and controlled by AES. It was found that the Fermi level of all the surfaces was pinned by donor states created by the bombardment and that there was no barrier on n type and an important surface barrier on p type. The diodes we obtained presented no barrier on n type and a rectifying contact on p type. So we deduced that the Schottky barrier is already fully formed before metal contact is achieved. Furthermore study of the electrical properties of the diodes had shown that the bombardment creates donor states responsible for the barrier and a perturbated layer with deep acceptor traps responsible for the current flow mechanism. A residual layer of oxide and a post annealing of the device did not noticeably change the Schottky barrier in the diodes achieved on p type but led to clearly differenciated performances for the diodes achieved on both p and n type substrate. So we therefore concluded that the characteristics of the deep acceptor traps of the superfacial layer are modified by the oxide and annealing, both of which on the other hand having no effect on the surface donor states.     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

Magnetic Properties of Al-Doped Na0.7Co1-xAlxO2

Single phase polycrystalline samples Na0.7Co1-xAlxO2 (x=0, 0.05, 0.10, 0.15, 0.20, 0.25, 0.30) were prepared by solid state reaction. The magnetic properties from 5 K to 300 K have been studied by dc and ac magnetic susceptibility measurements. Samples with lower doping quantity (x=0, 0.05, 0.10) showed paramagnetic behaviors, but those with higher doping quantity (x=0.20, 0.25, 0.30) showed spin-glass behaviors with a freezing temperature (Tf) of about 13 K.     

Properties of discontinuous gold thin films deposited on a silicon substrate

Experimental results on the dependence on deposition conditions of the electrical resistance and gauge factor of discontinuous gold films in the vicinity of the percolation threshold are reported. The three-dimensional nature of the films is emphasized. The gauge factor reveals anomalous behaviour.     

Correction of the temperature effect on the solar cell Isc − Voc characteristic

In this paper we present a simple method to determine the thermal resistance of a solar cell from its experimental I_sc ? V_oc characteristic. The knowledge of this parameter permits one to obtain the cell junction temperature and, consequently, the real I_sc ? V_oc characteristic of the cell. The method, which does not require any additional measurement, has been applied to our devices: reasonable agreement between theory and experiment was obtained.