Highly reliable copper dual-damascene interconnects with self-formed MnSi/sub x/O/sub y/ barrier Layer

Copper (Cu) dual-damascene interconnects with a self-formed MnSi/sub x/O/sub y/ barrier layer were successfully fabricated. Transmission electron microscopy shows that approximately 2-nm thick and continuous MnSi/sub x/O/sub y/ layer was formed at the interface of Cu and dielectric SiO/sub 2/, and that no barrier was formed at the via bottom because no oxygen was at the via bottom during annealing. No leakage-current increase was observed, and electron energy loss analysis shows that no Cu was in SiO/sub 2/, suggesting that MnSi/sub x/O/sub y/ layer has sufficient barrier properties for Cu, and that the concept of self-forming barrier process works in Cu dual-damascene interconnects. Via chain yield of more than 90% and 50% reduction in via resistance were obtained as compared with physical vapor deposited tantalum barrier, because there is no barrier at the via bottom. In addition, no failure in the stress-induced voiding measurement was found even after a 1600-h testing. No failure in electromigration (EM) testing was found, as the electron flow is from the lower level interconnects through via up to upper level interconnects even after 1000-h testing. At least, four times EM lifetime improvement was obtained in the case of electron flow from upper level interconnect through via down to lower level interconnects. Significant EM lifetime improvement is due to no flux divergence site at the via bottom, resulting from there being no bottom barrier at the via.     

Reliability challenges for copper interconnects

In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low-k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.     

铜互连新型阻挡层材料的研究进展

铜互连阻挡层材料起到防止铜与介质材料发生扩散的重要作用。因此,阻挡层材料需要满足高稳定性、与铜和介质材料良好的粘附性以及较低的电阻。自1990年代以来,氮化钽/钽(TaN/Ta)作为铜的阻挡层和衬垫层得到了广泛的应用。然而,随着晶体管尺寸微缩,互连延时对芯片速度的影响越来越重要。由于TaN/Ta的电阻率高且无法直接电镀铜,已经逐渐难以满足需求。文章综述了铜互连阻挡层材料的最新进展,包括铂族金属基材料、自组装单分子层、二维材料和高熵合金,以期对金属互连技术的发展提供帮助。     

Improving Reliability of Copper Dual-Damascene Interconnects by Impurity Doping and Interface Strengthening

Electromigration (EM)-derived void nucleation and growth in 65-nm-node dual-damascene interconnects were investigated, and the effects of impurity doping as well as copper adhesion strength to a capping-dielectric layer (CAP) are clarified. It is found that surface-reductive treatment of the copper line improves its adhesion to the SiCN-CAP, elongating the incubation time of voiding at the via bottom. An aluminum doping is effective in suppressing both the void nucleation and growth. Consequently, an aluminum-doped copper alloy with the strong copper/CAP interface improves the EM lifetime by 50 times compared to that of a conventional pure copper. These results clearly indicate that blocking migration paths of vacancies through both grain boundaries and the copper/CAP interface is essential in improving the EM reliability.     

超薄Ru/TaN双层薄膜作为无籽晶铜互连扩散阻挡层

研究了钌（Ru) /氮化钽（TaN）双层结构对铜的扩散阻挡特性，在Si (100）衬底上用离子束溅射的方法沉积了超薄Ru/TaN以及Cu/Ru/TaN薄膜，在高纯氮气保护下对样品进行快速热退火，用X射线衍射、四探针以及电流-时间测试等表征手段研究了Ru/TaN双层结构薄膜的热稳定性和对铜的扩散阻挡特性. 同时还对Ru/TaN结构上的铜进行了直接电镀. 实验结果表明Ru/TaN双层结构具有优良的热稳定性和扩散阻挡特性,在无籽晶铜互连工艺中有较好的应用前景.     

Void control during plating process and thermal annealing of through-mask electroplated copper interconnects

The quality of the sputtered copper film, which serves as the seed layer for sequent electroplating, becomes critical when the size of crack on the surface of the sputtered film is close to the feature size of the electroplated copper interconnect. The crack results in void formation in electroplated copper before thermal annealing and this phenomenon limits attainable highest anneal temperature. To solve this problem, the sputtered seed layer was slightly etched before electroplating process and a TaN passivation layer was deposited on the electroplated Cu interconnect before thermal annealing. Those processes not only suppressed void formation during the electroplating and annealing process at 300 °C, but also resulted in lower electrical resistance in the copper interconnects.     

Effects of material interfaces in Cu/low-/spl kappa/ damascene interconnects on their performance and reliability

The performance and reliability of Cu/Low-/spl kappa/ damascene interconnects are investigated from the view point of the material interface structure. We are focusing especially on the heterointerfaces between the Cu and the barrier metal (BM), as well as between the hard mask (HM) and the capping barrier dielectrics (CAP) covered on the Cu interconnects. It is found that the highest via reliabilities of electromigration (EM) and thermal cycle are established by the barrier-metal-free (BMF) structure without the heterointerface between the Cu and the BM due to the strong Cu-to-Cu connection at the via bottom. The interline time-dependant dielectric breakdown lifetime is improved mostly by using a HM with the same materials as the CAP layer, referred to as an unified structure, which diminishes the heterointerface between the HM and the CAP. These ideal structures without the material heterointerfaces derive the highest reliability and performance. Structural control of the material heterointerfaces in the actual Cu/low-/spl kappa/ damascene interconnect is crucial for the high reliability and performance.     

Reliability and early failure in Cu/oxide dual-damascene interconnects

Recent results on up-direction electromigration (EM) studies on Cu dual-damascene (DD) interconnects are presented. The issue of the DD process and its potential effect on EM reliability is described with special focus on the peculiarities of the DD interconnect architecture in comparison to the previous subtractively etched Al-based interconnect technology. Experiments performed on multilink, DD interconnects that highlight EM reliability issues, such as early failure, and the Blech effect are summarized.     

柠檬酸在钴基铜互连CMP及后清洗的研究进展

钴(Co)具有较低的电阻率、良好的热稳定性、与铜(Cu)粘附性好等优点,可以替代钽(Ta)成为14 nm以下技术节点集成电路(IC) Cu互连结构的新型阻挡层材料。化学机械抛光(CMP)是唯一可以实现Cu互连局部和全局平坦化的方法,也是决定Co基Cu互连IC可靠性的关键技术。柠檬酸含有羟基,在电离后对金属离子有较强的络合作用,成为Co基Cu互连CMP及后清洗中的主要络合剂。文章评述了柠檬酸在Cu互连CMP及后清洗中的应用和研究进展,包括柠檬酸对Cu/Co去除速率选择比、Co的表面形貌以及Co CMP后清洗中Co表面残留去除等方面的影响,并展望了络合剂及Cu互连阻挡层CMP的发展趋势。     

Effects of Ti addition on via reliability in Cu dual damascene interconnects

We investigated the effects of a Ti addition on the reliability and the electrical performance of Cu interconnects, comparing three different ways of Ti addition such as A) Ti layer insertion under Ta-TaN stacked barrier metal, B) Ti layer insertion between a Ta-TaN barrier and Cu, and C) the Ti doping from the surface of the electrochemical-plated (ECP) Cu film. The structure-A drastically suppresses the stress-induced voiding (SIV) under the via connected to a wide lower line due to adhesion improvement by Ti at the via-bottom, while the electromigration (EM) is not improved. In the structure-B, by contrast, the EM is improved but the SIV resistance is degraded. The Ti doping from the bottom surface of Cu film restricts the grain growth and increases the tensile stress, enhancing the SIV. The structure-C improves not only the SIV but also the EM resistance. The oxygen gettering effect of Ti during the ECP-Cu annealing is a reason for the reliability improvements of the SIV and the EM. The improvement of adhesiveness at the interface between the via and the lower Cu line, and the oxygen gettering from Cu by Ti play an important role in suppressing the SIV and the EM.     

集成电路铜互连线及相关问题的研究

论述了Cu作为互连金属的优点、面临的主要问题及解决方案,介绍了制备Cu互连线的双镶嵌工艺及相关工艺问题,讨论了Cu阻挡层材料的作用及选取原则,对低k材料的研究的进展情况也了简要的介绍。     

Barrier-free direct-contact-via (DCV) structures for copperinterconnects

New barrier-free direct-contact-via (DCV) structures applicable to 0.18 μm integrated circuits have been developed based on step coverage of the Ta barrier and time-controlled plasma etching. The via resistance in the novel DCV structures could be reduced to 29%, while the breakdown voltage in the novel DCV structures can be enhanced to 150%     

伪通孔对铜互连应力诱生空洞的影响

基于铜的随动强化模型,使用三维有限元方法,分析在窄-宽线铜互连结构中添加伪通孔对互连应力诱生空洞的影响。对宽互连M1分别为无伪通孔、中间添加伪通孔、右侧边沿添加伪通孔和添加双伪通孔结构进行了研究。结果表明,添加伪通孔不但可以降低通孔底部互连M1区域的空洞生长速率,而且使伪通孔正下面的互连M1成为额外的空位收集器,从而有效地提高互连应力诱生空洞性能,双伪通孔可进一步增强应力诱生空洞性能。     

Comparative study of novel barrier layers in ULSI copper interconnects

As ULSI dimensions shrink, conventional Ta/TaN barriers will not meet the future demands for ULSI interconnects, i.e. thin conformal layer without overhangs. In this paper, we have compared the material properties of TaN/Ta barriers with Ta only and W based barriers by means of XRD, AFM, Stress and SEM imaging. We found that using a conformal CVD W based barriers has great potential for future ULSI interconnects. It grain size and tensile stress improve resistance to both electromigration and stress migration, extending conductor lifetime.     

Evaluation of CVD/PVD multilayered seed for electrochemicaldeposition of Cu-damascene interconnects

Multilayered seed for electrochemical deposition (ECD) of Cu was investigated to develop narrow-pitched, dual-damascene Cu interconnects that will be required for future ULSI devices. The seed was obtained by the physical vapor deposition (PVD) of a Cu film followed by the chemical vapor deposition (CVD) of a Cu film. The seed of the thinner CVD-Cu element and the thicker PVD-Cu element demonstrated better filling characteristics in high-aspect ratio vias. Good current-voltage characteristics were demonstrated using the multilayered seed technique with Cu dual-damascene interconnects (0.28 μm minimum via size) resulting in a via resistance about 0.7 Ω. In addition, ring-oscillator circuits were fabricated by integrating the double-layered interconnects with a transistor having a 0.18 μm gate width. The propagation delay per inverter, which had an interconnect with 10⁴ vias, was about 6 ns. We successfully fabricated multilevel Cu-damascene interconnects, which are available for future high-speed devices using this multilayered seed technique     

Post electrochemical Cu deposition anneal impact on stress-voiding in individual vias

Stress-voiding is a critical reliability issue in Cu dual-damascene interconnects which could induce via openings. In our case, voids are typically observed at the edges at the bottom of vias. This location is correlated to a local delamination at Cu/Ta interface [E.T. Ogawa, J.W. McPherson, J.A. Rosal, M.J. Dickerson, T.-C. Chiu, L.Y. Tsung, M.K. Jain, T.D. Bonifield, J.C. Ondrusek, W.R. McKee, IEEE Int. Rel. Phys. Symp. Proc. (2002) 312-321; Y.K. Lim et al., Stress-induced voiding in multi-level copper/low-k interconnects, IEEE Int. Rel. Phys. Symp. Proc. (2004) 240-245]. Then, Cu/Ta interface properties at the bottom of via seem to be in the critical path for stress-voiding. In this paper, stress-voiding on 300 mm wafers in individual vias for different post electrochemical Cu deposition (ECD) anneals is studied. Electrical results show the clear benefit of hot plate and short furnace annealings. Microstructural characterizations indicate that impurities accumulation at Cu/Ta interface during long annealings could drive preferred void nucleation.     

Cu contact on NiSi substrate with a Ta/TaN barrier stack

The thermal and electrical stabilities of Cu contact on NiSi substrate with and without a Ta/TaN barrier stack in between were investigated. Four-point probe (FPP), X-ray diffraction (XRD), scanning electron microscopy (SEM), depth-profiling X-ray photoelectron spectroscopy (XPS), and Schottky barrier height (SBH) measurement were carried out to characterize the diffusion barrier properties. The SBH measurement provides a very sensitive method to characterize the diffusion barrier properties for the copper contact on NiSi/Si. The results show that the Ta/TaN stack can be both thermally and electrically stable after annealing at 450 °C for 30 min and it will have a potential application as a diffusion barrier for Cu contact on NiSi.     

Characterization and modeling of electromigration failures inmultilayered interconnects and barrier layer materials

Electromigration failure mechanisms of TiN/Al-alloy/TiN multilayered interconnect and TiN, TiW barrier layer materials have been studied. The stress induced in Al electromigration instead of severe joule-heating has been attributed to the damage healing or resistance oscillation observed in TiN/Al-alloy/TiN multilayered interconnects. The lifetime dependence on interconnect geometry (length and width) for multilayered structures has been investigated. The experimental results show that the failure observed in TiN and TiW barrier layer materials was not caused by electromigration, instead it was due to a thermally activated process. The activation energy of this thermal process for TiN was found to be 1.5 eV. A 10-year lifetime was projected to be attainable if the hottest spot in TiN film was kept below 408°C. This suggests that TiN may safely conduct 2.4×10⁷ A/cm ² for the typical thermal impedance of a hot spot     

Via-Shape-Control for Copper Dual-Damascene Interconnects With Low-k Organic Film

Copper dual-damascene (DD) interconnects are fabricated with low-k organic film (SiLKtrade) without any etch-stop layers by use of dual hard mask (dHM) process combined with sidewall-hardening etching step. It is a key point to reduce shoulder loss during trench etching at connecting regions of vias and trenches, so that hardening of the via-sidewall by fluorocarbon plasma during via etching is implemented. Careful designs of dual hard mask structures and their patterning sequence are carried out for the process without etch-stop layer under the trench. The two-layered interconnect with low-k structure has achieved low via-resistance of 0.65 Omega at 0.28 mumOslash with keeping large tolerance of misalignment up to 0.1 mum.