A new complementary monolithic transistor structure

A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process a pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure.     

A new complementary bipolar transistor structure

A novel complementary monolithic bipolar transistor structure has been developed. By adding one extra diffusion to the standard monolithic bipolar transistor process, a complementary pair of high current gain and very low saturation resistance n-p-n and p-n-p transistors can be fabricated on the same chip. High sheet resistances are also present in this structure. Novel low-voltage (1.3 V) complementary digital circuits have been fabricated by this new process.     

Diode operation of a transistor in functional blocks

Many functional blocks have a basic double-diffused three-layer n-p-n or p-n-p structure to permit the incorporation of transistors. If diodes are also to be incorporated in the block, it is often more convenient to connect the transistor structure already present as a diode so that "batch" processing can be used. There are five different ways to connect a transistor as a diode, either by opening certain electrodes or by short-circuiting a pair of electrodes. The different connections are compared both analytically and experimentally on the basis of forward voltage drop, recovery time and reverse characteristics. It is found that the shorted collector -base connection has the shortest recovery time, comparable to fast computer diodes, and a lower forward voltage drop than the open collector diode connection. The performance is almost equivalent to a diode with a metallic contact in place of the collector. The shorted emitter-base connection has the lowest forward voltage drop. There is good agreement between theory and experiments. The applications of this analysis to the design and fabrication of a high-speed nonsaturated diode-emitter follower AND gate functional block will be illustrated.     

Lateral insulated-gate bipolar transistor (LIGBT) with a segmentedanode structure

A novel lateral insulated-gate bipolar transistor (LIGBT) structure, called the segmented anode LIGBT, is presented. In this structure, the anode, which is responsible for the injection of minority carriers for conductivity modulation, is implemented using segments of p ⁺ and n⁺ diffusions along the device width. This segmented design of the anode structure results in higher switching speed and reduction in device size. Depending on the value of the specific ON resistance, experimental results show that the segmented anode LIGBT has from 20% to 250% reduction in turn-off time as compared to the shorted anode LIGBT     

A high-performance lateral geometry transistor for complementary integrated circuits

The lateral geometry transistor has shown itself to be highly useful in the realization of low-frequency integrated circuits. This simple structure has been limited essentially to dc applications, however, by bandwidth and switching time performance. The p-n-p device to be described in this paper substantially overcomes these deficiencies by the addition of an n+ diffusion directly beneath the emitter region. As a result of the steeper gradient at the bulk, or planar, portion of the emitter-base junction, injection occurs primarily near the surface. It is possible to control the dimensions of the buried layer such that injection of carriers greater than a few micrometers from the collector will be minimized. A further consequence of the n+ region is the introduction of a graded base such that minority carrier transport is enhanced. The improved transistor structure has demonstrated the feasibility of obtaining an f_{T} of 10 MHz to 20 MHz at collector currents of 100 µA and rise, fall, and storage times in the tens of nanoseconds.     

Thin-film transistor fabrication for high brightness reconfigurablevacuum fluorescent displays

The design and fabrication of a thin-film transistor array for use in a reconfigurable, active matrix vacuum fluorescent display suitable for high ambient light operating conditions such as automotive instrument clusters is described. Thin-film transistor (TFT) arrays were fabricated in a novel 4-transistor per pixel configuration using a p-channel polycrystalline silicon transistor fabrication process. Display assembly was then completed by the Futaba Corporation. The robust transistor structure is capable of enduring the 550°C post-processing anneal temperature associated with phosphor deposition and packaging, Initial displays yielded luminances of 2500 ftL when operated at 40 V, and suggest an ultimate brightness of 5000 ftL for 55 V operation     

An analysis and the fabrication technology of the lambda bipolar transistor

A new type of voltage-controlled negative-differential-resistance device using the merged integrated circuit of an n-p-n (p-n-p) bipolar transistor and an n(p)-channel enhancement MOSFET, which is called the Lambda bipolar transistor, is studied both experimentally and theoretically. The principal operation of the Lambda bipolar transistor is characterized by the simple circuit model and device physics. The important device properties such as the peak voltage, the peak current, the valley voltage, and the negative differential resistance, are derived in terms of the known device parameters. Comparisons between the characteristics of the fabricated devices and the theoretical model are made, which show that the analysis is in good agreement with the observed device characteristics.     

An epitaxial planar structure for the unijunction transistor

A unijunction transistor with fast recovery time and high interbase resistance is made by growing a thin high-resistivity boron-doped epitaxial layer on a low-resistivity arsenic-doped substrate. Ring-and-dot base contacts are made directly on the p-type epitaxial layer with the beam-lead contact process. With the dot grounded and a negative bias on the ring, the most positive point along the edge of the space-charge region in the epitaxy is centered below the dot. When the substrate is adequately biased in the forward direction with respect to this point, conductivity modulation of the spreading resistance under the dot begins because of minority charge injection from the substrate. Experimental devices have been made by growing a 7.1-micron 53.1-Ω.cm epitaxial layer on a 5Ω.cm substrate. Interbase resistance was ∼ 100k Ω, intrinsic stand-off ratio ∼ 0.5, holding current ∼ 1 mA, and recovery time <20 ns. The paper concludes with possible memory array and shift register circuit applications that incorporate the unit described as well as a junction-isolated version that is free of parasitic transistors.     

Low temperature fabrication of a ZnO nanoparticle thin-film transistor suitable for flexible electronics

A bottom-gate/top-drain/source contact ZnO nanoparticle thin-film transistor was fabricated using a low temperature annealing process (150 °C) suitable for flexible electronics. Additionally, a high-k resin filled with TiO₂ nanoparticles was used as gate dielectric. After fabrication, the transistors presented almost no hysteresis in the I–V curve, a threshold voltage (V_T) of 2.2 V, a field-effect mobility on the order of 0.1 cm²/V s and an I_ON/I_OFF ratio of about 10⁴. However, the transistor is sensitive to aging effects due to interactions with the ambient air, resulting in current level reduction caused by trapped oxygen at the nanoparticle surface, and an anti-clockwise hysteresis in the transfer curve. It was demonstrated, conjointly, the possible desorption of oxygen by voltage stress and UV light exposure.     

Optimization of transistor structure for transistor-stabilizedfield emitter arrays

Reliability of the metal-oxide-semiconductor field-effect transistor (MOSFET)-stabilized field emitters at high-field operation has been assessed by comparing two different MOSFET structures. Electrical characteristics and behavior of carriers in the device structure have been investigated by means of device simulation. One structure, which is referred to as the externally connected-MOSFET emitter, exhibits an anomalous increase in drain current, which is induced by impact ionization at the drain edge. Upon evaluating the emission characteristics, it was clarified that the anomalous current increase induced by the impact ionization degraded stability and controllability of the emission current significantly. The other structure, which is referred to as the MOSFET-structured emitter, shows higher reliability with negligible effect of impact ionization     

SIPOS纵向结构对晶体管电压特性的影响

通过对半绝缘多晶硅(SIPOS)膜纵向结构均匀性不同结果的对比,论述了SIPOS膜成分的纵向结构分布对晶体管的钝化作用的影响,同时根据实际生产提出一些改进SIPOS膜结构的方法。     

Efficient transient analysis of transistor circuits from device fabrication data

Tabulated values of transistor charge-current-voltage characteristics are generated directly from device process parameters An efficient numerical Laplace inversion method is used with a piecewise-linear approximation technique to obtain the time response of the transistor in a given circuit.     

Feasible approach for processes integration of CMOS transistor gate/side-wall spacer patterning fabrication

As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly critical manufacturing process. In recent CMOS technologies, side-wall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present approach to overcome these fabrication limitations. The spacer patterning technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical integrated lithography and etching processes. Generally relates to semiconductor manufacturing, and more particularly to nanotechnology fabrication feasibility for CMOS wafer process on gate spacer technology manufacture feasibility. A modified side-wall spacer patterning method was implemented for using conventional lithography and etching processing technology. Based on the systematical investigation of the effects of the various etch conditions on etching profile and their impacts on the sidewall transistor gate structure, a novel integrated process for well controlled side-wall spacer formation was developed for fabrication.     

Design, fabrication, and characterization of a germanium microwave transistor

This paper summarizes the design, fabrication, and characterization of a p-n-p planar epitaxial germanium transistor for use as an amplifier in the 1-to 4-GHz frequency range and as a high-speed switch. The analytical basis for the geometry and impurity profile arrived at in the development of this transistor is presented in conjunction with experimental measurements. It is shown that good agreement between experiment and theory can be achieved even in the 1-to 6-GHz frequency region when sufficient attention is given to the formulation of an adequate equivalent circuit. For example, the calculated fTof this germanium microwave transistor is 5.7 GHz, which compares to a typical measured value of 5.6 GHz. The measured maximum available gain of the better transistors is 13.4 dB at 1.3 GHz (the corresponding calculated value is 13.9 dB) with a 2.7-dB noise figure at the same frequency.     

HBT结构的新进展

介绍了以In0.03Ga0.97As0.99N0.01材料为基区的GaAs异质结双极型晶体管和以GaAs0.51Sb0.49材料为基区的InP HBT.讨论了GaAs和InP HBT结构的新进展及其对性能的改善,并对各结构的适用范围和优缺点进行了比较.     

Design, fabrication and operation of a hot electron resonant tunneling transistor

Transistors employing resonant tunneling injection of hot electrons into a thin quantum well base region have been fabricated. The base region in these transistors is formed by a narrow bandgap material like InGaAs so that the first level is a confined one lying below the Fermi level in the contact regions. This results in charge transfer into the bound state in the quantum well thus allowing independent control of the base electrostatic potential. Theoretical calculations showing the importance of various device parameters in the design of a resonant tunneling transistor are presented and preliminary results showing the capability of transistor action in such devices are presented.     

Selective alignment of a ZnO nanowire in a magnetic field for the fabrication of an air-gap field-effect transistor

An air-gap field-effect transistor (FET) was prepared by selectively aligning a Ni-capped ZnO nanowire in a magnetic field on a pre-fabricated electrode patterns formed by lithography. It was demonstrated that the magnetic alignment technique could be applied effectively to the fabrication of air-gap nanowire FETs with desired circuit configurations. This device showed operational characteristic strongly dependent on the possible surface adsorbates originating from the negatively charged oxygen related species, as compared to the back-gate nanowire FET separately prepared for comparison. These results will illuminate the prospect of realizing producible matrix-type devices based on one-dimensional nanostructures such as logic circuits and biochemical sensors.     

Step and flash imprint lithography for quantum dots based room temperature single electron transistor fabrication

In this work we demonstrate the successful fabrication using step and flash imprint lithography – reverse tone (SFIL-R)? coupled with a novel Focus ion beam (FIB) quantum dot (QD) deposition technique to produce of a full array of room temperature single electron transistors (RT-SET) based on tungsten quantum dot arrays. The integration of SFIL-R and FIB technology process flow has been developed in order to explore the possibility of an ultra low power, monolithically integrated nano-electronics circuits using RT-SET. We describe the parallel production of RT-SET devices using SFIL-R. The yield of the mass produced devices are examined. These QD based devices are characterized and initial results are evaluated.     

Generation of transient response of nonlinear bipolar transistor circuits from device fabrication data

Dynamic models of double diffused bipolar transistors are generated from device fabrication data. The models consist of interconnections of two- and three-terminal resistors and capacitors whose characteristics are expressed in the form of tabulated values describing piecewise-linear surfaces. A circuit analysis program based on a piecewise-linear approach, simulates the time responses of circuits in which the transistors are imbedded. DC and small-signal AC analyses are also obtained. The computer program package thus yields overall circuit responses with fabrication data as input.     

高电子迁移率晶体管新结构

介绍了通过插入ＩｎＡｓ层到ＩｎＧａＡｓ沟道中，改善了ＩｎＡｌＡｓ／ＩｎＧａＡｓ高电子迁移率晶体管（ＨＥＭＴ）的性质，合适的ＩｎＡｓ层厚度和准确的插入位置会使在３００Ｋ时此结构的ＨＥＭＴ比普通结构的ＨＥＭＴ的迁移率和电子速度分别提高３０％和１５％。