Mechanical integrity analysis of multilayer insulator coatings on flexible steel substrates

The cohesive and adhesive properties, and related critical radius of curvature of thin multilayer insulator coatings on a 152 μm thick flexible steel substrate were investigated using tensile experiments carried out in-situ in an optical microscope. This method was found to be well adapted for the two types of coatings studied: SiO₂ single layers with different thickness and SiO₂/SiN_x/polyimide stacks. Special attention was paid to the influence of surface roughness and yielding of the steel substrate. Coating delamination and spallation was observed at low strain in case of SiO₂ coatings on unpolished steel, resulting from roughness-induced stress concentrations and slippage of grain boundaries. Polishing the steel substrate, or using a polyimide interlayer, was found to be useful to avoid premature delamination of the layers. In all investigated cases, a critical radius of curvature for layer damage of approximately 5 mm was found.     

Electrical characterization of MIS capacitors fabricated from ECR-PECVD silicon oxide and silicon nitride bilayer films

In this study, a comparative electrical characterization of Al/SiN _x /Si and Al/SiN _x /SiO₂/Si MIS structures has been carried out. Both SiO₂ and SiN _x films have been deposited by using electron-cyclotron resonance plasma-enhanced chemical vapor deposition method. C–V results show that samples without SiO₂ have more defects than those with SiO₂. Deep-level transient spectroscopy and conductance transient measurements demonstrate that as for the samples containing the SiO₂ film, these defects are mostly concentrated in the insulator/semiconductor interface, whereas in the other case defects are spatially distributed into the insulator.     

Electric conductivity of a bulk composite based on Bi<Subscript>2</Subscript>Te<Subscript>3</Subscript>/SiO<Subscript>2</Subscript> core-shell nanoparticles

Composite Bi₂Te₃/SiO₂ nanoparticles of the core-shell type have been synthesized for the first time with a view to creating bulk composites possessing high thermoelectric figure of merit (conversion efficiency). It is suggested that bulk composited based on Bi₂Te₃/SiO₂ nanoparticles will provide a combination of low lattice heat conduction due to SiO₂ insulator and rather high electric conduction due to charge-carrier tunneling via dielectric spacers between adjacent Bi₂Te₃ semiconductor grains. The electric resistance of the composite increases with increasing temperature in the range of 130–300 K. This temperature dependence can be described in terms of a tunneling conduction model.     

Light-induced resistive switching in silicon-based metal–insulator–semiconductor structures

We have studied light-induced resistive switching in metal–insulator–semiconductor structures based on silicon covered with a tunneling-thin SiO₂ layer and nanometer-thick layer of antimony. The role of an insulator was played by yttria-stabilized zirconia.

     

Single- and double-layer insulator metal-oxide-semiconductor capacitors on indium arsenide

Single- and double-layer insulator MOS capacitors on InAs were investigated for possible MOS device applications. The single layers were formed by anodic oxidation or by reactive evaporation of SiO₂. The double layers were formed by depositing SiO₂ on the anodic oxide. With the anodically oxidized InAs, the fast state and fixed charge densities were respectively two and five time greater than with the deposited SiO₂. The slow state densities were approximately the same for these insulators. No collected charge between the two insulators of the double-layer capacitors was observed.     

Fabricating gate insulator by low temperature solution-based process

Solution-processed gate insulator was fabricated using polymethylphenylsilane (PMPS) as a liquid precursor. The spin-coated PMPS films were transformed into SiO₂ films after exposing to ultraviolet (UV) with 365 nm of wavelength. Fourier transform infrared spectra showed the variations of photo oxidation according to UV exposing time. The peak intensity of Si-O-Si bond increases with the UV energy, while the intensities of the methyl and phenyl peaks decrease. The electrical characteristics of PMPS-based spin-on glass (PMPS-SOG) were analyzed by capacitance-voltage and leakage current measurements. The dielectric constant was 4.14 and leakage current density was 10^− 7 A/cm². The low temperature below 200 °C fabrication processing of PMPS-SOG could be achieved by UV exposing. PMPS-SOG, forming SiO₂, is applicable to gate insulator by low temperature solution-based process.     

Trapping states in thin film transistors measured by thermally stimulated currents

Thermally stimulated current measurements were made on MIM capacitors of sputtered SiO₂ and on SiO₂/CdSe thin film transistors. The peaks in the spectra were interpreted in terms of trapping states in the insulator and defect levels in the semiconductor. Fast interface and grain boundary states, if present, have densities below the detection level of 10¹⁹ m^-3.     

High-performance ZnO thin film transistors with sputtering SiO2/Ta2O5/SiO2 multilayer gate dielectric

A high-performance ZnO thin film transistor （ZnO-TFT） with SiO₂/Ta₂O₅/SiO₂ (STS) multilayer gate insulator is fabricated by sputtering at room temperature. Compared to ZnO-TFTs with sputtering SiO₂ gate insulator, its electrical characteristics are significantly improved, such as the field effect mobility enhanced from 11.2 to 52.4 cm²/V s, threshold voltage decreased from 4.2 to 2 V, and sub-threshold swing improved from 0.61 to 0.28 V/dec. The improvements are attributed to the high gate capacitance (from 50 to 150 nF/cm²) as well as nice surface morphology by using dielectric with high～k Ta₂O₅ sandwiched by SiO₂ layers. The capacitance-voltage characteristic of a metal-insulator-semiconductor capacitor with the structure of Indium Tin Oxide/STS/ZnO/Al was investigated and the trap charges at the interface or bulk is evaluated to be 2.24 × 10¹² cm⁻². From the slope of C⁻² versus gate voltage, the doping density N_D of ZnO is estimated to be 1.49 × 10¹⁶ cm⁻³.     

Mechanical failure analysis of thin film transistor devices on steel and polyimide substrates for flexible display applications

The crack onset strain (COS) of 4-level thin film transistor (TFT) devices on both steel foils and thin polyimide (PI) films was investigated using tensile experiments carried out in situ in an optical microscope. Cracks initiated first within the SiO₂ insulator layer for both types of substrates. The COS was found to be equal to 1.15% and 0.24% for steel and PI, respectively. The influence of loading direction on failure of the TFT stack with anisotropic geometry was moreover found to be considerable, leading to recommendations for backplane design. The large difference in critical strain of the SiO₂ layer on the two substrates was analyzed using an energy release rate approach, and found to result from differences in layer/substrate mechanical contrast and in internal stress state. Based on this analysis a correlation between layer/substrate elastic contrast and tensile failure behavior was devised.     

Thermal annealing effects on the interface state density of metal-oxide-semiconductor capacitors with electron cyclotron resonance plasma enhanced chemical vapor deposition Silicon dioxide

Silicon dioxide films (SiO₂), deposited at room temperature by electron cyclotron resonance (ECR) plasma reactor from a gas phase combination of O₂, SiH₄ and He, present excellent structural and electrical properties. However, when fabricating field effect devices it is also crucial to minimize the defect density at the semiconductor/insulator interface. We show that the interface state density, investigated in Al/SiO₂/Si MOS capacitors, can be substantially reduced performing post-deposition annealing. In particular we studied the effects of annealing temperature and time in different gas ambient: vacuum, nitrogen and forming gas (5% H₂ + N₂). We found that interface state passivation mainly occurs when thermal annealing is performed after Al-contact deposition and that it is quite insensitive to the annealing atmosphere. The present results clearly suggest that the hydrogen passivation mechanism is driven by the H-containing species present in the film and a possible mechanism to explain the results is proposed.     

Effect of N2O plasma treatment on the improvement of instability under light illumination for InGaZnO thin-film transistors

This paper investigates the impact of N₂O plasma treatment on the light-induced instability of InGaZnO thin film transistors with a SiO₂ passivation layer deposited by plasma-enhanced-chemical-vapor-deposition (PECVD). For the untreated device, because the deposition of the SiO₂ passivation layer by PECVD causes extra trap states, the anomalous subthreshold leakage current can be attributed to a lowering of the source side barrier due to trap-assisted photogenerated holes. In contrast, the N₂O plasma treatment applied to both the gate insulator and the active layer effectively suppresses the device instability under illumination. In order to clarify the influence of the N₂O plasma treatment, this study investigates a device with treatment of only the gate insulator. This device shows a slight decrease of light-induced subthreshold leakage current. This demonstrates that N₂O plasma treatment on IGZO active layer after its deposition is critical in preventing damage from the subsequent SiO₂ passivation deposition process. In addition, the instability of threshold voltage (V_T) under negative bias illumination stress (NBIS) is significantly improved by the N₂O plasma treatment. Furthermore, a different dark recovery rate follows NBIS for untreated and N₂O plasma-treated devices, indicating different hole-trapping levels exist in the energy band.     

Synthesis of multilayered composite nanotube heterostructure; SiC–SiO2, C–SiO2, and C–SiC–SiO2 nanotubes

Three types of composite nanotube heterostructures (two double-layered and one triple-layered structure) are synthesized by simple heat treatment, forming SiC–SiO₂, C–SiO₂, and C–SiC–SiO₂ composite coaxial nanotubes. These multilayered composite nanotubes consist of several components with different electrical properties, for example, metal, semiconductor, and insulator components. In particular, C–SiC–SiO₂ triple-layered nanotubes with metallic, semiconducting, and insulating layers are synthesized for the first time. These multilayered nanotubes can be expected to find applications in nanoscale heterostructure electronic and optical devices.     

Interface reactions at TiN/HfSiON gate stacks: Dependence on the electrode structure and deposition method

We systematically investigated intrinsic and extrinsic thermal reactions at TiN/HfSiON gate stacks. The formation of an ultrathin TiO₂ interlayer was found to be an intrinsic reaction at the metal/insulator interface, but growth of SiO₂ underlayers between HfSiON and Si substrates, which determines the electrical thickness of metal-oxide-semiconductor (MOS) devices, depends on the structure and deposition method of the gate electrodes. Physical vapor deposition (PVD) grown TiN electrodes covered with W overlayers exhibited excellent thermal stability at up to 1000 °C. Formation of ultrathin TiO₂ interlayers reduced gate leakage current (I_g), and growth of the oxide underlayer was suppressed by less than a few angstroms even for 1000 °C annealing. In contrast, we found that halogen impurities within CVD-grown metal electrodes enhance interface SiO₂ growth, resulting in deterioration of equivalent oxide thickness (EOT) versus I_g characteristics of the gate stacks.     

Rutile-type TiO2 thin film for high-k gate insulator

We investigated rutile-type titanium dioxide (TiO₂) films for possible use as a high-k gate insulator. The TiO₂ thin films were directly deposited on Si substrates using a RF magnetron sputtering method with a sintered oxide target. A single phase of rutile-type TiO₂ whose dielectric constant of approximately 75 was obtained when the film was deposited in an inert gas atmosphere and annealed at 800 °C in an oxidizing gas atmosphere. The oxygen ions were deficient in the as-deposited film, and consequently, a sufficient oxygen supply was needed to crystallize the film to a single phase of rutile during the post-annealing. However, the interfacial SiO₂ layer between the TiO₂ and the Si substrate simultaneously grew thicker than 2 nm. As the interfacial SiO₂ grew, the leakage current was decreased and the equivalent oxide thickness was increased, in the Au/rutile-type TiO₂/Si capacitor. Therefore, we concluded that the growth of the interfacial SiO₂ layer thicker than 2 nm is inevitable to form the single phase of rutile-type TiO₂ and to decrease the leakage.     

N-channel thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride with ultrathin polymer gate buffer layer

N-channel operation of thin-film transistors based on 1,4,5,8-naphthalene tetracarboxylic dianhydride (NTCDA) with a 9-nm-thick poly(methyl methacrylate) (PMMA) gate buffer layer was examined. The uniform coverage of the ultrathin PMMA layer on an SiO₂ gate insulator, verified by X-ray reflectivity measurement, caused the increase of electron field-effect mobility because of the suppression of electron traps existing on the SiO₂ surface. In addition, air stability for n-channel operation of the NTCDA transistor was also improved by the PMMA layer which possibly prevented the adsorption of ambient water molecules onto the SiO₂ surface.     

Hysteresis in metal insulator semiconductor structures with high temperature annealed ZrO2/SiOx layers

Hysteresis behaviour in sandwich structure — zirconium oxide/chemical silicon oxide, annealed at temperature of 850 °C in oxygen ambient, was studied. Formation of thin ZrSi_xO_y layer due to the high temperature annealing was found. Metal-insulator-semiconductor (MIS) capacitors using ZrO₂/ZrSi_xO_y/SiO_x insulator were studied. High-frequency capacitance-voltage (HF C-V), current-voltage (I-V) and current-time (I-t) measurements were carried out on the Al/ZrO₂/ZrSi_xO_y/SiO_x/Si capacitors.Two leakage current components were identified — tunneling current component at high electric fields and transient current component at low fields. The transient leakage currents are due to charge trapping phenomena. The measured I-t characteristics are related with charging/discharging and dielectric relaxation phenomena. A counter-clockwise HF C-V hysteresis, larger than 2 V at thickness of the stack structure of about 50 nm was observed.Metal-insulator-semiconductor field effect transistors (MISFETs) using ZrO₂/ZrSi_xO_y/SiO_x-gate insulator were studied. P-channel MISFETs with aluminum gate electrode were fabricated on standard n-type silicon substrates. Due to charging/discharging phenomena in the gate dielectric the transistors can be switched between On- and Off-state with the polarity of applied stress voltage.     

Study of an AlSi3N4 interface by photoinjection measurements in MNS and MNOS sandwiches

From photoinjection measurements of an Al/Si₃N₄/SiO₂/Si structure, a mechanism is proposed for the charging process of the traps situated in the insulator close to the metallic emitter electrode. A decomposition of the evolution of the barrier in two steps, increase in the barrier height and drift of the position of the barrier maximum, is shown and correlated with spatial depth of filling of the traps in the insulator. A method is deduced for determining the zero field barrier height of the AlSi₃N₄ interface when a trapped space charge prevents the use of the conventional method, and a value for the scattering mean free path of electrons in Si₃N₄ is obtained.     

Non-volatile memory properties of metal/SrTiO3/SiO2/Si structures

Non-volatile MIOS-type semiconductor memory elements were fabricated on silicon using electron-beam-evaporated SrTiO₃ as the second insulator. The charge storage properties were characterized for Au/SrTiO₃/SiO₂/Si structures. Our results show that a short-time post-deposition oxygen annealing is essential to anneal out the radiation damage resulting from electron beam deposition. The devices on n-type silicon substrates show fast switching for a positive applied pulse and a much lower switching speed (longer than 20 ms) for a negative pulse, which is believed to be caused by the minority carrier restriction. The devices show a logarithmic decay of the flat-band voltage as a function of time, with a rate of 0.4 V decade^-1 for stored electrons and 0.5 V decade^-1 for stored holes. The devices can survive 10⁴ write-erase cycles of endurance testing. An inversion of the surface silicon layer is found for devices on p-type substrates subjected to high temperature oxygen annealing.     

The conduction process in pyrolytically deposited SiO2 films

The I-V and I-T characteristics of pyrolytic SiO₂ films are studied within the framework of the theory of dielectric relaxation. The exhaustion of donor centres by the Poole-Frenkel effect gives rise to the formation of a depletion region near the cathode-insulator interface. Thus the electric field in the insulator is modified until a steady state is reached. The energy level and density of the Poole-Frenkel centres are determined and a steady state Schottky current is shown to be dominant above 400 K.