IoT scheduling for higher throughput and lower transmission power

Wireless Networks - The massive increase in the Internet of Things (IoT) has brought a diverse long-range, low-power, and low bit-rate wireless network technologies. The LoRa a low-power wide area...     

A novel trench-injector power device with low ON resistance andhigh switching speed

A power MOSFET device structure that has been developed to optimize the tradeoff between ON resistance and switching speed is discussed. The device structure features a trench injector that injects a controlled quantity of minority carriers into the drift path of the MOSFET current to modulate the conductivity of the device during the ON state. The conductivity-modulated MOSFET device (CMDMOS) has been fabricated and characterized. The device structure has demonstrated low ON resistance and high switching speed. It can be implemented along with logic circuitry to allow programmable electrical control of the switching-speed/ON-resistance tradeoff     

Fabrication and electrical characterization of phase-change memory devices with nanoscale self-heating-channel structures

We proposed a material composition and an optimized patterning process for the phase-change memory devices with a nanoscale self-heating channel (NSC) structures. As a suitable composition, Ge₁₈Sb₃₉Te₄₃ was employed, which is the 22% Sb-excessive phase compared with the conventional Ge₂Sb₂Te₅. For fabricating the NSC memory devices, Ge₁₈Sb₃₉Te₄₃ layer was patterned into a thin channel having enlarged pad areas at both sides end by the developed two-step dry etching technique using a TiN hard mask. The NSC memory devices showed such good behaviors as lower power operations without any degradation of switching speed and better endurance for cyclic rewritings even in the scaling regime of tens-of-nanometer size. It can be concluded from the obtained results that the proposed NSC memory devices promise the feasibility for realizing both aggressive scaling with a simpler process and enhanced memory performances for the phase-change nonvolatile memory applications.     

LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM

Packet classification is an important method implemented in modern network processors used in embedded systems such as routers. Current software-based packet classification techniques exhibit low performance, prompting researchers to move their focus to architectures encompassing both software and hardware components. Some of the newer hardware architectures exclusively utilize Ternary Content Addressable Memory (TCAM) to improve the performance of rule matching. However, this results in systems with high power consumption. In this paper, we propose LOP, a novel SRAM-based architecture where incoming packets are compared against parts of all rules simultaneously until a single matching rule is found for the compared bits in the packets. LOP significantly reduces power consumption as only a segment of the memory is compared against the incoming packet. Despite the additional time penalty to match a single packet, parallel comparison of multiple packets can improve throughput beyond that of the TCAM approaches, while consuming significantly less power. Compared with a state-of-the-art TCAM implementation (throughput of 495 Million Search per Second (Msps)) in 65 nm CMOS technology, on average, LOP saves 43% of energy consumption with a throughput of 590 Msps. In addition, an analysis of how the area scales is provided.     

Modeling of data retention statistics of phase-change memory with confined- and mushroom-type cells

Data retention statistics of phase-change memory with two representative cell schemes, confined and mushroom cells, were investigated using phase-field method that can correctly model successive nucleation events and their growth, simultaneously. Several directions of cell structure engineering are suggested. An interesting point is that reducing only one lateral dimension below a characteristic length can improve the data retention. Most importantly, it was found that the cumulative distribution of the retention time is Weibull for the mushroom cells while that is lognormal for the confined cells.     

从电压较高的电源获取较低直流电压的电路

如果使用图1中的电路,那么您不用求助于电噪声很大的DC/DC转换器,也不必在降压电阻器中浪费功率,就能从电压较高并经整流的正弦电压源获得5VDC等很低的稳定电压。该应用需要一个稳定的5VDC源,但是变压器向全波桥式整流器供应18Vrms。在充电阶段,两个等值电解电容器C1和C2在通过     

Characterisation of a new hump-free device structure for smart power and embedded memory technologies

A new device structure suitable for smart power and embedded memory technologies is presented that provides ideal hump-free subthreshold behaviour for shallow trench isolations by locally thickening the gate dielectric. This device structure is compared with an alternative approach to remove the hump effect, an improved process that reduces the oxide recess of the isolating trench. The new device offers a superior subthreshold slope. Emphasis has been placed not only on the hump effect but also on the reliability characterisation. The gate integrity of the new structure is comparable and only a minor degradation of the hot-carrier lifetime is observed. The new device structure provides an easy way to remove the hump without any change in the process and is applicable to every technology that offers more than one gate dielectric.     

具有更高激光功率的新型加工支持系统

在加工制造业，从焊接、切割到粉末金属喷镀，对激光功率的要求正推动二氧化碳激光器机械加工系统向更高的功率水平发展。随着激光光源技术的进步，对有效利用激光功率的要求使机械加工设备支持系统得以同步发展。这些支持系统包括机械运动控制系统、高压辅助气体传递控制系统和高流速切割喷嘴技术等。     

Fe-doped InP semi-insulating buried heterostructure for high speed and high power operations in directly modulated semiconductor laser

A buried heterostructure based on Fe-doped InP semi-insulating layers is optimised for both high output power and large modulation bandwidth operations up to 70/spl deg/C in a 10 Gbit/s directly modulated 1.3 /spl mu/m InGaAsP/InP distributed feedback laser. The slope efficiency of 0.19 W/A and -3 dB bandwidth of 10 GHz at 1.5 times threshold current is demonstrated experimentally.     

0.35-μm asymmetric and symmetric LDD device comparison using areliability/speed/power methodology

The reliability and performance of NMOSFET asymmetric LDD devices (with no LDD on the source side) are compared with that of conventional LDD devices. The results show that asymmetric LDD devices exhibit higher I_dsat and larger I_sub TO maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V_dd. For the same hot-carrier lifetime, we show that ring oscillators with asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power     

一种适用于低压高速嵌入式应用的2T P沟道纳米晶存储器件

本文基于嵌入式应用的低压、高速要求,提出了一种基于2T结构的P沟道纳米晶存储新型结构。该器件采用带带隧穿激发热电子注入(BTBTIHE)的编程方式,可以同时实现高速、低功耗编程。同时采用2T结构以简化外围高压和读出电路。该器件具有良好的存储特性,包括高编程速度（5us编程脉冲下获得1.1V窗口）和优异的数据保持特性（在10年的保持时间电荷损失仅为20%）。该器件在嵌入式非挥发存储领域具有很强的应用潜力。     

复合埋层上的薄层SOI-LDMOS功率器件

为了提高SOI-LDMOS功率器件击穿电压及相关性能,针对薄层SOI-LDMOS功率器件提出了一种新结构,在新结构中引入了复合埋层,它由p埋层与Si3N4绝缘介质埋层构成。复合埋层不仅改善了比导通电阻与耐压的关系,而且还缓解了自热效应。仿真结果表明,在漂移区长度为57 m时,新结构耐压达到了1052 V,与CamSemiSOI相当,而比导通电阻与表面最高温度分别比CamSemi SOI降低了233.05.mm2和64 K。     

高速低功耗深度报文检测方法

针对基于三态内容寻址存储器(TCAM,ternary content addressable memory)的深度报文检测(DPI,deep packet inspection)存在的高功耗问题,提出一种分级DPI方法BF-TCAM。第一级采用低功耗的并行布鲁姆过滤器(bloom fliter)排除无需检测的正常报文;第二级采用TCAM对真正需要检测的攻击报文和第一级的假阳性误判报文做进一步的检测。由于网络流量中大部分报文是正常报文,攻击报文在其中只占很少的部分,布鲁姆过滤器的假阴性(false negative)概率为0,可以保证不会产生漏检,假阳性概率很低,可以保证高速DPI检测的同时大大地降低功耗。     

High speed and high density static induction transistor memory

Describes a high speed and high density dynamic RAM utilizing a static induction transistor (SIT) structure. The main conduction mechanism of an SIT is carrier injection control due to the potential hump at the intrinsic gate, where the potential hump is capacitively controlled by the gate and the drain voltage in a basic operation. The SIT forms a dynamic RAM memory cell if one of the drain and the source regions is set as a floating region directly connected to the storage capacitor. Basic operation of a single SIT memory cell is experimentally demonstrated in this paper.     

功率VDMOS器件设计及研制

分析了VDMOS器件击穿电压、导通电阻、阈值电压和开关特性等主要性能指标的影响因素,并借助半导体模拟仿真软件Sentaurus对VDMOS器件进行建模,调整器件各个结构参数,提出采用P体区间厚氧化层方法提高器件的动态特性,获得满足设计目标要求的器件电性能参数,最终形成器件设计版图,并依此在现有生产线上进行工艺流片,根据流片结果进一步优化调整设计参数,最终获得一款击穿电压400 V、导通电阻0.45?、阈值电压2.5 V、开关特性较好的功率VDMOS器件。     

可编程电源管理器件及其应用

在现代电子设备中往往需要使用不同的电源,Lattice公司提供了经过优化的对于现在的多电源系统很重要的电源管理功能和独特的可编程控制方案。介绍了可编程电源管理器件isp PAC-POWR1208的特点及其应用。