可编程逻辑PLD和CPU组构W-CDMA mOdem

绪论 从用户数量和将要支持的服务种类来看,社会对先进的信息服务的要求正在与日俱增.在这个社会里,高速Internet接入被认为是理所当然的,语声和低速率数据业务不足以满足用户的要求.支持大量开支带宽的多媒体业务的需求,是用户向蜂窝系统和网络提出的新的挑战.因此,在被称IMT-2000的动议的推动下,国际电信联盟(ITU)提出了几个能够满足这些要求的标准.     

Architecture and design of NX-2700: a programmable single-chip HDTVall-format-decode-and-display processor

This paper describes the architecture, functionality, and design of NX-2700, a digital television and media processor chip from Philips Semiconductors. The NX-2700 is the second generation of an architectural family of programmable multimedia processors targeted at the digital television (DTV) markets, including the United States Advanced Television Systems Committee (ATSC) DTV-standard-based applications. The chip not only supports all of the 18 ATSC formats from standard-definition to wide-angle, high-definition video, but has also the power to handle high-definition television (HDTV) video and audio source decoding (high-level MPEG-5 AC-3 and ProLogic audio, closed captioning, etc.) as well as the flexibility to process advanced interactive services. NX-2700 is a programmable processor with a very powerful, general-purpose very long instruction word (VLIW) central processing unit (CPU) core that implements many nontrivial multimedia algorithms, coordinates all on-chip activities, and runs a small real-time operating system. The CPU core, aided by an array of peripheral devices (multimedia coprocessors and input-output units) and high-performance buses, facilitates concurrent processing of audio, video, graphics, and communication-data     

A reconfigurable analog processor using coarse-grained,heterogeneous configurable analog blocks for field programmable mixed-signal processing

A field programmable analog array (FPAA), designed for a reconfigurable analog processor, introduces coarse-grained, heterogeneous configurable analog blocks that improves performance and power consumption. Designed in an SMIC standard 0.18 μm CMOS process, mixed-signal processing can be performed by the assistance of an on-chip MCU and configurable digital blocks. Relative precision of the analog processing is 99.5%. A PID controller is shown as an application example. With a total die area of 11 mm², the maximum power consumption is 17.6 mA with a 3.3 V supply voltage, resulting in a 17× improvement in energy-efficiency over current conventional FPAAs.     

A single-chip MPEG-2 codec based on customizable media embedded processor

A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm/sup 2/ die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.     

A configurable convolution chip with programmable coefficients

Describes the architecture and implementation of a bit-level configurable convolver array. The systolic field supports a configuration during operation in terms of number of taps and coefficient word length. A chip has been designed in 1.5- mu m CMOS using a full-custom design style which contains 112586 transistors on an active area of 46 mm/sup 2/. The configurability consumes only 9% of that area. The prototypes are shown to be fully functional up to 20 MHz. An extension of the architecture for optimized calculation of transformations is also presented.<>     

A CCD programmable signal processor

A generic large-coupled device (CCD) signal processor that performs 2.8-billion computations per second with a 10-MHz clock rate is described. The device's concept, design, operation, performance, and applications are reviewed. A dynamic range greater than 42 dB has been demonstrated by the device. This processor can be used as a one-dimensional correlator, a two-dimensional matched filter or a two-layer neural net device. The device demonstrates the flexibility and computational power that is possible using CCD technology     

A configurable multimedia middleware platform

Experience demonstrates the benefits and feasibility of supporting multimedia applications in distributed middleware architectures. However, deployment of multimedia-capable middleware platforms has not yet occurred on a large scale. This article describes designing such a platform and its attempts to maximize performance, predictability, and configurability in a standard workstation operating system environment     

一种新的基于可配置处理器的异构多核线程级动态调度模型

本文针对基于可配置处理器的异构多核结构,提出一种新的线程级动态调度模型。此类异构多核系统中每个核分别针对某一应用做指令集扩展,调度器通过线程、处理器核以及指令集间的映射关系,动态调度线程至适合的处理器核,从而在没有大幅增加芯片面积的前提下,达到与每个核都具有全扩展指令集相近似的加速比,此外该模型还可以有效减少编程模型的复杂度。     

A single-chip 80-bit floating point processor

A single-chip 80-bit floating point VLSI processor capable of performing 5.6 million floating point operations per second has been realized using 1.2-/spl mu/m n-well CMOS technology. The processor handles 80-bit double-extended floating point data conforming to IEEE standard 754. The chip has 128 microinstructions which are stored in an on-chip ROM. By programming microinstruction sequences in an external control storage, not only basic arithmetic operation but also special arithmetic functions can be performed. A composite design method supported by a hierarchical design automation system was used to quickly lay out 50K gates including a 64-/spl times/64-bit multiplier and 15 kb of memory on a chip with a die size of 10/spl times/10 mm/SUP 2/. Only 11 man-months were required for the effort.     

Simulation of a programmable signal processor

Although simulation, in general, is a very widely used technique, simulation of a complex processor as a tool for v microprogram development is only of recent origin. A signal processor has, quite often, special features like multiple storage and computational modules functioning in parallel, real-time devices, etc. The problems connected with simulating these features are discussed here in the context of a specific architecture. An interactive debugger, incorporated as a special feature of the simulator is also presented, which is an invaluable aid in microprogram debugging.     

A fuzzy logic inference processor

A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 μm CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 μs     

小型可编程数字信号处理机

本文介绍的一种实时处理的可编程数字信号处理机是采用正交双通道处理,用一组高阶复数FIR滤波器和高阶实数FIR滤波器实现滤波,信噪比和地杂波抑制得到改善,并具有三种恒虚警处理手段。全机由微程序控制。     

A single-chip digital signal processor for telecommunication applications

A single-chip, software-programmable digital signal processor, intended for telecommunication applications, has been developed. The processor, fabricated with the most advanced 3 /spl mu/m n-channel E/D MOS technology, incorporates a 16/spl times/16-bit full hardware multiplier and a sophisticated bus structure to minimize bus conflicts, thus attaining the capability to implement 55 second-order filters at a sampling rate of 8 kHz with sufficient dynamic range to process PCM encoded signals. The authors describe the design concept, architecture, instructions, device design, and application techniques.     

A programmable focal-plane MIMD image processor chip

An 80×78 pixels vision chip for focal-plane image processing is presented. The chip employs a Multiple-Instruction-Multiple-Data (MIMD) architecture to provide five spatially processed images in parallel. The size, configuration, and coefficients of the spatial kernels are programmable. The chip's architecture allows the photoreceptor cells to be small and parked densely by performing all computations on the read-out, away from the array. The processing core uses digitally programmed current-mode analog computation. Operating at 9.6 K frames/s in 800-lux ambient light, the chip consumes 4 mW from a 2.5-V power supply. Performing 11×11 spatial convolutions, an equivalent computation (5.5 bit scale-accumulate) rate of 12.4 GOPS/mW is achieved using 22 mm² in a 1.2-μm CMOS process. The application of the chip to line-segment orientation detection is also presented     

COBRA: a 100-MOPS single-chip programmable and expandable FFT

This paper presents an optimized column fast Fourier transform (FFT) architecture, which utilizes bit-serial arithmetic and dynamic reconfiguration to achieve a complete overlap between computation and communication. As a result, for a clock rate of 40 MHz, the system can compute a 24-b precision 1K point complex FFT transform in 9.2 μs, far surpassing the performance of any existing FFT systems     

A CCD programmable image processor and its neural networkapplications

A charge coupled device (CCD)-based image processor that performs 2D filtering of a gray-level image with 20 programmable 8-b 7×7 spatial filters is described. The processor consists of an analog input buffer, 49 multipliers, and 49 8-b 20-stage local memories in a 29-mm ² chip area. Better than 99.999% charge transfer efficiency and greater than 42-dB dynamic range have been achieved by the processor, which performs one billion arithmetic operations per second and dissipates less than 1 W when clocked at 10 MHz. The device is also suited for neural networks with local connections and replicated weights. Implementation of a specific neural network, the neocognitron, based on this CCD processor has been simulated. The effect of weight quantization imposed by use of this CCD device on the performance of the neocognitron is presented     

运用可配置处理器内核的设计

虽然专用集成电路(ASIC)设计者不希望从零开始开发整个系统的每一个部分,但是他们必须确信整个系统和每个部分都按专用特性工作,即使第三方供应商可能提供系统的部件.目前,嵌入式系统是由几组工程师去设计的,因而出现硬件和软件分别开发的倾向,导致最终产品的工作特性偏离原来的指标.根据这种情况,使用第三方的知识产权(IP)只会增加多头开发和延长上市时间的可能性.     

基于VLSI平台的AVR处理器仿真与设计

传统的微处理器由于内部有限的逻辑资源和外部固定的引脚封装，大大限制了应用范围。为此，在阐述微控制器的内部结构、存储器管理结构和指令集结构后，利用现场可编程门阵列丰富的逻辑资源，虚拟出传统微控制器的处理器核心，添加Wishbone总线，将处理器核心与通用外设连接构成一个虚拟的微控制器平台，并使用硬件描述语言Verilog和VHDL，自底向上设计AVR处理器核心，与通用外设互连组成系统，使用XILINX Virtex?Ⅱ Pro芯片进行板级验证。结果表明，实现了既定目标，与标准的微控制器兼容，系统运行稳定。该方法延续了传统微控制器的生命力，能使其得到更大发展。