An integrated high resolution CMOS timing generator based on anarray of delay locked loops

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with subgate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted. The clock alignment function is obtained by selecting one of the timing generator signals as an output clock. The proposed timing generator has been mapped into a 1.0 μm CMOS process and an r.m.s. error of the time taps of 48 ps has been measured with a bin size of 0.15 ns. Used as a TDC device, an r.m.s. error of 76 ps has been obtained, A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives     

The delay vernier pattern generation technique

The authors describe a new technique for generating an arbitrary digital data stream with very fine timing resolution. Note that this timing resolution specifies the output edge placement precision, not the bit rate. The resolution is determined by the difference between two propagation delays rather than by an absolute delay. Because this difference can be made very small, the circuit, called the delay vernier generator, can achieve unprecedented timing resolution in a particular circuit technology. Also, this very precise timing is obtained without requiring an extremely high speed clock. The generator architecture includes delay-locked loop calibration mechanisms to compensate for process and temperature variations. A prototype chip was fabricated in a 1.2-μm CMOS technology, and measurements confirmed that resolutions as fine as 100 ps can be achieved reliably     

A low-power direct digital synthesizer using a self-adjustingphase-interpolation technique

A complete direct digital synthesizer (DDS) using a self-adjusting phase-interpolation technique is fabricated using 0.35-μm CMOS process technology. A self-adjusting delay generator reduces the periodic jitter in the most significant bit (MSB) of the accumulator in this DDS. To improve the spectral performance, a method of spurious signal reduction that uses offset current sources (OCSs) is newly adopted in the delay generator. Test results confirm that the delay generator produces highly accurate delay timing without the need to adjust circuit constants. The measured spurious free dynamic range (SFDR) is 62 dBc for a dc to 10-MHz output and the power consumption of the complete DDS is 39.2 mW at a 100-MHz clock rate     

Delay Test Generation: A Hardware Perspective

An important problem one faces during design of a built-in self-test(BIST) based delay test is the selection of a proper generator toapply the test vectors. This problem is due to the need of applyinga pair of patterns to detect any given delay fault. The secondvector has to be launched against the logic immediately following thefirst vector. This timing requirement places severe restrictions onthe kind of hardware suitable for the task, especially in built-inself-test applications where the generator must reside on chip.This paper studies the various options one has in designing the delay test vector generator. Both scan and non-scan designs are addressed. Thedifferent options are measured based on their performance, cost, and flexibility.     

视频时序信号发生器的实现方法

阐述了一种新型视频时序信号发生器的实现方法,并提供了详细的设计结构图.通过软件配置不同的时序描述指令,该发生器中的指令解码器和指令跳转器将时序描述指令解码,产生相应的连续时序信号,包括小尺寸和超大尺寸显示设备的时序信号,以及不规则分辨率的时序信号.视频时序信号发生器可以输出多标准的视频格式,满足各种视频显示格式的要求.     

一种嵌入式SIMD协处理器地址产生器的设计

文章介绍了一种新的嵌入式SIMD协处理器地址产生器.该地址产生器主要完成地址计算和协处理器指令的场抽取功能.为了提高协处理器的性能,地址产生器中设计了新的传送路径.该传送路径能够不通过地址产生器中的ALU而把数据送入寄存器中,这个传送路径能够减少ldN指令的一个延迟周期.在SMIC0.18微米标准库单元下,该地址产生器的延迟能够满足周期为10ns的协处理器.     

A New Timing-Driven Placement Algorithm Based on Table-Lookup Delay Model

An algorithm is presented for obtaining placements of cell-based very large scale integrated circuits, subject to timing constraints based on table-lookup model. A new timing delay model based on some delay tables of fabricators is first simplified and deduced; then it is formulated as a constrained programming problem using the new timing delay model. The approach combines the well-known quadratic placement with bottom-up clustering, as well as the slicing partitioning strategy, which has been tested on a set of sample circuits from industry and the results obtained show that it is very promising.     

Limited-Shift-Full-Rank Matrices With Applications in Asynchronous Cooperative Communications

Shift-full-rank (SFR) matrices are matrices that have full row rank no matter how their rows are shifted. SFR matrices have been used lately as generator matrices for a family of space-time trellis codes to achieve full diversity in asynchronous cooperative communications, where the numbers of columns of the SFR matrices correspond to the memory sizes of the trellis codes. A systematic construction of SFR matrices, including the shortest (square) SFR (SSFR) matrices, has been also previously proposed. In this paper, we study a variation of SFR matrices with a relaxed condition: limited-shift-full-rank (LT-SFR) matrices, i.e., the matrices that have full row rank no matter how their rows are shifted as long as the shifts are within some range called delay tolerance. As the generator matrices for the previously proposed space-time trellis codes, LT-SFR matrices can guarantee asynchronous full diversity of the corresponding codes when the timing errors are within the delay tolerance. Therefore, due to the relaxed condition imposed on LT-SFR matrices, more eligible generator matrices than SFR matrices become available.     

亚阈值电路单元延时波动统计建模方法

集成电路产业的不断发展以及行业对高能效的不断追求使得工艺尺寸不断缩小，越来越多的电路工作在亚阈值区，工艺参数波动导致电路延时呈现非高斯分布。统计静态时序分析作为先进工艺下用于分析时序的新手段，采用将工艺参数和延时用随机变量表示的方法，可以加速时序收敛，显示预期成品率。文章主要研究了亚阈值电路单元延时波动的统计建模方法。分别对单时序弧和多时序弧的蒙特卡洛金标准数据进行建模研究。提出了单时序弧单元延时的分布拟合统计建模方法，其误差小于6.30%。提出了多时序弧单元延时人工神经网络统计建模方法，其误差小于4.95%。     

A New Timing-Driven Placement Algorithm Based on Table-Lookup Delay Model

There have been extensive studies on timing-driven placement in recent years.Theapproaches toward this problem fall into two main categories:net-based and path-based.In a typical net-based one,potential critical paths and acceptable d...     

A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement

This paper presents a Built-In Self-Test (BIST) technique to test the setup and hold times of memory interface circuitry. The BIST scheme generates data and clock using an on-chip pattern generator. The relative timing difference between data and clock is controlled using a cycle-by-cycle control method for testing. Two test methods of static and dynamic modes have been presented to measure the timing difference and then are used to specify the setup and hold times. The static mode is mainly used to detect pass or fail for timing specifications, and the dynamic mode is devised to measure the amount of timing mismatches and thus detect timing margin degradations due to the timing delay mismatches. Using these two test modes, the BIST scheme obtains test results with low frequency signals, which are compatible with low performance testers. The test chip including the BIST scheme has been fabricated with a commercial 0.18-μm CMOS process. The chip measurement results are shown to validate the testability of the BIST scheme for the setup and hold times of memory devices.     

基于人文关怀的信号配时方法研究

在传统的信号配时中，都是以减少车辆的总延误为目标，这样并不能很好地体现出整个社会中人的时间价值。现以减少所有通过交叉口的出行者的总延误为目标，在传统的信号配时方案的基础上，提出了一套新的配时方案，同时以减少全部出行者的总延误时间为目标给出了相应的延误评价公式，最后以杭州市文一路-古翠路口的实测交通数据进行分析，论证了本配时方案的有效性。     

A versatile 3.3/2.5/1.8-V CMOS I/O driver built in a 0.2-μm,3.5-nm Tox, 1.8-V CMOS technology

This I/O driver supports 3.3/2.5/1.8-V interfaces in a 3.5-nm Tox, 1.8-V CMOS technology. A bias generator, its switch capacitors, and a level shifter with protection network guarantee reliability and improve noise rejection. Measured output timing degradation is 2.5 ps per I/O switching. Buried resistors limit variation in output impedance. Interface delay of 2 ns with worst case I/O switching allows 400-MHz operation     

A portable clock multiplier generator using digital CMOS standardcells

High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 μm CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps     

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM

An ultrahigh-speed 4.5-Mb CMOS SRAM with 1.8-ns clock-access time, 1.8-ns cycle time, and 9.84-μm² memory cells has been developed using 0.25-μm CMOS technology. Three key circuit techniques for achieving this high speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array. The proposed decoder can reduce the delay time between the address input and the word-line signal of the 4.5-Mb SRAM to 68% of that of an SRAM with conventional circuits. The sense amplifier with nMOS source followers can reduce not only the delay time of the sense amplifier but also the power dissipation. In the SRAM, the sense-amplifier activation pulse must be input into the sense amplifier after the signal from the memory cell is input into the sense amplifier. A large timing margin required between these signals results in a large access time in the conventional SRAM. The sense-amplifier activation pulse generator that uses a duplicate memory-cell array can reduce the required timing margin to less than half of the conventional margin. These three techniques are especially useful for realizing ultrahigh-speed SRAM's, which will be used as on-chip or off-chip cache memories in processor systems     

汉明距离发生器实现方案的研究

汉明距离是用来衡量2个二进制码字之间的相似程度的,本文主要针对用FPGA实现的汉明距离发生器,详细研究了其关键部件累加器的几种实现方案,给出了波形仿直结果时延及战胜FPGA资料的统计结果,提出了一种能大在缩短电路时延、提高运算速度并节省资源的实现方案,最终用FPGA实现并应用于一种卫星通信的帧同步系统中。     

IC测试系统精密定时器的新结构

讨论了一种适合于VLSI的精密定时子系统的新结构.该结构将定时计数器分为高速和低速两部分,低速部分采用存储器代替分散的寄存器,既有利于集成,又降低了系统的成本.同时,新的精密定时子系统还解决了定时中不完整周期的问题.     

支持像移补偿功能面阵CCD相机驱动电路系统

为了设计一种支持电子式像移补偿功能的高帧频大面阵CCD驱动电路,满足像移补偿功能.论文首先给出了大面阵CCDFTF5066M的基本驱动电路,然后在其基础上通过增加一个像移补偿时序发生器与主时序发生器SAA8103配合工作来实现电子像移补偿,给出了像移补偿发生器内部设计结构,所增加的像移补偿时序发生器只用于产生曝光期间所需的几个垂直转移驱动时序和转发SAA8103 产生的时序信号.选择了FPGA作为像移补偿时序发生器,并且进行了时序仿真.最后对设计的驱动电路进行了室内像移补偿实验验证,取得了很好的补偿效果,该驱动电路系统支持最大帧频可达2.7 F/s,信噪比达到了66 dB.该驱动电路能方便地选择输出通道数量和输出方式,使相机适用于不同的场合.     

Modeling Packet Delay in Multiplexed Video Traffic

In this paper a Markov chain based characterization of a single video source is used to model multiplexed video traffic and the resulting packet delay. The multiplexed video stream of statistically identical sources is represented using a reduced order approximation of the superposed Markov generator matrix. It is shown that inadequate spectral content in the single source generator matrix is manifested as an underestimate of the packet delay probabilities for the multiplexed stream. A new method for simplifying the generator matrix for the multiplexed video stream that amply models its spectral content is given. The simulated and calculated results using the aforementioned model are shown be in good agreement.     

一种高效的FFT处理器地址快速生成方法

地址产生器是FFT处理器的主要组成部分,地址快速生成和旋转因子读取次数是它的两个重要指标,但很少有算法能够将其统一起来。本文采取了一种新的操作数地址生成顺序并构造了一种新的FFT循环级数表示方法,基于操作数地址的位倒序方式,提出了一种兼有地址简单快速生成与避免重复读取旋转因子特点的可变长地址生成方法,解决了以往地址产生时生成速度与旋转因子重复读取之间的矛盾,实现了快速和降低系统功耗的统一。