一种900-MHz 20-mW CMOS功率放大器的设计

提出了一个工作电压为3V，工作频率900MHZ，输出功率为20mW的高效率CMOS功率放大器。为了达到设计目标，文章采用了一些特殊的方法，包括三级放大结构，级间的调谐匹配和层叠差分结构。     

A 52?pJ/bit 433-MHz low power OOK transmitter

An OOK transmitter in 433-MHz ISM band employing a speed-up circuit is described. The proposed speed-up circuit accelerates the start-up of the oscillator and buffer by briefly increasing the bias currents during transmission of bit “1”. This leads to a data rate increase from 3 to 10-Mb/s without any penalty on power consumption. The data rate can also be made adaptable by varying the duration in which the bias current is increased. The proposed OOK transmitter is implemented in 0.35-μm CMOS technology. The measured results show that the transmitter achieves a maximum data rate of 10-Mb/s with a dc power consumption of 518 μW from a 1-V power supply, yielding an energy efficiency of 52 pJ/bit or 0.97 nJ/bit/mW when normalized to the output power. This paper also derives a closed form equation which describes the transient behavior of Colpitts oscillator during start up.     

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (G _m -C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the modulator. Implemented in a MOSIS HP 0.5-m CMOS technology, the chip area is 857 m × 420 m, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.     

一种0.2-mV 20-MHz 600-μW比较器

提出了一种低功耗中速高精度比较器。比较器采用3级前置放大器加锁存器的多级结构,应用失调校准技术,用于一个电压2.5 V、速度1 MS/s、精度12位的逐次逼近型A/D转换器。该比较器采用UMC 0.18μm混合模式3.3 V CMOS工艺设计制造。仿真结果表明,在2.5 V电压下,速度可以达到20 MHz,准确比较0.2 mV电压,并能有效校准20 mV输入失调,功耗仅为600μW,版图面积为620μm×190μm。     

A 18-mW,20-MHz bandwidth,12-bit continuous-time∑△modulator using a power-efficient multi-stage amplifier

正A fourth-order continuous-time sigma delta modulator with 20-MHz bandwidth,implemented in 130nm CMOS technology is presented.The modulator is comprised of an active-RC operational-amplifier based loop filter,a 4-bit internal quantizer and three current steering feedback DACs.A three-stage amplifier with low power is designed to satisfy the requirement of high dc gain and high gain-bandwidth product of the loop filter.Non-return-to -zero DAC pulse shaping is utilized to reduce clock jitter sensitivity.A special layout technique guarantees that the main feedback DAC reaches 12-bit match accuracy,avoiding the use of a dynamic element matching algorithm to induce excess loop delay.The experimental results demonstrate a 64.6-dB peak signal-to-noise ratio,and 66-dB dynamic range over a 20-MHz signal bandwidth when clocked at 480 MHz with 18-mW power consumption from a 1.2-V supply.     

一种电流复用共栅低噪声放大器的低功耗433/915-MHz射频前端的设计

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.