High-frequency noise of the junction field-effect transistor

Based on Geurst's treatment of the high-frequency value of the admittances of the junction field-effect transistor, the high-frequency noise of the device has been computed, assuming that the noise source is of thermal origin. By applying an appropriate series expansion of the current it is possible to express the noise of the drain and gate current in terms of known quantities, as steady-state transconductance, gate capacitance, and frequency. At low frequencies the noise spectrum of the drain current is independent of the frequency and is much larger than the noise of the gate current; however, at high frequencies the noise spectra of the gate and drain current both vary by ω²and are of the same order of magnitude.     

Ambipolar field-effect transistor

The results of measurements performed on an amorphous-silicon thin-film transistor structure are presented and interpreted. The device characteristics show a continuous alternation between n-channel and p-channel operation, an “ambipolar” effect that is made possible by the provision of ohmic source and drain contacts.     

Vacuum-insulated-gate field-effect transistor

A vacuum-insulated-gate field-effect transistor (VIGFET) is fabricated using a modified polysilicon-gate MOS process. The vacuum insulation is formed by first selectively etching the initial SiO/sub 2/ layer under the polysilicon gate in HF and then depositing LPCVD SiO/sub 2/ (LTO) to seal the evacuated cavity under the gate. Initial measurements of n-channel FET drain characteristics result in an effective value for the channel-electron mobility*gate capacitance product of k'= mu /sub n/C'=21 mu A V/sup -2/, comparable to that of conventional MOSFETs.<>     

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.     

Influence of low-field-mobility-related issues on SiC metal-semiconductor field-effect transistor performance

High field-dependent electron transport characteristics in 4H-SiC were measured successfully using a nanosecond-pulsed technique. It should be noted that the velocity-field characteristics of SiC are different from GaAs in that SiC does not have velocity overshooting behavior. Without the overshooting behavior, the current density of SiC metal-semiconductor field-effect transistors (MESFETs) is restricted fundamentally by the low drift velocity in the low-field, parasitic regions. These parasitic regions not only limit the current density but also are responsible for a significant shift of the threshold voltage.     

High performance of induced-channel heterojunction field-effect transistor (HFET)

AlGaAs/GaAs high-performance, minority-carrier, induced-channel, heterojunction field-effect transistors (HFETs) fabricated on semi-insulating GaAs using molecular beam epitaxy (MBE) are reported. A 0.6 mu m self-aligned gate HFET exhibited a room-temperature transconductance of 540 mS/mm with a cutoff frequency of 25 GHz.<>     

A vertical-junction field-effect transistor

A vertical JFET structure is described which allows realization of submicrometer channel-length devices using standard photolithographic techniques. The fabrication procedure utilizes an anisotropic etch followed by an impurity diffusion or implantation to define the channel. A numerical simulation of the JFET operation is implemented using a finite-element analysis technique. Typical devices exhibit high-output conductance and a tendency to resist channel pinchoff at the drain end. Etched bipolar transistors having current gains as high as 400 can also be formed concurrently with the fabrication of the vertical JFET structures.     

V-shaped notched-channel field-effect transistor

A junction field-effect transistor with a V-shaped notched channel fabricated by preferential etching of (100) silicon is described. This transistor exhibits a higher maximum transconductance and a lower turn-on resistance than conventional silicon f.e.t.s. with rectangular channels. The fabrication, characteristics and possible applications of this device are described.     

Vertical tunnel field-effect transistor

The realization of a novel vertically grown tunnel field-effect transistor (FET) with several interesting properties is presented. The operation of the device is shown by means of both experimental results as well as two-dimensional computer simulations. This device consists of a MBE-grown, vertical p-i-n structure. A vertical gate controls the band-to-band tunneling width, and hence the tunneling current. Both n-channel and p-channel current behavior is observed. A perfect saturation in drain current-voltage (I/sub D/--V/sub DS/) characteristics in the reverse-biased condition for n-channel, an exponential and nearly temperature independent drain current-gate voltage (I/sub D/--V/sub GS/) relation for both subthreshold, as well as on-region, and source-drain off-currents several orders of magnitude lower then the conventional MOSFET are achieved. In the forward-biased condition, the device shows normal p-i-n diode characteristics.     

Dipole heterostructure field-effect transistor

It is proposed to reduce the gate current by using a dipole created by two doped planes, n⁺⁺ and p⁺⁺, in charge control layer, dipole heterostructure field-effect transistors (dipole HFETs) fabricated in AlGaAs/GaAs use doped p⁺⁺ and n ⁺⁺ planes in the charge control AlGaAs layer to form a dipole that provides a considerably larger barrier between the channel and the gate than that in conventional heterostructure FETs. This leads to a reduction of the forward-biased gate current in enhancement-mode n-channel devices, by a factor of approximately 9 at 1.2 V in the experimental devices, when compared with equivalent conventional HFETs. A much broader transconductance region, in the range of 0.5-2.5-V gate bias, a higher maximum drain current, and no negative transconductance are also observed. A comparison between the gate current-voltage characteristics of conventional and dipole HFETs for 1-μm-long and 10-μm-wide gate devices is given. The measured results clearly indicate that a dipole HFET has a much smaller gate leakage current leading to superior performance of enhancement-mode devices. The results demonstrate the effectiveness of the dipole layer concept for digital HFET devices     

Long-channel field-effect transistor with short-channel transistor properties

The typical parameters of samples of long-channel field-effect transistors and the results of measurement of their functional characteristics are presented. The possible distributions of the carrier mobility over the channel thickness are considered. The current-voltage characteristics of long-channel field-effect transistors with an arbitrary doping profile and carrier-mobility gradient are theoretically analyzed taking into account carrier velocity saturation.     

The cylindrical field-effect transistor

The characteristics of a cylindrical field-effect transistor are derived analytically on the basis of Shockley's theory of the planar field-effect transistor. It is found that the cylindrical device is capable of giving twice the (voltage) amplification factor of that of the planar device. Its frequency behavior should be comparable to that of the Shockley unit. Because of the loss of one degree of freedom, the transconductance and power characteristics of the cylindrical field-effect transistor are sharply limited. Experimental data support the analytical results.     

Charge-storage junction field-effect transistor

A charge-storage junction FET (CSJFET) has been developed which is capable of storing a charge in its gate region. The storage time can be varied in the orders of several seconds to less than one microsecond by illumination or by hole injection. This function is given by the double-layered structure of the gate region. The stored negative space charge in the floating gate region controls the channel conductance of a CSJFET. An illumination-time convertor and a variable delay-time controller are the basic applications. CSJFET's can easily be fabricated by the bipolar-IC technology.     

Superconductive magnetoelectric field-effect transistor

A transistor-like three-terminal superconducting device-the superconductive magnetoelectric field-effect transistor (SMET)-is described. The SMET represents a field-controlled Josephson device with its control based on the magnetoelectric effect. The device is characterized by a very high input-output isolation because the input is strictly voltage-controlled. As such, it may be useful for interconnecting voltage-controlled semiconductor electronics with current-controlled superconducting devices. The design considerations are reviewed, and preliminary experimental results are presented. Possible other practical applications are also discussed     

High-frequency silicon alloy transistor

The silicon alloy transistor is a high-frequency, p-n-p type transistor capable of operation at high temperatures. Its temperature characteristic, derived principally from the use of silicon as the semiconductor, permits operation from - 70°C to 150°C. It achieves its high-frequency characteristic through accurate control of the base geometry. The n-type base of silicon is accurately machined by jet electrochemical techniques. Alloy contacts of aluminum are fused into the bottoms of the etch pits without producing appreciable change in base geometry. The depth of alloy is limited by the thickness of the aluminum, by the temperature, and by the length of time for alloying. Lead wires are soldered to the aluminum contacts and the transistor hermetically sealed in glass-metal containers. The electrical characteristics of typical silicon alloy transistors include an Icoof 0.005 µa, a common emitter forward current gain of 12, and an alpha-cutoff frequency of 12 mc.     

Dual-gate gallium-arsenide microwave field-effect transistor

Dual-gate gallium-arsenide field-effect transistors have been fabricated which give power gains greater than those which can be obtained from single-gate devices of similar gate length. Unconditionally stable gains in excess of 12 dB at 5 GHz have been measured for these devices.     

Static large-signal field-effect transistor models

A series of static large-signal field-effect transistor (FET) models are presented which consist of familiar circuit building blocks plus a new nonlinear element, the ideal field-effect diode. The models present a unified form for all types of FET's, and generate the complete set of static FET characteristics, including inverted operation.     

Elementary ambipolar field-effect transistor model

An ambipolar FET can be operated alternatively in n-channel and p-channel modes. A simple conceptual model is proposed. It considers ohmic source and drain contacts, a gradual channel, and the depletion approximation.     

Microwave silicon Schottky-barrier field-effect transistor

Schottky-barrier field-effect transistors have been realised in silicon epitaxial films on high-resistivity silicon substrates. The 1 ?m wide gates are produced by projection-masking techniques. The maximum transconductances observed are 42 mA/V per mm gate length; the maximum frequency of oscillation fmax was 8 GHz.