Effects of crystallization on trap state densities at grain boundaries in polycrystalline silicon

The relationship between crystallization processes in the formation of polycrystalline-silicon (poly-Si) films and trap state densities at grain boundaries is described. Three different crystallization techniques were used to obtain poly-Si films: 1) LPCVD, 2) solid-phase crystallization, and 3) laser recrystallization. Trap state densities in laser-recrystallized poly-Si are 9.2-9.6 × 10¹¹cm^-2, regardless of grain size. These values are half of those in LPCVD and solid-phase crystallized poly-Si. It is indicated quantitatively that laser-induced melting and the subsequent solidification process exert a significant influence on the electrical activity of silicon grain boundaries.     

接触面陷阱密度对a-InSnZnO薄膜晶体管器件电气性能的影响研究

We reported the influence of interface trap density（Nt） on the electrical properties of amorphous InSnZnO based thin-film transistors,which were fabricated at different direct-current（DC） magnetron sputtering powers.The device with the smallest N_t of 5.68×10¹¹ cm^-2 and low resistivity of 1.21×10^-3Ω·cm exhibited a turn-on voltage(V_ON) of-3.60 V,a sub-threshold swing（S.S） of 0.16 V/dec and an on-off ratio(I_ON/I_OFF) of⁸ x 108.With increasing N_t,the V_ON,S.S and I_ON/I_OFF were suppressed to-9.40 V,0.24 V/dec and 2.59×10⁸,respectively.The V_TH shift under negative gate bias stress has also been estimated to investigate the electrical stability of the devices.The result showed that the reduction in N_t contributes to an improvement in the electrical properties and stability.     

Modeling the electrical characteristics of TIPS-pentacene thin-film transistors: Effect of contact barrier,field-dependent mobility,and traps

The device characteristics of organic thin-film transistors (OTFT) fabricated using tris-isopropylsilylethynyl (TIPS)-pentacene are analyzed with the help of a two-dimensional physics-based numerical simulation. The model incorporates contact barrier at a metal–semiconductor interface, field-dependent mobility, and trap distribution in TIPS-pentacene films and at dielectric-semiconductor interface. The Poole–Frenkel type field-dependence of mobility is included in addition to the contact barrier height of 0.38 eV to describe the non-ideal behavior in the linear region of the output characteristics. An account of the transfer characteristics and its hysteresis behavior is completed in both below- and above- threshold region upon consideration of the presence of acceptor-like traps of an exponential distribution in TIPS-pentacene films and positive trapped charges at dielectric-semiconductor interface. The obtained device parameters not only match the electrical characteristics but also give one an insight on the charge injection, transport, and trap properties of TIPS-pentacene from the perspectives of TFT operation.     

Effects of longitudinal grain boundaries on the performance ofMILC-TFTs

Compared to conventional solid phase crystallized (SPC) thin-film transistors (TFTs), metal induced laterally crystallized (MILC) TFTs exhibit significantly enhanced performance at reduced processing temperature. It is concluded that the major improvements in MILC-TFTs result from the growth of the crystal grains in a direction longitudinal to that of the current flow, whereas in SPC-TFTs, the grain boundaries are randomly oriented. It is also observed in this work that while the MILC-TFTs are less sensitive to short-channel effects (SCEs), their leakage current exhibits higher sensitivity to channel length reduction. These differences again can be traced to the different arrangements of the grain boundaries in the two types of devices     

The effect of grain boundaries on the electrical properties of zinc oxide-based varistor

The ac response of ZnO-based varistors was measured as a function of temperature and applied electric field. Conductivity-frequency measurements indicated that the grain boundaries of the ZnO varistors were amorphous. The device resistance was found to decrease as the temperature/applied field increased. This was attributed to deterioration of the insulating property of the grain boundaries due to generation of conduction carriers in the ZnO grains. As a large amount of these charge carriers passed through the grain boundaries, the ZnO varistors remarkably revealed a non-Debye characteristic that can be modeled by a capacitance to simulate the behavior of the grain boundaries.     

The effects of grain boundaries in the electrical characteristics of large grain polycrystalline thin-film transistors

High-performance low-voltage thin-film transistors (TFTs) can be fabricated by grain-enhancement methods such as nickel-seeded metal-induced lateral crystallization (MILC). Electrical characteristics of the TFTs may vary due to the existence of the grain boundaries in the device active region. To obtain the best device characteristics, the effect of grain boundaries on the device must be investigated. In this paper, the cumulative distributions of the device properties such as leakage current, threshold voltage, subthreshold slope, and field-effect mobility as a function of different channel lengths and widths were studied. In general, the grain boundary effects decrease with device size. Devices with short channel lengths and wide channel widths may suffer from degradation due to large leakage current. Moreover, the effects due to the location of the nickel-seeding region on device characteristics were investigated. These include the effect of the longitudinal and lateral grain boundaries and the distance between the nickel seeding region and the device. Finally, a design guideline to reduce the grain boundary effect is presented.     

Effects of grain boundaries on laser crystallized poly-Si MOSFET's

Data are reported for n-MOSFET's fabricated in laser crystallized poly-Si on amorphous insulating substrates. The dependence of electrical characteristics on the effective channel length in the range of 100 to 0.3 µm and on channel width from 120 to 20 µm is presented. The electron surface mobility is found to increase as the channel length is reduced, approaching that of devices in single-crystalline silicon. The source-to-drain leakage current, negligible for long channels, rapidly increases for channels shorter than ≃ 3 µm. This excessive current results from grain boundary diffusion of As from source and drain during high temperature fabrication steps.     

Effects of grain boundaries on the channel conductance of SOl MOSFET's

A physical model that describes the effects of grain boundaries on the linear-region (strong-inversion) channel conductance of SOI (polysilicon on silicon-dioxide) MOSFET's is developed and supported experimentally. The model predicts an effective turn-on characteristic that occurs beyond the strong-inversion threshold, and henceforth defines the "carrier mobility threshold voltage" and the effective field-effect carrier mobility in the channel, which typically is higher than the actual (intragrain) mobility. These parameters, which are defined by the properties of the grain boundaries, can easily be misinterpreted experimentally as the threshold voltage and the actual carrier mobility.     

Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements

High field electrical stress effects on the mid-gap interface trap density (D_it0) and geometric mean capture cross sections (σ₀) in n-MOSFETs have been studied using the pulsed interface probing method. The results show that the PIP technique is sensitive to changes in mid-gap trap cross section values caused by the Fowler–Nordheim (F–N) electrical stress. The decrease of mid-gap trap cross sections following the F–N tunneling injection is found. Our works also provide further insight into the influence of electrical stress on mid-gap interface trap generation in n-MOSFETs without the assumption of the constant capture cross section value during F–N stresses.     

Carrier mobility in pentacene as a function of grain size and orientation derived from scanning transmission X-ray microscopy

Pentacene field-effect transistors were prepared on silicon nitride membranes for scanning transmission X-ray microscopy (STXM) investigations. The membranes were modified by different self-assembled monolayers (SAMs). Pentacene was deposited atop the SAM-treated membrane and the in-plane orientation of the grains were subsequently investigated by polarization dependent STXM measurements. The grain sizes were determined and compared to those obtained from atomic force microscopy (AFM) measurements. Statistical analysis of the grain orientation was correlated with the charge carrier mobility of the films, in which we observed an increase in the mobility with increasing grain size and decreasing surface roughness of the SAM.     

不同狭缝与遮挡条设计对TFT特性的影响与规律(英文)

通过对掩膜版上不同狭缝与遮挡条设计与TFT沟道形貌、电学特性相互关系的分析,发现随着狭缝与遮挡尺寸的减小,TFT的电学特性、沟道处光刻胶起伏与最终关键尺寸偏移量都会改善。狭缝的尺寸比遮挡条的尺寸对TFT特性的影响更加显著。考虑到沟道转角处的短路几率问题,小的狭缝与遮挡条尺寸设计更加适合于四次掩膜光刻工艺,转角处的缺陷可以通过调整遮挡条的尺寸来避免。     

Effects of grain boundaries on the current-voltage characteristics of polycrystalline silicon solar cells

The current components associated with the grain boundaries of diffused p/n junction polysilicon solar cells made on n- and p-type Wacker substrates are analyzed and experimentally identified. New electrical methods for determining the presence or absence of preferential diffusion along the grain boundaries and for determining the average doping density of preferentially diffused regions along the grain boundaries are described. For p-type substrates, these methods revealed preferential phosphorus diffusion along grain boundaries; no preferential boron diffusion along grain boundaries was observed. The recombination current components were analyzed for the cells in which preferential diffusion occurred. The analysis shows that the dominant current component at small bias levels (0-300 mV) is the recombination current at the grain boundaries within the p/n junction space-charge region. At higher bias levels (V simeq V_{OC} simeq 500-600mV), both this current component and the current component due to recombination at that part of the grain boundary below the preferentially diffused region are important. The grain-boundary shunt resistance does not contribute a significant current component. It is shown that the preferential diffusion makes negligible the recombination current injected into the sidewall of the preferentially diffused region. This is consistent with a model in which the phosphorus diffusion significantly lowers the surface recombination velocity at the grain boundaries and in which the retarding built-in electric field further decreases the recombination current.     

Effect of enhanced-mobility current path on the mobility of AOS TFT

In this study, the mobility enhancement in an Amorphous Oxide Semiconductor Thin Film Transistor (AOS TFT), particularly the effect of enhanced-mobility current path was investigated. In the TFT structure, the a-IGZO single active channel layer was replaced by double layers. Indium Tin Oxide (ITO) was employed as an enhanced-mobility current path material and was embedded in an amorphous Indium Gallium Zinc Oxide (a-IGZO) channel layer of a conventional bottom gate structure TFT. To analyze the effect of the length of an additional current path, the a-IGZO channel length was fixed at 80 μm, and the length of the ITO enhanced-mobility current path was increased to 20, 40, and 60 μm. As a result, the mobility increased monotonically with the length of the enhanced-mobility current path and was predictable from the rule of mixture. The maximum saturation mobility of 28.3 cm²/V s resulted when the length of the enhanced-mobility current path was 60 μm. This value is more than double that of a single path TFT. Such enhancement in mobility is attributed to the high conductivity of ITO and a good conduction band match between a-IGZO and ITO.     

Effects of longitudinal and latitudinal grain boundaries on theperformance of large-grain polysilicon MOSFET

The effects of longitudinal and latitudinal polysilicon grain boundaries on the performance metal oxide semiconductor field effect transistors (MOSFETs) fabricated on large-grain polysilicon-on-insulator (LPSOI) have been investigated. Unlike conventional thin-film-transistors (TFTs) with random grain distribution, MOSFETs fabricated on the LPSOI film contains the combination of only longitudinal or latitudinal grain boundaries. Longitudinal GBs parallel to the direction of current flow has smaller impact to the current flow, but provided extra leakage current that caused early device shortage, especially in wide devices. The latitudinal GBs perpendicular to the direction of current flow offered higher resistance to the inversion carriers thus causing lower current drive, higher threshold voltage, and gentler subthreshold slope. The result of the study can be used to optimize device design for high performance on MOSFETs on the LPSOI substrate     

The effect of nitrogen plasma anneals on interface trap density and channel mobility for 4H-SiC MOS devices

We report results on the introduction of nitrogen at the SiC/SiO₂ interface using a plasma process, thus avoiding the detrimental effects of additional oxidation that accompany other standard nitridation processes, such as annealing in NO gas. The plasma process results in an ‘NO-like’ mobility for approximately 1/6 the interfacial nitrogen content injected via the gas anneal. Direct exposure of the oxide to the plasma is also shown to have a deleterious effect on the breakdown characteristics of the oxide.     

Effect of molybdenum electrode annealing on the interface properties between metal and pentacene

Contact resistance between molybdenum (Mo) electrode and pentacene was studied with transmission line method (TLM). The Mo electrodes were annealed at 200 °C, 400 °C, 600 °C and 800 °C for 1 h and pentacene layer of 300 Å thickness was vacuum deposited on patterned Mo to form Mo–pentacene contact. Current–voltage measurement for Mo–pentacene contact showed linear relationship and it was confirmed that ohmic contact was formed. XRD and AFM measurements showed that Mo could be crystallized at annealing temperatures above 600 °C. 800 °C annealed Mo showed larger grains and work function was increased from 4.60 eV to 4.80 eV due to the decrease in defect density. The contact resistance was reduced down to 11.2 MΩ cm from 37.8 MΩ cm of as-deposited Mo. Also the pentacene film deposited on annealed Mo was denser with better crystallinity. Bottom contact organic field-effect transistor made with 800 °C annealed Mo showed better performance than as deposited Mo.     

Nonequilibrium behavior of depletion, inversion, and accumulation grain boundaries

The recombination velocity of polysilicon grain boundaries is calculated from the Shocley-Read-Hall formula, taking into account the balance of charges for nonequilibrium conditions. The calculation is not restricted to grain boundaries in depletion, but applies to the full range of band bending. The results show the existence of significant differences in the nonequilibrium behavior of depletion, inversion, and accumulation grain boundaries. For depletion/inversion grain boundaries, the recombination velocity is small and nearly independent of excitation for both low- and high-state densities, whereas medium-state densities show high recombination velocities and a strong injection dependence. Accumulation grain boundaries always provide lower recombination velocities than depletion/inversion grain boundaries and they do not show any dependence upon excitation. In order to verify the theoretical excitation dependences, several n⁺-p and p⁺-n solar cells prepared from polycrystalline bulk material have been investigated under various insolation conditions. For the n⁺-p cells, deviations from a linear dependence of the short circuit current upon intensity were observed, whereas the p⁺-n cells showed a precisely linear dependence, indicating depletion/inversion grain boundaries in p-type, but accumulation grain boundaries in n-type polysilicon.     

Effects of twin grain boundaries on the subgrain rotation of the solder joint during thermal shock

The ball grid array (BGA) component was selected as the specimen with the outmost edge row cross-sectioned to investigate subgrain rotation behavior influenced by grain boundaries under thermal shock cycles condition. To study the subgrain rotation, the crystal orientation was obtained by electron backscattered diffraction(EBSD). The results showed that a lot of subgrains were generated in the solder joints due to cyclic stress caused by the high mismatched coefficient of thermal expansion (CTE) under the thermal shock cycles condition. And the subgrains near the chip-side and the twin grain boundaries were analyzed in detail to estimate the impact of the grain boundaries on the subgrain rotation behavior. The results showed that a large number of subgrain boundaries and several newly generated subgrains appeared at the tilted twin grain boundaries and the chip-side in the solder joint after 200 thermal shock cycles. Meantime, the subgrain rotation axes and misorientation angles were both calculated, and the dislocation slip was recognized to closely relate to subgrain rotation by comprehensively analyzing the rotation axes and misorientation angles. The subgrain rotation axes of the chip-side was about Sn [101] and [001], while the subgrains rotation near the tilted grain boundaries in the same dominant grain was different from that of the subgrains near the chip-side, and subgrain rotation axes were [101], [100] and [110]. There were also a large difference in the direction of subgrain rotation between the chip-side and the tilted twin grain boundaries. The subgrain rotation axes at both sides of twin grain boundaries were similar, but the rotation directions were opposite.     

The effects of the surface morphology of poly(3,4-ethylenedioxythiophene) electrodes on the growth of pentacene,and the electrical performance of the bottom contact pentacene transistor

An investigation is presented of the effect of the surface roughness of poly(3,4-ethylenedioxythiophene) (PEDOT) electrodes on the growth of pentacene and the electrical performance of PEDOT electrode bottom contact pentacene transistor. Smooth PEDOT films contained well-oriented and small sized pentacene islands whilst rough PEDOT films exhibited randomly oriented islands with non-uniformly sized islands. In addition, PEDOT electrodes provided morphological continuity at the electrode–channel interface, making the accumulation channel of the pentacene formed on the electrodes a main contributor to the contact resistance. Accordingly, the smooth PEDOT surface yielded the low contact resistance (5.7 kΩ cm), approximately half of that obtained with the rough surface.