一种结构新颖的流水线Booth乘法器设计

在对传统Booth乘法器研究的基础上,介绍了一种结构新颖的流水线型布什(Booth)乘法器。使用基-4 Booth编码、华莱士树(Wallace Tree)压缩结构、64位Kogge-Stone前缀加法器实现,并在分段实现的64位Kogge-Stone前缀加法器中插入4级流水线寄存器,实现32 t×32 bit无符号和有符号数快速乘法。用硬件描述语言设计该乘法器,使用现场可编程门阵列(Field Programmable Gate Array,FPGA)进行验证,并采用SMIC 0.18 μm CMOS标准单元工艺对该乘法器进行综合。综合结果表明,电路的关键路径延时为3.6 ns,芯片面积＜0.134 mm,功耗＜32.69 mW。     

20×18位符号定点乘法器的FPGA实现

在数字信号处理中经常需要进行乘法运算,乘法器的设计对整个器件的性能有很大的影响,在此介绍20×18比特定点阵列乘法器的设计.采用基4-Booth算法和4-2压缩的方案,并采用先进的集成电路工艺,使用SMIC 0.18μm标准单元库,提高了乘法器的速度,节省了器件.利用Xilinx FPGA(xc2vp70-6ff1517)对乘法器进行了综合仿真,完成一次乘法运算的时间为15.922 ns,在减少乘法器器件的同时,提高了乘法器的速度,降低了器件的功耗.     

基于改进的布斯算法FPGA嵌入式18×18乘法器

设计了一款嵌入FPGA的乘法器,该乘法器能够满足两个18b有符号或17b无符号数的乘法运算。该设计基于改进的布斯算法,提出了一种新的布斯译码和部分积结构,并对9-2压缩树和超前进位加法器进行了优化。该乘法器采用TSMC 0.18μm CMOS工艺,其关键路径延迟为3.46ns。     

FPGA中专用可重构乘法器的设计

提出了一种新的嵌入在FPGA中可重构的流水线乘法器设计. 该设计采用了改进的波茨编码算法,可以实现18×18有符号乘法或17×17无符号乘法. 还提出了一种新的电路优化方法来减少部分积的数目,并且提出了一种新的乘法器版图布局,以便适应tile-based FPGA 芯片设计所加的约束. 该乘法器可以配置成同步或异步模式,也可以配置成带流水线的模式以满足高频操作. 该设计很容易扩展成不同的输入和输出位宽. 同时提出了一种新的超前进位加法器电路来产生最后的结果. 采用了传输门逻辑来实现整个乘法器. 乘法器采用了中芯国际0.13μm CMOS工艺来实现,完成18×18的乘法操作需要4.1ns. 全部使用2级的流水线时,时钟周期可以达到2.5ns. 这比商用乘法器快29.1%,比其他乘法器快17.5%. 与传统的基于查找表的乘法器相比,该乘法器的面积为传统乘法器面积的1/32.     

指纹识别专用集成电路中乘法器模块的设计

介绍了一种用于指纹识别专用集成电路(ASIC)的乘法器模块的设计.该乘法器模块能够处理32位的有符号数、无符号数的乘法和乘加运算.电路采用基-4的Booth编码以及改进型压缩器阵列结构.采用提出的迭代和阵列结合的结构算法,可节省芯片面积30%,提高工作频率24%.模块电路在TSMC 0.25 μm工艺上实现.该乘法器模块易于移植到其他数字处理系统.     

FPGA中专用可重构乘法器的设计

提出了一种新的嵌入在FPGA中可重构的流水线乘法器设计.该设计采用了改进的波茨编码算法,可以实现18×18有符号乘法或17×17无符号乘法.还提出了一种新的电路优化方法来减少部分积的数目,并且提出了一种新的乘法器版图布局,以便适应tilebased FPGA芯片设计所加的约束.该乘法器可以配置成同步或异步模式,也町以配置成带流水线的模式以满足高频操作.该设计很容易扩展成不同的输入和输出位宽.同时提出了一种新的超前进位加法器电路来产生最后的结果.采用了传输门逻辑来实现整个乘法器.乘法器采用了中芯国际0.13μm CMOS工艺来实现,完成18×18的乘法操作需要4.1ns.全部使用2级的流水线时,时钟周期可以达到2.5ns.这比商用乘法器快29.1%,比其他乘法器快17.5%.与传统的基于查找表的乘法器相比,该乘法器的面积为传统乘法器面积的1/32.     

54位高速冗余二进制乘法器的设计

冗余二进制(RB)数是一种有符号数的表示方法,利用冗余二进制算法的进位无关特性和规整的结构,可以设计高速RB并行乘法器.系统地研究了RB乘法器的算法和结构,给出了基于修正Booth算法,RB部分积压缩树和RB-NB转换器的54b乘法器的设计过程,并利用并行前缀/进位选择混合加法器对RB-NB转换器进行优化设计.采用Verilog HDL对乘法器进行描述,并在ModelSim平台上进行仿真验证,在SMIC 0.18mm标准工艺库下,通过Synopsys公司综合工具Design Compiler进行综合,得到54bRB乘法器的延时可达到3.97ns,面积是409 293mm2.     

基于Booth算法的32×32乘法器IP核设计

在Booth算法的基础上,提出了一个适用于多媒体加速单元(Multirnedia Accelerator)的乘法器IP核设计。通过增加一位符号位,本设计支持32X32无符号和有符号乘法。通过一个32X9结合2-bit Booth算法阵列乘法器循环四次加法．完成32bit乘法。前四个时钟周期,每次处理一个9bit乘法,后两个周期分别处理低32bit和高32bit加法。我们采用2．5v,0．25μm SMIC CMOS工艺,实现乘法器的设计,其中部分积求和部分和ALU单元．Hspice仿真的最大延迟分别为0．64ns,1．51ns。     

32位定/浮点乘法器设计

针对Wallace树连接线复杂度高,版图实现比较困难的缺点,提出了一种新的加法器阵列结构.这种结构在规则性和连接复杂度方面优于ZM树和OS树.同时提出一种新的CLA加法器结构以提高乘法器的性能.乘法器采用1.5μm CMOS工艺实现,完成一次定点与浮点乘法操作的时间分别是56ns和76ns.     

32位定/浮点乘法器设计

针对 Wallace树连接线复杂度高 ,版图实现比较困难的缺点 ,提出了一种新的加法器阵列结构 .这种结构在规则性和连接复杂度方面优于 ZM树和 OS树 .同时提出一种新的 CL A加法器结构以提高乘法器的性能 .乘法器采用 1.5μm CMOS工艺实现 ,完成一次定点与浮点乘法操作的时间分别是 5 6 ns和 76 ns     

Resolution Enhancement Technology:Integrated Process Solutions using OPC

DUV lithography, using the 248 nm wavelength, is a viable manufacturing option for devices with features at 130 nm and less. Given the low kl value of the lithography, integrated process development is a necessary method for achieving acceptable process latitude. The application of assist features for rule based OPC requires the simultaneous optimization of the mask, illumination optics and the resist.Described in this paper are the details involved in optimizing each of these aspects for line and space imaging.A reference pitch is first chosen to determine how the optics will be set. The ideal sigma setting is determined by a simple geometrically derived expression. The inner and outer machine settings are determined, in turn,with the simulation of a figure of merit. The maximum value of the response surface of this FOM occurs at the optimal sigma settings. Experimental confirmation of this is shown in the paper.Assist features are used to modify the aerial image of the more isolated images on the mask. The effect that the diffraction of the scattering bars (SBs) has on the image intensity distribution is explained. Rules for determining the size and placement of SBs are also given.Resist is optimized for use with off-axis illumination and assist features. A general explanation of the material' s effect is discussed along with the affect on the through-pitch bias. The paper culminates with the showing of the lithographic results from the fully optimized system.     

Cost-effective test solutions for smart card and other integrated flash applications

From its emergence in the late 1980s as a lower cost alternative to early EEPROM technologies, flash memory has evolved to higher densities and speedsand rapidly growing acceptance in mobile applications.In the process, flash memory devices have placed increased test requirements on manufacturers. Today, as flash device test grows in importance in China, manufacturers face growing pressure for reduced cost-oftest, increased throughput and greater return on investment for test equipment. At the same time, the move to integrated flash packages for contactless smart card applications adds a significant further challenge to manufacturers seeking rapid, low-cost test.     

Theoretical analysis of the relationship between the Brillouin gain coefficient and the strain in the optical-fiber sensors

The relation between the power of the Brillouin signal and the strain is one of the bases of the distributed fiber sensors of temperature and strain. The coefficient of the Bfillouin gain can be changed by the temperature and the strain that will affect the power of the Brillouin scattering. The relation between the change of the Brillouin gain coefficient and the strain is thought to be linear by many researchers. However, it is not always linear based on the theoretical analysis and numerical simulation. Therefore, errors will be caused if the relation between the change of the Brillouin gain coefficient and the strain is regarded as to be linear approximately for measuring the temperature and the strain. For this reason, the influence of the parameters on the Brillouin gain coefficient is proposed through theoretical analysis and numerical simulation.     

An improved parallel thinning algorithm with two subiterations

The parallel thinning algorithm with two subiterations is improved in this paper. By analyzing the notions of connected components and passes, a conclusion is drawn that the number of passes and the number of eight-connected components are equal. Then the expression of the number of eight-connected components is obtained which replaces the old one in the algorithm. And a reserving condition is proposed by experiments, which alleviates the excess deletion where a diagonal line and a beeline intersect. The experimental results demonstrate that the thinned curve is almost located in the middle of the original curve connectivelv with single pixel width and the processing speed is high.     

Novel fiber-optical interferometer with miniaturized probe for in-hole measurements

Today, micro-system technology and the development of new MEMS （Micro-Electro-Mechanical Systems） are emerging rapidly. In order for this development to become a success in the long run, measurement systems have to ensure product quality. Most often, MEMS have to be tested by means of functionality or destructive tests. One reason for this is that there are no suitable systems or sensing probes available which can be used for the measurement of quasi inaccessible features like small holes or cavities. We present a measurement system that could be used for these kinds of measurements. The system combines a fiber optical, miniaturized sensing probe with low-coherence interferometry, so that absolute distance measurements with nanometer accuracy are possible.     

Study of waveguide coupling efficiency in hybrid silicon lasers

This paper presents a new method to increase the waveguide coupling efficiency in hybrid silicon lasers. We find that the propagation constant of the InGaAsP emitting layer can be equal to that of the Si resonant layer through improving the design size of the InP waveguide. The coupling power achieves 42% of the total power in the hybrid lasers when the thickness of the bonding layer is 100 nm. Our result is very close to 50% of the total power reported by Intel when the thickness of the thin bonding layer is less than 5 nm. Therefore, our invariable coupling power technique is simpler than Intel＇s.     

Teleportation of an arbitrary unknown N-qubit entangled state under the controlling of M controllers

A new quantum protocol to teleport an arbitrary unknown N-qubit entangled state from a sender to a fixed receiver under M controllers(M < N) is proposed. The quantum resources required are M non-maximally entangled Greenberger-Home-Zeilinger (GHZ) state and N-M non-maximally entangled Einstein-Podolsky-Rosen (EPR) pairs. The sender performs N generalized Bell-state measurements on the 2N particles. Controllers take M single-particle measurement along x-axis, and the receiver needs to introduce one auxiliary two-level particle to extract quantum information probabilistically with the fidelity unit if controllers cooperate with it.     

Diode-end-pumped Nd:YVO4/LBO lasers with 4.2W continuous-wave output at 457 nm

A continuous-wave (CW) 457 nm blue laser operating at the power of 4.2 W is demonstrated by using a fiber coupled laser diode module pumped Nd: YVO4 and using LBO as the intra-cavity SHG crystal With the optimization of laser cavity and crystal parameters, the laser operates at a very high efficiency. When the pumping power is about 31 W, the output at 457nm reaches 4.2 W, and the optical to optical conversion efficiency is about 13.5% accordingly. The stability of the out putpower is better than 1.2% for 8 h continuously working.     

Call for Papers

正Wireless Body-area Networks The last decade has witnessed the convergence of three giant worlds:electronics,computer science and telecommunications.The next decade should follow this convergence in most of our activities with the generalization of sensor networks.In particular with the progress in medicine,people live longer and the aging of population will push the development of wireless personal networks     

Call for Papers—Feature Topic,Vol.12,No.7,2015

正Information Centric Networking Information-Centric Networking(ICN) is an emerging direction in Future Internet architecture research,gaining significant tractions among academia and industry.Aiming to replace the conventional host-to-host communication model by a data-centric model,ICN treats data content as the first