Incremental Testability Analysis for Partial Scan Selection and Design Transformations

This paper presents an efficient estimation method for incremental testability analysis, which is based partially on explicit testability re-calculation and partially on gradient techniques. The analysis results have been used successfully to guide design transformations and partial scan selection. Experimental results on a variety of benchmarks show that the quality of our incremental testability analysis is similar to those of the conventional explicit testability re-calculation methods and the technique can be used efficiently for improving the testability of a design during the high-level test synthesis and partial scan selection processes.     

A synthesis-based test generation and compaction algorithm for multifaults

Because of its inherent complexity, the problem of automatic test pattern generation for multiple stuck-at faults (multifaults) has been largely ignored. Recently, the observation that multifault testability is retained by algebraic factorization demonstrated that single fault (and therefore multifault) vector sets for two-level circuits could give complete multifault coverage for multilevel circuits constructed by algebraic factorization. Unfortunately, in using this method the vector set size can be much larger than what is really required to achieve multifault coverage, and the approach has some limitations in its applicability.In this article we first present a multifault test generation and compaction strategy for algebraically factored multilevel circuits, synthesized from two-level representations. We give a basic sufficiency condition for multifault testability of such networks.We next focus on the relationship between hazard-free robust path-delay-fault testability and multifault testability. We show that the former implies the latter for arbitrary multilevel circuits. This allows the use of previously developed composition rules that maintain path-delay-fault testability for the synthesis of multifault testable circuits.We identify a class of multiplexor-based networks and prove an interesting property of such networks—if the networks are fully single stuck-at fault testable, or made fully single stuck-at fault testable, they are completely multifault testable. We give a multifault test generation and compaction algorithm for such networks.We provide experimental results which indicate that a compacted multifault test set derived using the above strategies can be significantly smaller than the test set derived using previously proposed procedures. These results also indicate the substantially wider applicability of our procedures, as compared to previous techniques.     

一种减少BIST测试资源的高级寄存器分配算法

在高级综合阶段考虑电路的可测性有许多优点，包括降低硬件开销，减少性能的下降，并达到更高的测试效率等。本文提出了一种基于伪随机可测性方法的寄存器分配算法，来减少内建自测试（BIST）所带来的硬件开销。在基准电路上的实验结果表明：与其它BIST测试综合方法相比较，采用本论文所提的方法进行测试综合对测试资源占用最多可以降低46.8%.     

Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits

In this paper, we propose a controller resynthesis technique to enhance the testability of register-transfer level (RTL) controller/data path circuits. Our technique exploits the fact that the control signals in an RTL implementation are don't cares under certain states/conditions. We make an effective use of the don't care information in the controller specification to improve the overall testability (better fault coverage and shorter test generation time). If the don't care information in the controller specification leaves little scope for respecification, we add control vectors to the controller to enhance the testability. Experimental results with example benchmarks show an average increase in testability of 9% with a 3–4 fold decrease in test generation time for the modified implementation. The area, delay and power overheads incurred for testability are very low. The average area overhead is 0.4%, and the average power overhead is 4.6%. There was no delay overhead due to this technique in most of the cases.     

雷达系统测试性设计

良好的测试性设计对雷达系统而言,可以有效地提高其维修性、保障性,降低全寿命周期费用。简要回顾了测试性的发展,指出了测试性设计对雷达系统的重要性和必要性,并给出了雷达系统的测试性设计的基本原则。从网络化设计、分层次设计、外场可更换模块（LRM）设计、校正维护设计和故障诊断设计等方面详细介绍了雷达系统的机内测试（BIT）设计,对原位检测设计和自动测试设备（ATE）设计进行了简要介绍。随着雷达技术的不断发展,在BIT技术、ATE技术进行创新发展的同时,还应积极探索综合诊断技术、预测和健康管理（PHM）技术等新的诊断方法在雷达系统测试性设计中的应用。     

A New Testability Calculation Method to Guide RTL Test Generation

Current paper presents a unified approach for calculating mixed-level testability measures. In addition, a new method of testability guided RTL Automated Test Pattern Generation (ATPG) for sequential circuits is introduced. The methods and algorithms are based on path tracing procedures on decision diagrams. The previous known methods have been implemented in test synthesis and in guiding gate-level test generation. However, works on application of testability measures to guide high-level test generation are missing. The main aim of this paper is to bridge this gap. Current method is compared to a recent approach known from the test synthesis area. Experiments show that testability measures greatly influence the fault coverage in RT-level test generation with the proposed approach achieving the best results. Similar to earlier works, our research confirms that RT-level fault coverage is in correlation with logic level one.This revised version was published online in March 2005 with corrections to the cover date.     

测试性技术分析与试验验证刍议

测试性质量特性是武器装备试验考核内容之一,攸关武器装备能否快速地检测故障并隔离故障。文中阐述了装备测试技术设计、测试性试验需求和靶场验证方法,着重研究了测试性定性检查、定量检查的基本准则和实施途径。并指出故障特征的分析提取和样本集的有效生成是测试验证的关键,旨在为提升武器装备测试性试验能力提供参考。     

数字调谐系统芯片DTSO614的可测性设计

介绍了集成电路可测性设计的概念和分类方法,然后以数字调谐系统芯片DTS0614为例,具体介绍了其中的一种即针对性可测性设计方法,包括模块划分、增加控制线和观察点.最后给出了提高电路可测性的另一种方法--内建自测试方法.     

Testability and test generation for majority voting fault-tolerant circuits

The testability of majority voting based fault-tolerant circuits is investigated and sufficient conditions for constructing circuits that are testable for all single and multiple stuck-at faults are established. The testability conditions apply to both combinational and sequential logic circuits and result in testable majority voting based fault-tolerant circuits without additional testability circuitry. Alternatively, the testability conditions facilitate the application of structured design for testability and Built-In Self-Test techniques to fault-tolerant circuits in a systematic manner. The complexity of the fault-tolerant circuit, when compared to the original circuit can significantly increase test pattern generation time when using traditional automatic test pattern generation software. Therefore, two test pattern generation algorithms are developed for detecting all single and multiple stuck-at faults in majority voting based circuits designed to satisfy the testability conditions. The algorithms are based on hierarchical test pattern generation using test patterns for the original, non-fault-tolerant circuit and structural knowledge of the majority voting based design. Efficiency is demonstrated in terms of test pattern generation time and cardinality of the resulting set of test patterns when compared to traditional automatic test pattern generation software.     

A Unified DFT Approach for BIST and External Test

This paper presents a partial reset technique for testability improvement of non-scan sequential circuits. Both pseudo-random BIST and deterministic External Test are in the scope of this paper. The partial reset technique is used to improve hard-to-detect fault activation. This DFT approach is completed with classical insertion of observation points in order to improve fault propagation. Numerous experimental results on ISCAS'89 benchmark circuits show that 100% fault efficiency can be achieved at low cost.     

电子装备测试性分析关键技术研究

针对目前国内测试性分析的理论较杂,缺少综合、适用的分析系统的问题,研究了利用功能—行为—结构(FBS)模型描述测试性的技术,提出了基于故障模式、影响和危害性分析法,利用FBS模型进行测试性分析,构建了测试性层次型预计体系。     

可测性度量的计算及研究

本文对ＳＣＯＡＰ可测性度量方法作了改进，提出了动态ＳＣＯＡＰ算法。此算法反映测试生成过程中系统和电路各节点可测性的变化，比静态ＳＣＯＡＰ更准确地描述了每个故障的可测性难度，为测试生成过程提供更有效的启发性信息。     

Integrating testability with design space exploration

Built-in self-test (BIST) has emerged as a promising test solution for high-speed, deep sub-micron VLSI circuits. Traditionally, the testability insertion phase comes after functional logic synthesis and verification in the design cycle. This creates two separate optimisation processes: functional optimisation followed by BIST insertion and optimisation. The first deals with functional design behaviour, while the second deals with test behaviour. Considering testability at such a late stage in the design flow limits efficient design space exploration. In this paper, we consider testability as a design objective alongside area and delay. We extend the concept of design space to include testability and show how this enhanced design space can be used by a high-level synthesis tool. We demonstrate that by taking testability into account at an early stage, we can generate better designs than by leaving BIST insertion to the end of the design cycle.     

航空电子系统的测试性及仿真研究

论述了仿真故障注入在测试性设计中的重要作用以及利用仿真进行测试性设计的几个重要环节。结合某飞机的凋堰电路给出了利用Pspice仿真软件研究电子产品测试性设计的方法，为测试设备的研制和开发提供一些新的思路。     

Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

Design for Testability Techniques at the Behavioral and Register-Transfer Levels

Improving testability during the early stages of the design flow can have several benefits, including significantly improved fault coverage, reduced test hardware overheads, and reduced design iteration times. This paper presents an overview of high-level design methodologies that consider testability during the early (behavior and architecture) stages of the design flow, and their testability benefits. The topics reviewed include behavioral and RTL test synthesis approaches that generate easily testable implementations targeting ATPG (full and partial scan) and BIST methodologies, and techniques to use high-level information for ATPG.     

一种针对多级串联模拟电路的可测性设计技术

随着集成电路的发展,测试难度的增加,可测试性设计也越来越重要。针对串联结构的模拟电路提出一种可测性设计结构,该结构大大提高了电路内系统模块的可测试性,减少了需要额外引出的I/O数,同时不随内部模块数的增加而增加,并且可以与数字电路的边界扫描技术相兼容,通过在Cadence下仿真,证明了该结构简单有效。