Interfacial phase-change memory

Phase-change memory technology relies on the electrical and optical properties of certain materials changing substantially when the atomic structure of the material is altered by heating or some other excitation process. For example, switching the composite Ge(2)Sb(2)Te(5) (GST) alloy from its covalently bonded amorphous phase to its resonantly bonded metastable cubic crystalline phase decreases the resistivity by three orders of magnitude, and also increases reflectivity across the visible spectrum. Moreover, phase-change memory based on GST is scalable, and is therefore a candidate to replace Flash memory for non-volatile data storage applications. The energy needed to switch between the two phases depends on the intrinsic properties of the phase-change material and the device architecture; this energy is usually supplied by laser or electrical pulses. The switching energy for GST can be reduced by limiting the movement of the atoms to a single dimension, thus substantially reducing the entropic losses associated with the phase-change process. In particular, aligning the c-axis of a hexagonal Sb(2)Te(3) layer and the 〈111〉 direction of a cubic GeTe layer in a superlattice structure creates a material in which Ge atoms can switch between octahedral sites and lower-coordination sites at the interface of the superlattice layers. Here we demonstrate GeTe/Sb(2)Te(3) interfacial phase-change memory (IPCM) data storage devices with reduced switching energies, improved write-erase cycle lifetimes and faster switching speeds.     

Ultra-high-density phase-change storage and memory

Phase-change storage is widely used in optical information technologies (DVD, CD-ROM and so on), and recently it has also been considered for non-volatile memory applications. This work reports advances in thermal data recording of phase-change materials. Specifically, we show erasable thermal phase-change recording at a storage density of 3.3 Tb inch(-2), which is three orders of magnitude denser than that currently achievable with commercial optical storage technologies. We demonstrate the concept of a thin-film nanoheater to realize ultra-small heat spots with dimensions of less than 50 nm. Finally, we show in a proof-of-concept demonstration that an individual thin-film heater can write, erase and read the phase of these storage materials at competitive speeds. This work provides important stepping stones for a very-high-density storage or memory technology based on phase-change materials.     

Programmable polymer thin film and non-volatile memory device

Building on the success of organic electronic devices, such as light-emitting diodes and field-effect transistors, procedures for fabricating non-volatile organic memory devices are now being explored. Here, we demonstrate a novel organic memory device fabricated by solution processing. Programmable electrical bistability was observed in a device made from a polystyrene film containing gold nanoparticles and 8-hydroxyquinoline sandwiched between two metal electrodes. The as-prepared device, which is in a low-conductivity state, displays an abrupt transition to a high-conductivity state under an external bias of 2.8 V. These two states differ in conductivity by about four orders of magnitude. Applying a negative bias of 1.8 V causes the device to return to the low-conductivity state. The electronic transition is attributed to the electric-field-induced charge transfer between the gold nanoparticles and 8-hydroxyquinoline. The transition from the low- to the high-conductivity state takes place in nanoseconds, and is non-volatile, indicating that the device may be used for low-cost, high-density memory storage.     

Antimony selenide phase-change nanowires for memory application

Synthesis and device characteristics of highly scalable antimony selenide nanowire-based phase transition memory are reported. Antimony selenide nanowires prepared using the metal-catalyst-free approach are single-crystalline and of high-purity. The nanowire memory can be repeatedly switched between high-resistance (approximately 10 Momega) and low-resistance (approximately 1 komega) states which are attributed to amorphous and crystalline states, respectively.     

Switching time of nanowire memory

Cadmium sulfide nanowires of 10-nm diameter, electrodeposited in porous anodic alumina films, exhibit an electronic bistability that can be harnessed for non-volatile memory. The current-voltage characteristics of the wires show two stable conductance states that are well-separated (conductances differ by more than 4 orders of magnitude) and long lived (longevity > 1 year at room temperature). These two states can encode binary bits 0 and 1. Here we report measurements of the switching time to switch from the high- to the low-conductance state. These measurements also shed some light on the physical mechanisms underlying the bistability.     

ZnO as dielectric for optically transparent non-volatile memory

This paper discusses the application of a DC sputtered ZnO thin film as a dielectric in an optically transparent non-volatile memory. The main motivation for using ZnO as a dielectric is due to its optical transparency and mechanical flexibility. We have established the relationship between the electrical resistivity (ρ) and the activation energy (E_a) of the electron transport in the conduction band of the ZnO film. The ρ of 2 × 10⁴–5 × 10⁷ Ω-cm corresponds to E_a of 0.36–0.76 eV, respectively. The k-value and optical band-gap for films sputtered with Ar:O₂ ratio of 4:1 are 53 ± 3.6 and 3.23 eV, respectively. In this paper, the basic charge storage element for a non-volatile memory is a triple layer dielectric structure in which a 50 nm thick ZnO film is sandwiched between two layers of methyl silsesquioxane sol–gel dielectric of varying thickness. A pronounced clockwise capacitance–voltage (C–V) hysteresis was observed with a memory window of 6 V. The integration with a solution-processable pentacene, 13,6-N-Sulfinylacetamodipentacene resulted in an optically transparent organic field effect transistor non-volatile memory (OFET-NVM). We have demonstrated that this OFET-NVM can be electrically programmed and erased at low voltage (± 10 V) with a threshold voltage shift of 4.0 V.     

Fabrication of nanostructure and formation of nanocrystal for non-volatile memory

In this work, we have demonstrated that the nanocrystal created by combining the self-assembled block copolymer thin film with regular semiconductor processing can be applicable to non-volatile memory device with increased charge storage capacity over planar structures. Self-assembled block copolymer thin film for nanostructures with critical dimensions below photolithographic resolution limits has been used during all experiments. Nanoporous thin film from PS-b-PMMA diblock copolymer thin film with selective removal of PMMA domains was used to fabricate nanostructure and nanocrystal. We have also reported about surface morphologies and electrical properties of the nano-needle structure formed by RIE technique. The details of nanoscale pattern of the very uniform arrays using RIE are presented. We fabricated different surface structure of nanoscale using block copolymer. We also deposited Si-rich SiNx layer using ICP-CVD on the silicon surface of nanostructure. The deposited films were studied after annealing. PL studies demonstrated nanocrystal in Si-rich SiNx film on nanostructure of silicon.     

Low-cost and nanoscale non-volatile memory concept for future silicon chips

Non-volatile 'flash' memories are key components of integrated circuits because they retain their data when power is interrupted. Despite their great commercial success, the semiconductor industry is searching for alternative non-volatile memories with improved performance and better opportunities for scaling down the size of memory cells. Here we demonstrate the feasibility of a new semiconductor memory concept. The individual memory cell is based on a narrow line of phase-change material. By sending low-power current pulses through the line, the phase-change material can be programmed reversibly between two distinguishable resistive states on a timescale of nanoseconds. Reducing the dimensions of the phase-change line to the nanometre scale improves the performance in terms of speed and power consumption. These advantages are achieved by the use of a doped-SbTe phase-change material. The simplicity of the concept promises that integration into a logic complementary metal oxide semiconductor (CMOS) process flow might be possible with only a few additional lithographic steps.     

Chalcogenide phase-change memory nanotubes for lower writing current operation

We report the synthesis and characterization of Sb-doped Te-rich nanotubes, and study their memory switching properties under the application of electrical pulses. Te-rich nanotubes display significantly low writing currents due to their small cross-sectional areas, which is desirable for power-efficient memory operation. The nanotube devices show limited resistance ratio and cyclic switching capability owing to the intrinsic properties of Te. The observed memory switching properties of this new class of nanostructured memory elements are discussed in terms of fundamental materials properties and extrinsic geometrical effects.     

Minimum voltage for threshold switching in nanoscale phase-change memory

The size scaling of the threshold voltage required for the amorphous-to-crystalline transition in phase-change memory (PCM) is investigated using planar devices incorporating individual GeTe and Sb2Te3 nanowires. We show that the scaling law governing threshold switching changes from constant field to constant voltage scaling as the amorphous domain length falls below 10 nm. This crossover is a consequence of the energetic requirement for carrier multiplication through inelastic scattering processes and indicates that the size of PCM bits can be miniaturized to the true nanometer scale.     

Impact of thermoelectric phenomena on phase-change memory performance metrics and scaling

The coupled transport of heat and electrical current, or thermoelectric phenomena, can strongly influence the temperature distribution and figures of merit for phase-change memory (PCM). This paper simulates PCM devices with careful attention to thermoelectric transport and the resulting impact on programming current during the reset operation. The electrothermal simulations consider Thomson heating within the phase-change material and Peltier heating at the electrode interface. Using representative values for the Thomson and Seebeck coefficients extracted from our past measurements of these properties, we predict a cell temperature increase of 44% and a decrease in the programming current of 16%. Scaling arguments indicate that the impact of thermoelectric phenomena becomes greater with smaller dimensions due to enhanced thermal confinement. This work estimates the scaling of this reduction in programming current as electrode contact areas are reduced down to 10 nm × 10 nm. Precise understanding of thermoelectric phenomena and their impact on device performance is a critical part of PCM design strategies.     

A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O(5-x)/TaO(2-x) bilayer structures

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.     

Core-shell heterostructured phase change nanowire multistate memory

Phase-change memory, which switches reversibly between crystalline and amorphous phases, is promising for next generation data-storage devices. In this work, we present a novel, nonbinary data-storage device using core-shell nanowires to significantly enhance memory capacity by combining two phase-change materials with different electronic and thermal properties to engineer different onsets of amorphous-crystalline transitions. Electric-field induced sequential amorphous-crystalline transition in core-shell nanowires displays three distinct electronic states with high, low, and intermediate resistances, assigned as data "0", "1", and "2".     

Crystallization kinetics of amorphous Ga-Sb films extended for phase-change memory

Performance of phase-change materials based on Ga-Te-Sb was found getting better with decreasing Te content in our earlier studies. We concerned much properties of Te-free, Sb-rich binary Ga-Sb, which has been known to possess extremely fast crystallization behavior. Non-isothermal and isothermal crystallization kinetics of amorphous Sb-rich Ga-Sb films were explored by temperature dependent electrical resistance measurements. The crystallization temperature (183 to 261 degrees C) increases with decreasing Sb content (91 to 77 at%). The activation energy and rate-factor vary with Sb contents and reach the maximum at Ga19Sb81. The kinetic exponent is smaller than 1.5 at Sb < 85 at% denoting that the mechanism is one-dimensional crystal-growth from nuclei. The temperature corresponding to 10-year data-retention, evaluated from films, is 180 degrees C (Ga19Sb81) and 137 degrees C (Ga13Sb87), respectively. We verified memory performance using test-devices made of Ga16Sb84 working at voltages with 100 ns pulse-width.     

Highly conductive interwoven carbon nanotube and silver nanowire transparent electrodes

Abstract

Electrodes fabricated using commercially available silver nanowires (AgNWs) and single walled carbon nanotubes (SWCNTs) produced sheet resistances in the range 4–24 Ω □^?1 with specular transparencies up to 82 %. Increasing the aqueous dispersibility of SWCNTs decreased the bundle size present in the film resulting in improved SWCNT surface dispersion in the films without compromising transparency or sheet resistance. In addition to providing conduction pathways between the AgNW network, the SWCNTs also provide structural support, creating stable self-supporting films. Entanglement of the AgNWs and SWCNTs was demonstrated to occur in solution prior to deposition by monitoring the transverse plasmon resonance mode of the AgNWs during processing. The interwoven AgNW/SWCNT structures show potential for use in optoelectronic applications as transparent electrodes and as an ITO replacement.     

Ultrafast switching in nanoscale phase-change random access memory with superlattice-like structures

Phase-change random access memory cells with superlattice-like (SLL) GeTe/Sb(2)Te(3) were demonstrated to have excellent scaling performance in terms of switching speed and operating voltage. In this study, the correlations between the cell size, switching speed and operating voltage of the SLL cells were identified and investigated. We found that small SLL cells can achieve faster switching speed and lower operating voltage compared to the large SLL cells. Fast amorphization and crystallization of 300 ps and 1 ns were achieved in the 40 nm SLL cells, respectively, both significantly faster than those observed in the Ge(2)Sb(2)Te(5) (GST) cells of the same cell size. 40 nm SLL cells were found to switch with low amorphization voltage of 0.9 V when pulse-widths of 5 ns were employed, which is much lower than the 1.6 V required by the GST cells of the same cell size. These effects can be attributed to the fast heterogeneous crystallization, low thermal conductivity and high resistivity of the SLL structures. Nanoscale PCRAM with SLL structure promises applications in high speed and low power memory devices.     

基于非易失存储器件的内存键值存储系统的性能研究

分析了互联网应用为满足后端存储系统高性能要求而引用的内存键值存储系统的应用特点,指出:为了永久保存数据,这些系统还需要在后端将数据从易失性的内存拷贝到慢速的非易失存储设备中;将新型的非易失存储器件(NVM)引入内存键值存储系统可减少其性能开销;根据NVM的特征,内存键值系统可采用两种架构:将NVM替代磁盘作为二级存储设备和将NVM替代DRAM直接作为主存储设备。基于上述分析,实现了两种NVM架构的内存键值存储系统,并通过实验分析,总结出了内存键值存储系统选择NVM架构的原则,这些原则可有效指导内存键值存储系统在采用当前以及未来NVM器件时,对架构的选择。其次,还通过理论和实验分析,得出了不同架构下的内存键值系统在软件层的主要开销,指出了未来针对这些系统的软件设计的优化方向。     

Performance of silicon nanocrystal non-volatile memory devices under various programming mechanisms

Non-volatile memory devices based on silicon nanocrystal synthesized with very low energy Si+ implantation are fabricated. Memory performance under various programming mechanisms including Fowler-Nordheim (FN), drain-bias channel-hot-electron (DCHE), and source-bias channel-hot-electron (SCHE) has been investigated. It is observed that the DCHE yields the largest memory window among the three programming mechanisms. The DCHE and SCHE have similar endurance characteristics, but the SCHE has a longer retention time than the DCHE. Both the DCHE and SCHE have a larger memory window, a better endurance and a longer retention time as compared to the FN. Explanations to the phenomena are given.     

Toward optimized light utilization in nanowire arrays using scalable nanosphere lithography and selected area growth

Vertically aligned, catalyst-free semiconducting nanowires hold great potential for photovoltaic applications, in which achieving scalable synthesis and optimized optical absorption simultaneously is critical. Here, we report combining nanosphere lithography (NSL) and selected area metal-organic chemical vapor deposition (SA-MOCVD) for the first time for scalable synthesis of vertically aligned gallium arsenide nanowire arrays, and surprisingly, we show that such nanowire arrays with patterning defects due to NSL can be as good as highly ordered nanowire arrays in terms of optical absorption and reflection. Wafer-scale patterning for nanowire synthesis was done using a polystyrene nanosphere template as a mask. Nanowires grown from substrates patterned by NSL show similar structural features to those patterned using electron beam lithography (EBL). Reflection of photons from the NSL-patterned nanowire array was used as a measure of the effect of defects present in the structure. Experimentally, we show that GaAs nanowires as short as 130 nm show reflection of <10% over the visible range of the solar spectrum. Our results indicate that a highly ordered nanowire structure is not necessary: despite the "defects" present in NSL-patterned nanowire arrays, their optical performance is similar to "defect-free" structures patterned by more costly, time-consuming EBL methods. Our scalable approach for synthesis of vertical semiconducting nanowires can have application in high-throughput and low-cost optoelectronic devices, including solar cells.     

Vertical nanowire electrode arrays as a scalable platform for intracellular interfacing to neuronal circuits

Deciphering the neuronal code--the rules by which neuronal circuits store and process information--is a major scientific challenge. Currently, these efforts are impeded by a lack of experimental tools that are sensitive enough to quantify the strength of individual synaptic connections and also scalable enough to simultaneously measure and control a large number of mammalian neurons with single-cell resolution. Here, we report a scalable intracellular electrode platform based on vertical nanowires that allows parallel electrical interfacing to multiple mammalian neurons. Specifically, we show that our vertical nanowire electrode arrays can intracellularly record and stimulate neuronal activity in dissociated cultures of rat cortical neurons and can also be used to map multiple individual synaptic connections. The scalability of this platform, combined with its compatibility with silicon nanofabrication techniques, provides a clear path towards simultaneous, high-fidelity interfacing with hundreds of individual neurons.