Nanocell logic gates for molecular computing

Molecular electronics seeks to build electrical devices to implement computation - logic and memory - using individual or small collections of molecules. These devices have the potential to reduce device size and fabrication costs, by several orders of magnitude, relative to conventional CMOS. However, the construction of a practical molecular computer will require the molecular switches and their related interconnect technologies to behave as large-scale diverse logic, with input/output wires scaled to molecular dimensions. It is unclear whether it is necessary or even. possible to control the precise regular placement and interconnection of these diminutive molecular systems. This paper describes genetic algorithm-based simulations of molecular device structures in a nanocell where placement and connectivity of the internal molecular switches are not specifically directed and the internal topology is generally disordered. With some simplifying assumptions, these results show that it is possible to use easily fabricated nanocells as logic devices by setting the internal molecular switch states after the topological molecular assembly is complete. Simulated logic devices include an inverter, a NAND gate, an XOR gate and a 1-bit adder. Issues of defect and fault tolerance are addressed.     

Functional stability conditions for logic devices of K- valued logic

For any input signal of logic elements (LE) which realize logical functions ofK-valued logic to be converted into any output signal, it has been shown to be sufficient that the LE have2(K- 1)different input-output characteristics without equal values of the output signal at neighboring discrete values of input signals. Sufficient conditions for stable operation of both long closed and short logical chains of elements with characteristics under consideration are formulated.     

Magnetic bubble logic

Although the literature on the bubble logic devices is limited, the concepts and device configurations are diverse. In conductor-access devices, logic can be performed by bubble transfer operations. In field-access devices, logic can be performed by providing alternative paths which are selected by interaction between bubbles. Examples include the conjugate logic gates, the resident-bubble cellular logic, and the chevron 3-3 circuits. Logic can also be performed by counting bubbles, such as in the symmetric switching function implementation. The various mechanisms for implementing bubble logic are all described by truth tables. To assess their efficiency, they are compared in terms of space and delay when they are used to implement the same logic element - a full adder. They are all comparable except for the resident-bubble cellular logic which requires excessive space and delay. However, it is important to point out that only the symmetric switching function devices offer rewrite-ability to eliminate the part number problem, and accommodation for a large number of inputs to ease interconnection and delay equalization problems.     

Grid computing and biomolecular simulation

Biomolecular computer simulations are now widely used not only in an academic setting to understand the fundamental role of molecular dynamics on biological function, but also in the industrial context to assist in drug design. In this paper, two applications of Grid computing to this area will be outlined. The first, involving the coupling of distributed computing resources to dedicated Beowulf clusters, is targeted at simulating protein conformational change using the Replica Exchange methodology. In the second, the rationale and design of a database of biomolecular simulation trajectories is described. Both applications illustrate the increasingly important role modern computational methods are playing in the life sciences.     

RSFQ logic arithmetic

Several ways to achieve local timing of Josephson-junction RSFQ (rapid single flux quantum) logic elements are proposed. Several examples of serial and parallel pipelined arithmetic blocks using various types of timing are suggested and their possible performance is discussed. Serial devices enable one to perform n-bit functions relatively slowly but using integrated circuits of a moderate integration scale, while parallel pipelined devices are more hardware-wasteful but promise extremely high productivity. The possible local and self-timing of RSFQ logic elements has been demonstrated, making it possible to construct digital blocks and complex devices operating at extremely high clock frequencies, limited only by logic delays of the RSFQ elements (~100 GHz for the present-day Nb technologies)     

Tribotronic triggers and sequential logic circuits

In this paper,a floating-gate tribotronic transistor (FGTT) based on a mobile triboelectric layer and a traditional silicon-based field-effect transistor (FET) is proposed.In the FGTT,the triboelectric charges in the layer created by contact electrification can be used to modulate charge carrier transport in the transistor.Based on the FGTTs and FETs,a tribotronic negated AND (NAND) gate that achieves mechanical-electrical coupled inputs,logic operations,and electrical level outputs is fabricated.By further integrating tribotronic NAND gates with traditional digital circuits,several basic units such as the tribotronic S-R trigger,D trigger,and T trigger have been demonstrated.Additionally,tribotronic sequential logic circuits such as registers and counters have also been integrated to enable external contact triggered storage and computation.In contrast to the conventional sequential logic units controlled by electrical signals,contact-triggered tribotronic sequential logic circuits are able to realize direct interaction and integration with the external environment.This development can lead to their potential application in micro/nano-sensors,electTomechanical storage,interactive control,and intelligent instrumentation.     

Scalable concurrent computing

This paper focusses on the challenge of building and programming scalable concurrent computers. The paper describes the inadequacy of current models of computing for programming massively parallel computers and discusses three universal models of concurrent computing — developed respectively by programming, architecture and algorithm perspectives. These models provide a powerful representation for parallel computing and are shown to be quite close. Issues in building systems architectures which efficiently represent and utilize parallel hardware resources are then discussed. Finally, we argue that by using a flexible universal programming model, an environment supporting heterogeneous programming languages can be developed.     

Scientific Grid computing

We introduce a definition of Grid computing which is adhered to throughout this Theme Issue. We compare the evolution of the World Wide Web with current aspirations for Grid computing and indicate areas that need further research and development before a generally usable Grid infrastructure becomes available. We discuss work that has been done in order to make scientific Grid computing a viable proposition, including the building of Grids, middleware developments, computational steering and visualization. We review science that has been enabled by contemporary computational Grids, and associated progress made through the widening availability of high performance computing.     

Flow simulation and high performance computing

Flow simulation is a computational tool for exploring science and technology involving flow applications. It can provide cost-effective alternatives or complements to laboratory experiments, field tests and prototyping. Flow simulation relies heavily on high performance computing (HPC). We view HPC as having two major components. One is advanced algorithms capable of accurately simulating complex, real-world problems. The other is advanced computer hardware and networking with sufficient power, memory and bandwidth to execute those simulations. While HPC enables flow simulation, flow simulation motivates development of novel HPC techniques. This paper focuses on demonstrating that flow simulation has come a long way and is being applied to many complex, real-world problems in different fields of engineering and applied sciences, particularly in aerospace engineering and applied fluid mechanics. Flow simulation has come a long way because HPC has come a long way. This paper also provides a brief review of some of the recently-developed HPC methods and tools that has played a major role in bringing flow simulation where it is today. A number of 3D flow simulations are presented in this paper as examples of the level of computational capability reached with recent HPC methods and hardware. These examples are, flow around a fighter aircraft, flow around two trains passing in a tunnel, large ram-air parachutes, flow over hydraulic structures, contaminant dispersion in a model subway station, airflow past an automobile, multiple spheres falling in a liquid-filled tube, and dynamics of a paratrooper jumping from a cargo aircraft. Sponsored by ARO, ARPA, NASA-JSC, and by the Army High Performance Computing Research Center under the auspices of the Department of the Army, Army Research Laboratory cooperative agreement number DAAH04-95-2-0003/ contract number DAAH04-95-C-0008. The content does not necessarily reflect the position or the policy of the Government, and no official endorsement should be inferred. CRAY C90 time and support for the second author was provided in part by the Minnesota Supercomputer Institute. Dedicated to the 10th anniversary of Computational Mechanics